1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmutil
.formaltest
import FHDLTestCase
5 from openpower
.decoder
.isa
.caller
import ISACaller
6 from openpower
.decoder
.power_decoder
import (create_pdecode
)
7 from openpower
.decoder
.power_decoder2
import (PowerDecode2
)
8 from openpower
.simulator
.program
import Program
9 from openpower
.decoder
.isa
.caller
import ISACaller
, SVP64State
10 from openpower
.decoder
.selectable_int
import SelectableInt
11 from openpower
.decoder
.orderedset
import OrderedSet
12 from openpower
.decoder
.isa
.all
import ISA
13 from openpower
.decoder
.isa
.test_caller
import Register
, run_tst
14 from openpower
.sv
.trans
.svp64
import SVP64Asm
15 from openpower
.consts
import SVP64CROffs
16 from copy
import deepcopy
17 from openpower
.decoder
.helpers
import fp64toselectable
18 from openpower
.decoder
.isafunctions
.double2single
import DOUBLE2SINGLE
19 from functools
import reduce
23 class DecoderTestCase(FHDLTestCase
):
25 def _check_regs(self
, sim
, expected
):
27 self
.assertEqual(sim
.gpr(i
), SelectableInt(expected
[i
], 64))
29 def test_sv_remap1(self
):
30 """>>> lst = ["svshape 2, 2, 3, 0, 0",
31 "svremap 31, 1, 2, 3, 0, 0, 0",
32 "sv.fmadds 0.v, 8.v, 16.v, 0.v"
34 REMAP fmadds FRT, FRA, FRC, FRB
36 lst
= SVP64Asm(["svshape 2, 2, 3, 0, 0",
37 "svremap 31, 1, 2, 3, 0, 0, 0",
38 "sv.fmadds 0.v, 16.v, 32.v, 0.v"
56 xf
= reduce(operator
.add
, X
)
57 yf
= reduce(operator
.add
, Y
)
58 print ("flattened X,Y")
62 # and create a linear result2, same scheme
63 #result1 = [0] * (ydim1*xdim2)
68 for i
, x
in enumerate(xf
):
69 fprs
[i
+16] = fp64toselectable(float(x
)) # X matrix
70 for i
, y
in enumerate(yf
):
71 fprs
[i
+32] = fp64toselectable(float(y
)) # Y matrix
73 #t = DOUBLE2SINGLE(fp64toselectable(t)) # convert to Power single
74 #u = DOUBLE2SINGLE(fp64toselectable(u)) # from double
76 #print ("FFT", i, "in", a, b, "coeff", c, "mul",
79 with
Program(lst
, bigendian
=False) as program
:
80 sim
= self
.run_tst_program(program
, initial_fprs
=fprs
)
81 print ("spr svshape0", sim
.spr
['SVSHAPE0'])
82 print (" xdimsz", sim
.spr
['SVSHAPE0'].xdimsz
)
83 print (" ydimsz", sim
.spr
['SVSHAPE0'].ydimsz
)
84 print (" zdimsz", sim
.spr
['SVSHAPE0'].zdimsz
)
85 print ("spr svshape1", sim
.spr
['SVSHAPE1'])
86 print ("spr svshape2", sim
.spr
['SVSHAPE2'])
87 print ("spr svshape3", sim
.spr
['SVSHAPE3'])
89 print ("i", i
, float(sim
.fpr(i
)))
90 # confirm that the results are as expected
91 #for i, (t, u) in enumerate(res):
92 # self.assertEqual(sim.fpr(i+2), t)
93 # self.assertEqual(sim.fpr(i+6), u)
95 def test_sv_remap2(self
):
96 """>>> lst = ["svshape 5, 4, 3, 0, 0",
97 "svremap 31, 1, 2, 3, 0, 0, 0, 0",
98 "sv.fmadds 0.v, 8.v, 16.v, 0.v"
100 REMAP fmadds FRT, FRA, FRC, FRB
102 lst
= SVP64Asm(["svshape 4, 3, 3, 0, 0",
103 "svremap 31, 1, 2, 3, 0, 0, 0, 0",
104 "sv.fmadds 0.v, 16.v, 32.v, 0.v"
143 # get the dimensions of the 2 matrices
149 print ("xdim2 ydim1 ydim2", xdim2
, ydim1
, ydim2
)
151 xf
= reduce(operator
.add
, X
)
152 yf
= reduce(operator
.add
, Y
)
153 print ("flattened X,Y")
157 # and create a linear result2, same scheme
158 #result1 = [0] * (ydim1*xdim2)
164 for i
, x
in enumerate(xf
):
165 fprs
[i
+16] = fp64toselectable(float(x
)) # X matrix
166 for i
, y
in enumerate(yf
):
167 fprs
[i
+32] = fp64toselectable(float(y
)) # Y matrix
169 #t = DOUBLE2SINGLE(fp64toselectable(t)) # convert to Power single
170 #u = DOUBLE2SINGLE(fp64toselectable(u)) # from double
172 #print ("FFT", i, "in", a, b, "coeff", c, "mul",
175 with
Program(lst
, bigendian
=False) as program
:
176 sim
= self
.run_tst_program(program
, initial_fprs
=fprs
)
177 print ("spr svshape0", sim
.spr
['SVSHAPE0'])
178 print (" xdimsz", sim
.spr
['SVSHAPE0'].xdimsz
)
179 print (" ydimsz", sim
.spr
['SVSHAPE0'].ydimsz
)
180 print (" zdimsz", sim
.spr
['SVSHAPE0'].zdimsz
)
181 print ("spr svshape1", sim
.spr
['SVSHAPE1'])
182 print ("spr svshape2", sim
.spr
['SVSHAPE2'])
183 print ("spr svshape3", sim
.spr
['SVSHAPE3'])
185 print ("i", i
, float(sim
.fpr(i
)))
186 # confirm that the results are as expected
187 #for i, (t, u) in enumerate(res):
188 # self.assertEqual(sim.fpr(i+2), t)
189 # self.assertEqual(sim.fpr(i+6), u)
191 def run_tst_program(self
, prog
, initial_regs
=None,
195 if initial_regs
is None:
196 initial_regs
= [0] * 32
197 simulator
= run_tst(prog
, initial_regs
, mem
=initial_mem
,
198 initial_fprs
=initial_fprs
,
209 if __name__
== "__main__":