1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmutil
.formaltest
import FHDLTestCase
5 from openpower
.decoder
.isa
.caller
import ISACaller
6 from openpower
.decoder
.power_decoder
import (create_pdecode
)
7 from openpower
.decoder
.power_decoder2
import (PowerDecode2
)
8 from openpower
.simulator
.program
import Program
9 from openpower
.decoder
.isa
.caller
import ISACaller
, SVP64State
10 from openpower
.decoder
.selectable_int
import SelectableInt
11 from openpower
.decoder
.orderedset
import OrderedSet
12 from openpower
.decoder
.isa
.all
import ISA
13 from openpower
.decoder
.isa
.test_caller
import Register
, run_tst
14 from openpower
.sv
.trans
.svp64
import SVP64Asm
15 from openpower
.consts
import SVP64CROffs
16 from copy
import deepcopy
17 from openpower
.decoder
.helpers
import fp64toselectable
18 from functools
import reduce
22 class DecoderTestCase(FHDLTestCase
):
24 def _check_regs(self
, sim
, expected
):
26 self
.assertEqual(sim
.gpr(i
), SelectableInt(expected
[i
], 64))
28 def test_sv_remap1(self
):
29 """>>> lst = ["svshape 2, 2, 3, 0, 0",
30 "svremap 31, 1, 2, 3, 0, 0, 0",
31 "sv.fmadds 0.v, 8.v, 16.v, 0.v"
33 REMAP fmadds FRT, FRA, FRC, FRB
35 lst
= SVP64Asm(["svshape 2, 2, 3, 0, 0",
36 "svremap 31, 1, 2, 3, 0, 0, 0",
37 "sv.fmadds 0.v, 16.v, 32.v, 0.v"
55 xf
= reduce(operator
.add
, X
)
56 yf
= reduce(operator
.add
, Y
)
57 print ("flattened X,Y")
61 # and create a linear result2, same scheme
62 #result1 = [0] * (ydim1*xdim2)
67 for i
, x
in enumerate(xf
):
68 fprs
[i
+16] = fp64toselectable(float(x
)) # X matrix
69 for i
, y
in enumerate(yf
):
70 fprs
[i
+32] = fp64toselectable(float(y
)) # Y matrix
72 #t = DOUBLE2SINGLE(fp64toselectable(t)) # convert to Power single
73 #u = DOUBLE2SINGLE(fp64toselectable(u)) # from double
75 #print ("FFT", i, "in", a, b, "coeff", c, "mul",
78 with
Program(lst
, bigendian
=False) as program
:
79 sim
= self
.run_tst_program(program
, initial_fprs
=fprs
)
80 print ("spr svshape0", sim
.spr
['SVSHAPE0'])
81 print (" xdimsz", sim
.spr
['SVSHAPE0'].xdimsz
)
82 print (" ydimsz", sim
.spr
['SVSHAPE0'].ydimsz
)
83 print (" zdimsz", sim
.spr
['SVSHAPE0'].zdimsz
)
84 print ("spr svshape1", sim
.spr
['SVSHAPE1'])
85 print ("spr svshape2", sim
.spr
['SVSHAPE2'])
86 print ("spr svshape3", sim
.spr
['SVSHAPE3'])
88 print ("i", i
, float(sim
.fpr(i
)))
89 # confirm that the results are as expected
90 #for i, (t, u) in enumerate(res):
91 # self.assertEqual(sim.fpr(i+2), t)
92 # self.assertEqual(sim.fpr(i+6), u)
94 def test_sv_remap2(self
):
95 """>>> lst = ["svshape 5, 4, 3, 0, 0",
96 "svremap 31, 1, 2, 3, 0, 0, 0, 0",
97 "sv.fmadds 0.v, 8.v, 16.v, 0.v"
99 REMAP fmadds FRT, FRA, FRC, FRB
101 lst
= SVP64Asm(["svshape 4, 3, 3, 0, 0",
102 "svremap 31, 1, 2, 3, 0, 0, 0, 0",
103 "sv.fmadds 0.v, 16.v, 32.v, 0.v"
142 # get the dimensions of the 2 matrices
148 print ("xdim2 ydim1 ydim2", xdim2
, ydim1
, ydim2
)
150 xf
= reduce(operator
.add
, X
)
151 yf
= reduce(operator
.add
, Y
)
152 print ("flattened X,Y")
156 # and create a linear result2, same scheme
157 #result1 = [0] * (ydim1*xdim2)
163 for i
, x
in enumerate(xf
):
164 fprs
[i
+16] = fp64toselectable(float(x
)) # X matrix
165 for i
, y
in enumerate(yf
):
166 fprs
[i
+32] = fp64toselectable(float(y
)) # Y matrix
168 #t = DOUBLE2SINGLE(fp64toselectable(t)) # convert to Power single
169 #u = DOUBLE2SINGLE(fp64toselectable(u)) # from double
171 #print ("FFT", i, "in", a, b, "coeff", c, "mul",
174 with
Program(lst
, bigendian
=False) as program
:
175 sim
= self
.run_tst_program(program
, initial_fprs
=fprs
)
176 print ("spr svshape0", sim
.spr
['SVSHAPE0'])
177 print (" xdimsz", sim
.spr
['SVSHAPE0'].xdimsz
)
178 print (" ydimsz", sim
.spr
['SVSHAPE0'].ydimsz
)
179 print (" zdimsz", sim
.spr
['SVSHAPE0'].zdimsz
)
180 print ("spr svshape1", sim
.spr
['SVSHAPE1'])
181 print ("spr svshape2", sim
.spr
['SVSHAPE2'])
182 print ("spr svshape3", sim
.spr
['SVSHAPE3'])
184 print ("i", i
, float(sim
.fpr(i
)))
185 # confirm that the results are as expected
186 #for i, (t, u) in enumerate(res):
187 # self.assertEqual(sim.fpr(i+2), t)
188 # self.assertEqual(sim.fpr(i+6), u)
190 def run_tst_program(self
, prog
, initial_regs
=None,
194 if initial_regs
is None:
195 initial_regs
= [0] * 32
196 simulator
= run_tst(prog
, initial_regs
, mem
=initial_mem
,
197 initial_fprs
=initial_fprs
,
208 if __name__
== "__main__":