src/openpower/decoder/isa/test_caller_svp64_matrix.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from openpower.decoder.isa.caller import ISACaller
   6 from openpower.decoder.power_decoder import (create_pdecode)
   7 from openpower.decoder.power_decoder2 import (PowerDecode2)
   8 from openpower.simulator.program import Program
   9 from openpower.decoder.isa.caller import ISACaller, SVP64State
  10 from openpower.decoder.selectable_int import SelectableInt
  11 from openpower.decoder.orderedset import OrderedSet
  12 from openpower.decoder.isa.all import ISA
  13 from openpower.decoder.isa.test_caller import Register, run_tst
  14 from openpower.sv.trans.svp64 import SVP64Asm
  15 from openpower.consts import SVP64CROffs
  16 from copy import deepcopy
  17 from openpower.decoder.helpers import fp64toselectable
  18 from openpower.decoder.isafunctions.double2single import DOUBLE2SINGLE
  19 from functools import reduce
  20 import operator
  21
  22
  23 class DecoderTestCase(FHDLTestCase):
  24
  25     def _check_regs(self, sim, expected):
  26         for i in range(32):
  27             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  28
  29     def test_sv_remap(self):
  30         """>>> lst = ["svremap 2, 2, 3, 0",
  31                        "sv.fmadds 0.v, 8.v, 16.v, 0.v"
  32                         ]
  33                 REMAP fmadds FRT, FRA, FRC, FRB
  34         """
  35         lst = SVP64Asm(["svremap 2, 2, 3, 0",
  36                        "sv.fmadds 0.v, 16.v, 32.v, 0.v"
  37                         ])
  38         lst = list(lst)
  39
  40         fprs = [0] * 64
  41         # 3x2 matrix
  42         X1 = [[1, 2, 3],
  43               [3, 4, 5],
  44              ]
  45         # 2x3 matrix
  46         Y1 = [[6, 7],
  47               [8, 9],
  48               [10, 11],
  49              ]
  50
  51         X = X1
  52         Y = Y1
  53
  54         xf = reduce(operator.add, X)
  55         yf = reduce(operator.add, Y)
  56         print ("flattened X,Y")
  57         print ("\t", xf)
  58         print ("\t", yf)
  59
  60         # and create a linear result2, same scheme
  61         #result1 = [0] * (ydim1*xdim2)
  62
  63
  64         res = []
  65         # store FPs
  66         for i, (x, y) in enumerate(zip(xf, yf)):
  67             fprs[i+16] = fp64toselectable(float(x))  # X matrix
  68             fprs[i+32] = fp64toselectable(float(y)) # Y matrix
  69             continue
  70             #t = DOUBLE2SINGLE(fp64toselectable(t)) # convert to Power single
  71             #u = DOUBLE2SINGLE(fp64toselectable(u)) # from double
  72             #res.append((t, u))
  73             #print ("FFT", i, "in", a, b, "coeff", c, "mul",
  74             #       mul, "res", t, u)
  75
  76         # SVSTATE (in this case, VL=12, to cover all of matrix)
  77         svstate = SVP64State()
  78         svstate.vl[0:7] = 12 # VL
  79         svstate.maxvl[0:7] = 12 # MAXVL
  80         print ("SVSTATE", bin(svstate.spr.asint()))
  81
  82         with Program(lst, bigendian=False) as program:
  83             sim = self.run_tst_program(program, svstate=svstate,
  84                                        initial_fprs=fprs)
  85             print ("spr svshape0", sim.spr['SVSHAPE0'])
  86             print ("    xdimsz", sim.spr['SVSHAPE0'].xdimsz)
  87             print ("    ydimsz", sim.spr['SVSHAPE0'].ydimsz)
  88             print ("    zdimsz", sim.spr['SVSHAPE0'].zdimsz)
  89             print ("spr svshape1", sim.spr['SVSHAPE1'])
  90             print ("spr svshape2", sim.spr['SVSHAPE2'])
  91             print ("spr svshape3", sim.spr['SVSHAPE3'])
  92             for i in range(4):
  93                 print ("i", i, float(sim.fpr(i)))
  94             # confirm that the results are as expected
  95             #for i, (t, u) in enumerate(res):
  96             #    self.assertEqual(sim.fpr(i+2), t)
  97             #    self.assertEqual(sim.fpr(i+6), u)
  98
  99     def run_tst_program(self, prog, initial_regs=None,
 100                               svstate=None,
 101                               initial_mem=None,
 102                               initial_fprs=None):
 103         if initial_regs is None:
 104             initial_regs = [0] * 32
 105         simulator = run_tst(prog, initial_regs, mem=initial_mem,
 106                                                 initial_fprs=initial_fprs,
 107                                                 svstate=svstate)
 108
 109         print ("GPRs")
 110         simulator.gpr.dump()
 111         print ("FPRs")
 112         simulator.fpr.dump()
 113
 114         return simulator
 115
 116
 117 if __name__ == "__main__":
 118     unittest.main()