src/openpower/decoder/isa/test_caller_svp64_pack.py

   1 from nmigen import Module, Signal
   2 from nmigen.sim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from openpower.decoder.isa.caller import ISACaller
   6 from openpower.decoder.power_decoder import (create_pdecode)
   7 from openpower.decoder.power_decoder2 import (PowerDecode2)
   8 from openpower.simulator.program import Program
   9 from openpower.decoder.isa.caller import ISACaller, SVP64State, CRFields
  10 from openpower.decoder.selectable_int import SelectableInt
  11 from openpower.decoder.orderedset import OrderedSet
  12 from openpower.decoder.isa.all import ISA
  13 from openpower.decoder.isa.test_caller import Register, run_tst
  14 from openpower.sv.trans.svp64 import SVP64Asm
  15 from openpower.consts import SVP64CROffs
  16 from copy import deepcopy
  17
  18 class DecoderTestCase(FHDLTestCase):
  19
  20     def _check_regs(self, sim, expected):
  21         print ("GPR")
  22         sim.gpr.dump()
  23         for i in range(32):
  24             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  25
  26     def test_svstep_pack(self):
  27         """tests pack mode
  28         """
  29         lst = SVP64Asm(["setvl 0, 0, 4, 0, 1, 1",
  30                         "svstep 0, 15, 0",  # set dst-pack
  31                         "sv.svstep./vec2 *0, 5, 1", # svstep get vector srcstep
  32                         "sv.svstep./vec2 *8, 6, 1", # svstep get vector dststep
  33                         "sv.svstep./vec2 *16, 7, 1", # svstep get src substep
  34                         "sv.svstep./vec2 *24, 8, 1", # svstep get dst substep
  35                         ])
  36         lst = list(lst)
  37
  38         # SVSTATE
  39         svstate = SVP64State()
  40         #svstate.vl = 2 # VL
  41         #svstate.maxvl = 2 # MAXVL
  42         print ("SVSTATE", bin(svstate.asint()))
  43
  44         with Program(lst, bigendian=False) as program:
  45             sim = self.run_tst_program(program, svstate=svstate)
  46             print ("SVSTATE after", bin(sim.svstate.asint()))
  47             print ("        vl", bin(sim.svstate.vl))
  48             print ("        mvl", bin(sim.svstate.maxvl))
  49             print ("    srcstep", bin(sim.svstate.srcstep))
  50             print ("    dststep", bin(sim.svstate.dststep))
  51             print ("     vfirst", bin(sim.svstate. vfirst))
  52             sim.gpr.dump()
  53             self.assertEqual(sim.svstate.vl, 4)
  54             self.assertEqual(sim.svstate.maxvl, 4)
  55             self.assertEqual(sim.svstate.srcstep, 0)
  56             self.assertEqual(sim.svstate.dststep, 0)
  57             for j in range(2):
  58                 for i in range(4):
  59                     offs = j*4+i
  60                     skew = i*2+j
  61                     self.assertEqual(sim.gpr(0+offs), SelectableInt(i, 64))
  62                     self.assertEqual(sim.gpr(8+skew), SelectableInt(i, 64))
  63                     self.assertEqual(sim.gpr(16+offs), SelectableInt(j, 64))
  64                     self.assertEqual(sim.gpr(24+skew), SelectableInt(j, 64))
  65             self.assertEqual(sim.svstate.vfirst, 0)
  66             CR0 = sim.crl[0]
  67             print("      CR0", bin(CR0.get_range().value))
  68             self.assertEqual(CR0[CRFields.EQ], 0)
  69             self.assertEqual(CR0[CRFields.LT], 0)
  70             self.assertEqual(CR0[CRFields.GT], 0)
  71             self.assertEqual(CR0[CRFields.SO], 1)
  72
  73     def test_svstep_unpack(self):
  74         """tests unpack mode
  75         oh ha ha very funny,  cannot use sv.srcstep on unpack:
  76         the dest indices are themselves put *into*
  77         the vector output in the order of their own values.
  78         """
  79         lst = SVP64Asm(["setvl 0, 0, 4, 0, 1, 1",
  80                         "svstep 0, 14, 0",  # set src-pack
  81                         "sv.ori/vec2 *0, *32, 0", # copy 01234567 to new order
  82                         ])
  83         lst = list(lst)
  84
  85         # SVSTATE
  86         svstate = SVP64State()
  87         #svstate.vl = 2 # VL
  88         #svstate.maxvl = 2 # MAXVL
  89         print ("SVSTATE", bin(svstate.asint()))
  90
  91         initial_regs = [0]*64
  92         for i in range(8):
  93             initial_regs[32+i] = i
  94
  95         with Program(lst, bigendian=False) as program:
  96             sim = self.run_tst_program(program, initial_regs, svstate=svstate)
  97             print ("SVSTATE after", bin(sim.svstate.asint()))
  98             print ("        vl", bin(sim.svstate.vl))
  99             print ("        mvl", bin(sim.svstate.maxvl))
 100             print ("    srcstep", bin(sim.svstate.srcstep))
 101             print ("    dststep", bin(sim.svstate.dststep))
 102             print ("     vfirst", bin(sim.svstate. vfirst))
 103             sim.gpr.dump()
 104             self.assertEqual(sim.svstate.vl, 4)
 105             self.assertEqual(sim.svstate.maxvl, 4)
 106             self.assertEqual(sim.svstate.srcstep, 0)
 107             self.assertEqual(sim.svstate.dststep, 0)
 108             for j in range(2):
 109                 for i in range(4):
 110                     offs = j*4+i
 111                     skew = i*2+j
 112                     self.assertEqual(sim.gpr(0+skew), SelectableInt(offs, 64))
 113
 114     def test_svstep_pack2(self):
 115         """tests pack mode
 116         """
 117         lst = SVP64Asm(["setvl 0, 0, 4, 0, 1, 1",
 118                         "svstep 0, 15, 0",  # set dst-pack
 119                         "sv.ori/vec2 *0, *32, 0", # copy 01234567 to new order
 120                         ])
 121         lst = list(lst)
 122
 123         # SVSTATE
 124         svstate = SVP64State()
 125         #svstate.vl = 2 # VL
 126         #svstate.maxvl = 2 # MAXVL
 127         print ("SVSTATE", bin(svstate.asint()))
 128
 129         initial_regs = [0]*64
 130         for i in range(8):
 131             initial_regs[32+i] = i
 132
 133         with Program(lst, bigendian=False) as program:
 134             sim = self.run_tst_program(program, initial_regs, svstate=svstate)
 135             print ("SVSTATE after", bin(sim.svstate.asint()))
 136             print ("        vl", bin(sim.svstate.vl))
 137             print ("        mvl", bin(sim.svstate.maxvl))
 138             print ("    srcstep", bin(sim.svstate.srcstep))
 139             print ("    dststep", bin(sim.svstate.dststep))
 140             print ("     vfirst", bin(sim.svstate. vfirst))
 141             sim.gpr.dump()
 142             self.assertEqual(sim.svstate.vl, 4)
 143             self.assertEqual(sim.svstate.maxvl, 4)
 144             self.assertEqual(sim.svstate.srcstep, 0)
 145             self.assertEqual(sim.svstate.dststep, 0)
 146             for j in range(2):
 147                 for i in range(4):
 148                     offs = j*4+i
 149                     skew = i*2+j
 150                     self.assertEqual(sim.gpr(0+offs), SelectableInt(skew, 64))
 151
 152     def test_svstep_predicate_pack(self):
 153         """tests pack mode with a predicate
 154         """
 155         lst = SVP64Asm(["setvl 0, 0, 4, 0, 1, 1",
 156                         "svstep 0, 15, 0",  # set dst-pack
 157                         "sv.ori/vec2/m=r3 *8, *16, 0",
 158                         ])
 159         lst = list(lst)
 160
 161         # SVSTATE
 162         svstate = SVP64State()
 163         #svstate.vl = 2 # VL
 164         #svstate.maxvl = 2 # MAXVL
 165         print ("SVSTATE", bin(svstate.asint()))
 166
 167         mask = 0b0110
 168         initial_regs = [0xffffffff]*64
 169         initial_regs[3] = mask
 170         for i in range(8):
 171             initial_regs[16+i] = i
 172
 173         with Program(lst, bigendian=False) as program:
 174             sim = self.run_tst_program(program, initial_regs, svstate=svstate)
 175             print ("SVSTATE after", bin(sim.svstate.asint()))
 176             print ("        vl", bin(sim.svstate.vl))
 177             print ("        mvl", bin(sim.svstate.maxvl))
 178             print ("    srcstep", bin(sim.svstate.srcstep))
 179             print ("    dststep", bin(sim.svstate.dststep))
 180             print ("     vfirst", bin(sim.svstate. vfirst))
 181             sim.gpr.dump()
 182             self.assertEqual(sim.svstate.vl, 4)
 183             self.assertEqual(sim.svstate.maxvl, 4)
 184             self.assertEqual(sim.svstate.srcstep, 0)
 185             self.assertEqual(sim.svstate.dststep, 0)
 186
 187             # sigh, in sz=0 mode you end up skipping.  have to
 188             # take that into account, extracting the expected values
 189             to_expect = []
 190             for j in range(2):
 191                 for i in range(4):
 192                     offs = j*4+i
 193                     skew = i*2+j
 194                     if mask & (1<<(skew>>1)):
 195                         to_expect.append(skew)
 196
 197             print ("expected", to_expect)
 198             for j in range(2):
 199                 for i in range(4):
 200                     offs = j*4+i
 201                     skew = i*2+j
 202                     if mask & (1<<(offs>>1)):
 203                         expected = SelectableInt(to_expect.pop(0), 64)
 204                     else:
 205                         expected = SelectableInt(0xffffffff, 64)
 206                     print ("checking", hex(expected.value), "at", offs)
 207                     self.assertEqual(sim.gpr(8+offs), expected)
 208
 209     def test_svstep_unpack(self):
 210         """tests unpack mode with predicate
 211         """
 212         lst = SVP64Asm(["setvl 0, 0, 4, 0, 1, 1",
 213                         "svstep 0, 14, 0",  # set src-pack
 214                         "sv.ori/vec2/m=r3 *8, *16, 0", # copy with mask
 215                         ])
 216         lst = list(lst)
 217
 218         # SVSTATE
 219         svstate = SVP64State()
 220         #svstate.vl = 2 # VL
 221         #svstate.maxvl = 2 # MAXVL
 222         print ("SVSTATE", bin(svstate.asint()))
 223
 224         mask = 0b0101
 225         initial_regs = [0xffffffff]*64
 226         initial_regs[3] = mask
 227         for i in range(8):
 228             initial_regs[16+i] = i
 229
 230         with Program(lst, bigendian=False) as program:
 231             sim = self.run_tst_program(program, initial_regs, svstate=svstate)
 232             print ("SVSTATE after", bin(sim.svstate.asint()))
 233             print ("        vl", bin(sim.svstate.vl))
 234             print ("        mvl", bin(sim.svstate.maxvl))
 235             print ("    srcstep", bin(sim.svstate.srcstep))
 236             print ("    dststep", bin(sim.svstate.dststep))
 237             print ("     vfirst", bin(sim.svstate. vfirst))
 238             sim.gpr.dump()
 239             self.assertEqual(sim.svstate.vl, 4)
 240             self.assertEqual(sim.svstate.maxvl, 4)
 241             self.assertEqual(sim.svstate.srcstep, 0)
 242             self.assertEqual(sim.svstate.dststep, 0)
 243
 244             # sigh, in sz=0 mode you end up skipping.  have to
 245             # take that into account, extracting the expected values
 246             to_expect = []
 247             for j in range(2):
 248                 for i in range(4):
 249                     offs = j*4+i
 250                     skew = i*2+j
 251                     if mask & (1<<(offs>>1)):
 252                         to_expect.append(offs)
 253
 254             print ("expected", to_expect)
 255             for j in range(2):
 256                 for i in range(4):
 257                     offs = j*4+i
 258                     skew = i*2+j
 259                     if mask & (1<<(skew>>1)):
 260                         expected = SelectableInt(to_expect.pop(0), 64)
 261                     else:
 262                         expected = SelectableInt(0xffffffff, 64)
 263                     self.assertEqual(sim.gpr(8+skew), expected)
 264
 265     def run_tst_program(self, prog, initial_regs=None,
 266                               svstate=None,
 267                               initial_sprs=None):
 268         if initial_regs is None:
 269             initial_regs = [0] * 32
 270         simulator = run_tst(prog, initial_regs, svstate=svstate,
 271                               initial_sprs=initial_sprs)
 272         simulator.gpr.dump()
 273         return simulator
 274
 275
 276 if __name__ == "__main__":
 277     unittest.main()
 278