src/openpower/decoder/isa/test_caller_svp64_subvl.py

   1 import unittest
   2 from copy import deepcopy
   3
   4 from nmutil.formaltest import FHDLTestCase
   5 from openpower.decoder.isa.caller import SVP64State
   6 from openpower.decoder.isa.test_caller import run_tst
   7 from openpower.decoder.selectable_int import SelectableInt
   8 from openpower.simulator.program import Program
   9 from openpower.sv.trans.svp64 import SVP64Asm
  10
  11
  12 class DecoderTestCase(FHDLTestCase):
  13
  14     def _check_regs(self, sim, expected):
  15         for i in range(32):
  16             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  17
  18     def test_sv_add_intpred(self):
  19         # adds, integer predicated mask r3=0b10
  20         #       1 = 5 + 9   => not to be touched (skipped)
  21         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
  22         #   reg num        0 1 2 3 4 5 6 7 8 9 10 11
  23         #   src r3=0b10      | |     N N Y Y N N Y Y
  24         #                    | |         | |     | |
  25         #                    | | +-------+-|-add-+ |
  26         #                    | | | +-------+-add---+
  27         #                    | | | |
  28         #   dest r3=0b10     N N Y Y
  29         isa = SVP64Asm(['sv.add/vec2/m=r30 *1, *5, *9'
  30                         ])
  31         lst = list(isa)
  32         print("listing", lst)
  33
  34         # initial values in GPR regfile
  35         initial_regs = [0] * 32
  36         initial_regs[1] = 0xbeef   # not to be altered
  37         initial_regs[2] = 0xefbe  # not to be altered
  38         initial_regs[3] = 0xebbe
  39         initial_regs[4] = 0xbeeb
  40         initial_regs[30] = 0b10   # predicate mask
  41         initial_regs[9] = 0x1234
  42         initial_regs[10] = 0x1111
  43         initial_regs[11] = 0x7eee
  44         initial_regs[12] = 0x2aaa
  45         initial_regs[5] = 0x4321
  46         initial_regs[6] = 0x2223
  47         initial_regs[7] = 0x4321
  48         initial_regs[8] = 0x2223
  49         # SVSTATE (in this case, VL=2)
  50         svstate = SVP64State()
  51         svstate.vl = 2  # VL
  52         svstate.maxvl = 2  # MAXVL
  53         print("SVSTATE", bin(svstate.asint()))
  54         # copy before running
  55         expected_regs = deepcopy(initial_regs)
  56         expected_regs[3] = initial_regs[7]+initial_regs[11]
  57         expected_regs[4] = initial_regs[8]+initial_regs[12]
  58
  59         with Program(lst, bigendian=False) as program:
  60             sim = self.run_tst_program(program, initial_regs, svstate)
  61             self._check_regs(sim, expected_regs)
  62
  63     def run_tst_program(self, prog, initial_regs=None,
  64                         svstate=None,
  65                         initial_cr=0):
  66         if initial_regs is None:
  67             initial_regs = [0] * 32
  68         simulator = run_tst(prog, initial_regs, svstate=svstate,
  69                             initial_cr=initial_cr)
  70         simulator.gpr.dump()
  71         return simulator
  72
  73
  74 if __name__ == "__main__":
  75     unittest.main()