src/openpower/decoder/isa/test_caller_svshape2.py

   1 """SVP64 unit test for svshape2
   2 svshape2 SVo,yx,rmm,SVd,sk,mm
   3 """
   4 import unittest
   5 from copy import deepcopy
   6
   7 from nmutil.formaltest import FHDLTestCase
   8 from openpower.decoder.isa.caller import SVP64State
   9 from openpower.decoder.isa.test_caller import run_tst
  10 from openpower.decoder.selectable_int import SelectableInt
  11 from openpower.simulator.program import Program
  12 from openpower.sv.trans.svp64 import SVP64Asm
  13
  14
  15 class SVSTATETestCase(FHDLTestCase):
  16
  17     def _check_regs(self, sim, expected):
  18         print("GPR")
  19         sim.gpr.dump()
  20         for i in range(32):
  21             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64),
  22                              "GPR %d %x expected %x" % (i, sim.gpr(i).value, expected[i]))
  23
  24     def test_0_sv_shape2(self):
  25         """sets VL=10 (via SVSTATE) then does svshape mm=0, checks SPRs after
  26         """
  27         isa = SVP64Asm(['svshape2 12, 1, 15, 5, 0, 0'
  28                         ])
  29         lst = list(isa)
  30         print("listing", lst)
  31
  32         # initial values in GPR regfile
  33         initial_regs = [0] * 32
  34         initial_regs[9] = 0x1234
  35         initial_regs[10] = 0x1111
  36         initial_regs[5] = 0x4321
  37         initial_regs[6] = 0x2223
  38
  39         # SVSTATE vl=10
  40         svstate = SVP64State()
  41         svstate.vl = 10  # VL
  42         svstate.maxvl = 10  # MAXVL
  43         print("SVSTATE", bin(svstate.asint()))
  44
  45         # copy before running
  46         expected_regs = deepcopy(initial_regs)
  47         #expected_regs[1] = 0x3334
  48
  49         with Program(lst, bigendian=False) as program:
  50             sim = self.run_tst_program(program, initial_regs, svstate=svstate)
  51             self._check_regs(sim, expected_regs)
  52
  53             print(sim.spr)
  54             SVSHAPE0 = sim.spr['SVSHAPE0']
  55             print("SVSTATE after", bin(sim.svstate.asint()))
  56             print("        vl", bin(sim.svstate.vl))
  57             print("        mvl", bin(sim.svstate.maxvl))
  58             print("    srcstep", bin(sim.svstate.srcstep))
  59             print("    dststep", bin(sim.svstate.dststep))
  60             print("      RMpst", bin(sim.svstate.RMpst))
  61             print("       SVme", bin(sim.svstate.SVme))
  62             print("        mo0", bin(sim.svstate.mo0))
  63             print("        mo1", bin(sim.svstate.mo1))
  64             print("        mi0", bin(sim.svstate.mi0))
  65             print("        mi1", bin(sim.svstate.mi1))
  66             print("        mi2", bin(sim.svstate.mi2))
  67             print("STATE0     ", SVSHAPE0)
  68             print("STATE0 offs", SVSHAPE0.offset)
  69             print("STATE0 xdim", SVSHAPE0.xdimsz)
  70             print("STATE0 ydim", SVSHAPE0.ydimsz)
  71             print("STATE0 skip", bin(SVSHAPE0.skip))
  72             print("STATE0  inv", SVSHAPE0.invxyz)
  73             print("STATE0order", SVSHAPE0.order)
  74             self.assertEqual(SVSHAPE0.xdimsz, 5)  # set
  75             self.assertEqual(SVSHAPE0.ydimsz, 2)  # calculated from MVL/xdimsz
  76             self.assertEqual(SVSHAPE0.skip, 0)   # no skip
  77             # (no inversion possible)
  78             self.assertEqual(SVSHAPE0.invxyz, [0, 0, 0])
  79             self.assertEqual(SVSHAPE0.offset, 12)
  80             self.assertEqual(SVSHAPE0.order, (1, 0, 2))  # y,x(,z)
  81             self.assertEqual(sim.svstate.RMpst, 0)  # mm=0 so persist=0
  82             self.assertEqual(sim.svstate.SVme, 0b01111)  # same as rmm
  83             # rmm is 0b01111 which means mi0=0 mi1=1 mi2=2 mo0=3 mo1=0
  84             self.assertEqual(sim.svstate.mi0, 0)
  85             self.assertEqual(sim.svstate.mi1, 1)
  86             self.assertEqual(sim.svstate.mi2, 2)
  87             self.assertEqual(sim.svstate.mo0, 3)
  88             self.assertEqual(sim.svstate.mo1, 0)
  89
  90     def test_1_sv_offset2_add(self):
  91         """sets VL=6 (via SVSTATE) then does modulo 3 svindex, and an add.
  92
  93         only RA is re-mapped via svshape2, not RB or RT, but an offset of
  94         1 is included on RA.
  95
  96         whilst this does not look useful for sv.add because it is EXTRA3
  97         encoded, it *is* a useful demo for anything EXTRA2-encoded which
  98         only has even-numbered GPR/FPR vector register accessibility.
  99         set the offset to compensate for EXTRA2 being so restricted.
 100         """
 101         # set some parameters here with comments
 102         offs = 1  # an offset of 1
 103         mod = 3  # modulo 3 on the range
 104         VL = 6   # RB will go 0..5 but RA will go 1 2 3 1 2 3
 105         isa = SVP64Asm(['svshape2 %d, 0, 1, %d, 0, 0' % (offs, mod),
 106                         'sv.add *8, *0, *0',
 107                         ])
 108         lst = list(isa)
 109         print("listing", lst)
 110
 111         # initial values in GPR regfile
 112         initial_regs = [0] * 32
 113         for i in range(VL):
 114             initial_regs[i] = i
 115
 116         # SVSTATE vl=10
 117         svstate = SVP64State()
 118         svstate.vl = VL  # VL
 119         svstate.maxvl = VL  # MAXVL
 120         print("SVSTATE", bin(svstate.asint()))
 121
 122         # copy before running and compute the expected results
 123         expected_regs = deepcopy(initial_regs)
 124         for i in range(VL):
 125             RA = initial_regs[offs+(i % mod)]  # modulo but also offset
 126             RB = initial_regs[0+i]             # RB is not re-mapped
 127             expected_regs[i+8] = RA+RB
 128             print("expected", i, expected_regs[i+8])
 129
 130         with Program(lst, bigendian=False) as program:
 131             sim = self.run_tst_program(program, initial_regs, svstate=svstate)
 132
 133             print(sim.spr)
 134             SVSHAPE0 = sim.spr['SVSHAPE0']
 135             SVSHAPE1 = sim.spr['SVSHAPE1']
 136             SVSHAPE2 = sim.spr['SVSHAPE2']
 137             SVSHAPE3 = sim.spr['SVSHAPE3']
 138             print("SVSTATE after", bin(sim.svstate.asint()))
 139             print("        vl", bin(sim.svstate.vl))
 140             print("        mvl", bin(sim.svstate.maxvl))
 141             print("    srcstep", bin(sim.svstate.srcstep))
 142             print("    dststep", bin(sim.svstate.dststep))
 143             print("      RMpst", bin(sim.svstate.RMpst))
 144             print("       SVme", bin(sim.svstate.SVme))
 145             print("        mo0", bin(sim.svstate.mo0))
 146             print("        mo1", bin(sim.svstate.mo1))
 147             print("        mi0", bin(sim.svstate.mi0))
 148             print("        mi1", bin(sim.svstate.mi1))
 149             print("        mi2", bin(sim.svstate.mi2))
 150             print("STATE0     ", SVSHAPE0)
 151             print("STATE0 offs", SVSHAPE0.offset)
 152             print("STATE0 xdim", SVSHAPE0.xdimsz)
 153             print("STATE0 ydim", SVSHAPE0.ydimsz)
 154             print("STATE0 skip", bin(SVSHAPE0.skip))
 155             print("STATE0  inv", SVSHAPE0.invxyz)
 156             print("STATE0order", SVSHAPE0.order)
 157             print(sim.gpr.dump())
 158             self.assertEqual(SVSHAPE0.xdimsz, 3)  # set
 159             self.assertEqual(SVSHAPE0.ydimsz, 1)  # calculated from MVL/xdimsz
 160             self.assertEqual(SVSHAPE0.skip, 0)   # no skip
 161             # (no inversion possible)
 162             self.assertEqual(SVSHAPE0.invxyz, [0, 0, 0])
 163             self.assertEqual(SVSHAPE0.offset, 1)
 164             self.assertEqual(SVSHAPE0.order, (0, 1, 2))  # x,y(,z)
 165             self.assertEqual(sim.svstate.RMpst, 0)  # mm=0 so persist=0
 166             self.assertEqual(sim.svstate.SVme, 0b00001)  # same as rmm
 167             # SVSHAPE1-3 zero
 168             self.assertEqual(SVSHAPE1, 0)
 169             self.assertEqual(SVSHAPE2, 0)
 170             self.assertEqual(SVSHAPE3, 0)
 171             # rmm is 0b00001 which means mi0=0 and all others inactive (0)
 172             self.assertEqual(sim.svstate.mi0, 0)
 173             self.assertEqual(sim.svstate.mi1, 0)
 174             self.assertEqual(sim.svstate.mi2, 0)
 175             self.assertEqual(sim.svstate.mo0, 0)
 176             self.assertEqual(sim.svstate.mo1, 0)
 177             self._check_regs(sim, expected_regs)
 178
 179     def run_tst_program(self, prog, initial_regs=None,
 180                         svstate=None):
 181         if initial_regs is None:
 182             initial_regs = [0] * 32
 183         simulator = run_tst(prog, initial_regs, svstate=svstate)
 184         simulator.gpr.dump()
 185         return simulator
 186
 187
 188 if __name__ == "__main__":
 189     unittest.main()