1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmutil
.formaltest
import FHDLTestCase
5 from openpower
.decoder
.isa
.caller
import ISACaller
6 from openpower
.decoder
.power_decoder
import (create_pdecode
)
7 from openpower
.decoder
.power_decoder2
import (PowerDecode2
)
8 from openpower
.simulator
.program
import Program
9 from openpower
.decoder
.isa
.caller
import ISACaller
, SVP64State
10 from openpower
.decoder
.selectable_int
import SelectableInt
11 from openpower
.decoder
.orderedset
import OrderedSet
12 from openpower
.decoder
.isa
.all
import ISA
13 from openpower
.decoder
.isa
.test_caller
import Register
, run_tst
14 from copy
import deepcopy
15 from openpower
.sv
.trans
.svp64
import SVP64Asm
16 from openpower
.decoder
.helpers
import fp64toselectable
17 from openpower
.decoder
.isafunctions
.double2single
import DOUBLE2SINGLE
21 class FPTranscendentalsTestCase(FHDLTestCase
):
23 def _check_regs(self
, sim
, expected_int
, expected_fpr
):
25 self
.assertEqual(sim
.gpr(i
), SelectableInt(expected
[i
], 64))
27 self
.assertEqual(sim
.fpr(i
), SelectableInt(expected_fpr
[i
], 64))
29 def tst_fp_sins_coss(self
):
30 """>>> lst = ["fsins 1, 2",
34 lst
= SVP64Asm(["fsins 1, 2",
39 with
Program(lst
, bigendian
=False) as program
:
41 for i
in range(-8, 9):
42 a
= math
.pi
* (i
/ 8.0) * 2.0
43 fprs
[2] = fp64toselectable(a
)
46 a1
= fp64toselectable(a
) # convert to Power single
47 t
= DOUBLE2SINGLE(fp64toselectable(t
)) # convert to Power single
48 u
= DOUBLE2SINGLE(fp64toselectable(u
)) # convert to Power single
51 sim
= self
.run_tst_program(program
, initial_fprs
=fprs
)
52 print("FPR 1", sim
.fpr(1))
53 print("FPR 2", sim
.fpr(2))
54 print("FPR 3", sim
.fpr(3))
55 self
.assertEqual(sim
.fpr(2), SelectableInt(a1
, 64))
56 self
.assertEqual(sim
.fpr(1), SelectableInt(t
, 64))
57 self
.assertEqual(sim
.fpr(3), SelectableInt(u
, 64))
59 def test_fp_coss_cvt(self
):
64 this is a base / proving-ground for the more complex SVP64
65 variant in test_caller_svp64_dct.py:
66 test_sv_remap_dct_cos_precompute_8
68 lst
= SVP64Asm(["std 1, 0(0)",
71 "fadds 0, 0, 3", # plus 0.5
72 "fmuls 0, 0, 1", # times PI
73 "fdivs 0, 0, 2", # div 4.0
78 with
Program(lst
, bigendian
=False) as program
:
82 fprs
[3] = fp64toselectable(0.5) # 0.5
83 fprs
[1] = fp64toselectable(math
.pi
) # pi
84 fprs
[2] = fp64toselectable(4.0) # 4.0
85 #for i in range(-8, 9):
87 a
= math
.pi
* ((i
+0.5) / 4.0)
89 a1
= DOUBLE2SINGLE(fp64toselectable(a
)) # to Power single
92 u
= DOUBLE2SINGLE(fp64toselectable(u
)) # convert to Power single
95 sim
= self
.run_tst_program(program
, gprs
, initial_fprs
=fprs
)
96 print("FPR 0", sim
.fpr(0), float(sim
.fpr(0)))
97 print("FPR 1", sim
.fpr(1), float(sim
.fpr(1)))
98 print("FPR 2", sim
.fpr(2), float(sim
.fpr(2)))
99 print("FPR 3", sim
.fpr(3), float(sim
.fpr(3)))
100 print("FPR 4", sim
.fpr(4), float(sim
.fpr(4)))
101 # sign should not do this, but hey
102 actual_r
= float(sim
.fpr(0))
103 expected_r
= float(a1
)
104 err
= abs(actual_r
- expected_r
) / expected_r
105 self
.assertTrue(err
< 1e-6)
106 actual_r
= float(sim
.fpr(4))
107 expected_r
= float(u
)
108 err
= abs(actual_r
- expected_r
) / expected_r
109 self
.assertTrue(err
< 1e-6)
111 def run_tst_program(self
, prog
, initial_regs
=None,
114 if initial_regs
is None:
115 initial_regs
= [0] * 32
116 simulator
= run_tst(prog
, initial_regs
, mem
=initial_mem
,
117 initial_fprs
=initial_fprs
)
125 if __name__
== "__main__":