src/openpower/decoder/isa/test_syscall.py

   1 import os
   2 import tempfile
   3 import unittest
   4
   5 from nmutil.formaltest import FHDLTestCase
   6
   7 from openpower.consts import MSRb
   8 from openpower.consts import PIb
   9 from openpower.consts import DEFAULT_MSR
  10 from openpower.decoder.helpers import ne
  11 from openpower.decoder.isa.test_runner import run_tst
  12 from openpower.test.runner import TestRunnerBase
  13 from openpower.simulator.program import Program
  14 from openpower.decoder.selectable_int import SelectableInt
  15 from openpower.decoder.selectable_int import selectconcat as concat
  16
  17
  18 class SyscallTestCase(FHDLTestCase):
  19     def run_tst_program(self, prog,
  20             initial_regs=None):
  21         if initial_regs is None:
  22             initial_regs=([0] * 32)
  23         initial_regs = list(initial_regs)
  24         initial_sprs = {
  25             'SRR0': 0xFFFF_FFFF_FFFF_FFFF,
  26             'SRR1': 0xFFFF_FFFF_FFFF_FFFF,
  27         }
  28         sim = run_tst(prog, initial_regs,
  29             initial_sprs=initial_sprs,
  30             initial_msr=DEFAULT_MSR,
  31             use_syscall_emu=True)
  32         sim.gpr.dump()
  33
  34         MSR = SelectableInt(DEFAULT_MSR, 64)
  35         SRR1 = SelectableInt(0xFFFF_FFFF_FFFF_FFFF, 64)
  36
  37         # sc instruction
  38         # 4.3.1 System Linkage Instructions
  39         # 7.5.14 System Call Interrupt
  40         SRR1[33:37] = 0
  41         SRR1[42:48] = 0
  42         SRR1[0:33] = MSR[0:33]
  43         SRR1[37:42] = MSR[37:42]
  44         SRR1[48:64] = MSR[48:64]
  45         SRR1[PIb.TRAP] = 1
  46
  47         # rfid instruction
  48         MSR[51] = MSR[3] & SRR1[51] | ~MSR[3] & MSR[51]
  49         MSR[3] = MSR[3] & SRR1[3]
  50         if ne(MSR[29:32], SelectableInt(value=0x2, bits=3)) | ne(SRR1[29:32],
  51             SelectableInt(value=0x0, bits=3)):
  52             MSR[29:32] = SRR1[29:32]
  53         MSR[48] = SRR1[48] | SRR1[49]
  54         MSR[58] = SRR1[58] | SRR1[49]
  55         MSR[59] = SRR1[59] | SRR1[49]
  56         MSR[0:3] = SRR1[0:3]
  57         MSR[4:29] = SRR1[4:29]
  58         MSR[32] = SRR1[32]
  59         MSR[37:42] = SRR1[37:42]
  60         MSR[49:51] = SRR1[49:51]
  61         MSR[52:58] = SRR1[52:58]
  62         MSR[60:64] = SRR1[60:64]
  63
  64         self.assertEqual(sim.spr['SRR0'], 8)    # PC to return to: CIA+4
  65         self.assertEqual(sim.spr['SRR1'], SRR1) # MSR to restore after sc return
  66
  67         # FIXME this is currently hardcoded to the same way as in test_trap.py.
  68         # However, I'd have expected 0x9000000000002903, not 0x9000000000000001.
  69         MSR = SelectableInt(0x9000000000000001, 64)
  70         self.assertEqual(sim.msr, MSR)          # MSR changed to this by sc/trap
  71
  72         print("SYSCALL SRR1", hex(int(SRR1)), hex(int(sim.spr['SRR1'])))
  73         print("SYSCALL  MSR", hex(int(MSR)), hex(int(sim.msr)), hex(DEFAULT_MSR))
  74         return sim
  75
  76     def test_sc_getpid(self):
  77         lst = ["sc 0"]
  78         initial_regs = [0] * 32
  79         initial_regs[0] = 20 # getpid
  80         with Program(lst, bigendian=False) as program:
  81             sim = self.run_tst_program(program, initial_regs)
  82             self.assertEqual(sim.gpr(3), os.getpid())
  83
  84     def test_sc_getuid(self):
  85         lst = ["sc 0"]
  86         initial_regs = [0] * 32
  87         initial_regs[0] = 24 # getuid
  88         with Program(lst, bigendian=False) as program:
  89             sim = self.run_tst_program(program, initial_regs)
  90             self.assertEqual(sim.gpr(3), os.getuid())
  91
  92     def test_sc_dup(self):
  93         with tempfile.TemporaryFile(mode="wb+") as stream:
  94             msg0 = b"hello, world!"
  95             stream.write(msg0)
  96             stream.seek(0)
  97             fd0 = stream.fileno()
  98             st0 = os.fstat(fd0)
  99
 100             lst = ["sc 0"]
 101             initial_regs = [0] * 32
 102             initial_regs[0] = 41 # dup
 103             initial_regs[3] = fd0
 104             with Program(lst, bigendian=False) as program:
 105                 sim = self.run_tst_program(program, initial_regs)
 106                 fd1 = int(sim.gpr(3))
 107                 st1 = os.fstat(fd1)
 108                 msg1 = os.read(fd1, 42)
 109                 self.assertEqual(st0, st1)
 110                 self.assertEqual(msg0, msg1)
 111                 os.close(fd1)
 112
 113
 114 if __name__ == "__main__":
 115     unittest.main()