1 """Power ISA Decoder second stage
3 based on Anton Blanchard microwatt decode2.vhdl
5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
6 over-riding the internal opcode when an exception is needed.
9 from nmigen
import Module
, Elaboratable
, Signal
, Mux
, Const
, Cat
, Repl
, Record
10 from nmigen
.cli
import rtlil
11 from nmutil
.util
import sel
13 from nmutil
.picker
import PriorityPicker
14 from nmutil
.iocontrol
import RecordObject
15 from nmutil
.extend
import exts
17 from openpower
.exceptions
import LDSTException
19 from openpower
.decoder
.power_svp64_prefix
import SVP64PrefixDecoder
20 from openpower
.decoder
.power_svp64_extra
import SVP64CRExtra
, SVP64RegExtra
21 from openpower
.decoder
.power_svp64_rm
import (SVP64RMModeDecode
,
22 sv_input_record_layout
,
24 from openpower
.sv
.svp64
import SVP64Rec
26 from openpower
.decoder
.power_regspec_map
import regspec_decode_read
27 from openpower
.decoder
.power_decoder
import (create_pdecode
,
28 create_pdecode_svp64_ldst
,
30 from openpower
.decoder
.power_enums
import (MicrOp
, CryIn
, Function
,
32 LdstLen
, In1Sel
, In2Sel
, In3Sel
,
33 OutSel
, SPRfull
, SPRreduced
,
34 RCOE
, SVP64LDSTmode
, LDSTMode
,
35 SVEXTRA
, SVEType
, SVPType
)
36 from openpower
.decoder
.decode2execute1
import (Decode2ToExecute1Type
, Data
,
39 from openpower
.consts
import (MSR
, SPEC
, EXTRA2
, EXTRA3
, SVP64P
, field
,
40 SPEC_SIZE
, SPECb
, SPEC_AUG_SIZE
, SVP64CROffs
,
41 FastRegsEnum
, XERRegsEnum
, TT
)
43 from openpower
.state
import CoreState
44 from openpower
.util
import (spr_to_fast
, spr_to_state
, log
)
47 def decode_spr_num(spr
):
48 return Cat(spr
[5:10], spr
[0:5])
51 def instr_is_priv(m
, op
, insn
):
52 """determines if the instruction is privileged or not
55 is_priv_insn
= Signal(reset_less
=True)
57 with m
.Case(MicrOp
.OP_ATTN
, MicrOp
.OP_MFMSR
, MicrOp
.OP_MTMSRD
,
58 MicrOp
.OP_MTMSR
, MicrOp
.OP_RFID
):
59 comb
+= is_priv_insn
.eq(1)
60 with m
.Case(MicrOp
.OP_TLBIE
):
61 comb
+= is_priv_insn
.eq(1)
62 with m
.Case(MicrOp
.OP_MFSPR
, MicrOp
.OP_MTSPR
):
63 with m
.If(insn
[20]): # field XFX.spr[-1] i think
64 comb
+= is_priv_insn
.eq(1)
68 class SPRMap(Elaboratable
):
69 """SPRMap: maps POWER9 SPR numbers to internal enum values, fast and slow
72 def __init__(self
, regreduce_en
):
73 self
.regreduce_en
= regreduce_en
79 self
.spr_i
= Signal(10, reset_less
=True)
80 self
.spr_o
= Data(SPR
, name
="spr_o")
81 self
.fast_o
= Data(4, name
="fast_o")
82 self
.state_o
= Data(3, name
="state_o")
84 def elaborate(self
, platform
):
90 with m
.Switch(self
.spr_i
):
91 for i
, x
in enumerate(SPR
):
93 m
.d
.comb
+= self
.spr_o
.data
.eq(i
)
94 m
.d
.comb
+= self
.spr_o
.ok
.eq(1)
95 for x
, v
in spr_to_fast
.items():
97 m
.d
.comb
+= self
.fast_o
.data
.eq(v
)
98 m
.d
.comb
+= self
.fast_o
.ok
.eq(1)
99 for x
, v
in spr_to_state
.items():
100 with m
.Case(x
.value
):
101 m
.d
.comb
+= self
.state_o
.data
.eq(v
)
102 m
.d
.comb
+= self
.state_o
.ok
.eq(1)
106 class DecodeA(Elaboratable
):
107 """DecodeA from instruction
109 decodes register RA, implicit and explicit CSRs
112 def __init__(self
, dec
, op
, regreduce_en
):
113 self
.regreduce_en
= regreduce_en
114 if self
.regreduce_en
:
120 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
121 self
.insn_in
= Signal(32, reset_less
=True)
122 self
.reg_out
= Data(5, name
="reg_a")
123 self
.spr_out
= Data(SPR
, "spr_a")
124 self
.fast_out
= Data(4, "fast_a")
125 self
.state_out
= Data(3, "state_a")
126 self
.sv_nz
= Signal(1)
128 def elaborate(self
, platform
):
133 m
.submodules
.sprmap
= sprmap
= SPRMap(self
.regreduce_en
)
135 # select Register A field, if *full 7 bits* are zero (2 more from SVP64)
136 ra
= Signal(5, reset_less
=True)
137 comb
+= ra
.eq(self
.dec
.RA
)
138 with m
.If((self
.sel_in
== In1Sel
.RA
) |
139 ((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
140 ((ra
!= Const(0, 5)) |
(self
.sv_nz
!= Const(0, 1))))):
141 comb
+= reg
.data
.eq(ra
)
144 # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
145 # moved it to 1st position (in1_sel)... because
146 rs
= Signal(5, reset_less
=True)
147 comb
+= rs
.eq(self
.dec
.RS
)
148 with m
.If(self
.sel_in
== In1Sel
.RS
):
149 comb
+= reg
.data
.eq(rs
)
152 # select Register FRA field,
153 fra
= Signal(5, reset_less
=True)
154 comb
+= fra
.eq(self
.dec
.FRA
)
155 with m
.If(self
.sel_in
== In1Sel
.FRA
):
156 comb
+= reg
.data
.eq(fra
)
159 # select Register FRS field,
160 frs
= Signal(5, reset_less
=True)
161 comb
+= frs
.eq(self
.dec
.FRS
)
162 with m
.If(self
.sel_in
== In1Sel
.FRS
):
163 comb
+= reg
.data
.eq(frs
)
166 # select Register FRT field,
167 frt
= Signal(5, reset_less
=True)
168 comb
+= frt
.eq(self
.dec
.FRT
)
169 with m
.If(self
.sel_in
== In1Sel
.FRT
):
170 comb
+= reg
.data
.eq(frt
)
173 # decode Fast-SPR based on instruction type
174 with m
.Switch(op
.internal_op
):
176 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
177 with m
.Case(MicrOp
.OP_BC
):
178 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
180 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.CTR
)
181 comb
+= self
.fast_out
.ok
.eq(1)
182 with m
.Case(MicrOp
.OP_BCREG
):
183 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
184 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
185 with m
.If(xo9
& ~xo5
):
187 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.CTR
)
188 comb
+= self
.fast_out
.ok
.eq(1)
190 # MFSPR move from SPRs
191 with m
.Case(MicrOp
.OP_MFSPR
):
192 spr
= Signal(10, reset_less
=True)
193 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
194 comb
+= sprmap
.spr_i
.eq(spr
)
195 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
196 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
197 comb
+= self
.state_out
.eq(sprmap
.state_o
)
202 class DecodeAImm(Elaboratable
):
203 """DecodeA immediate from instruction
205 decodes register RA, whether immediate-zero, implicit and
206 explicit CSRs. SVP64 mode requires 2 extra bits
209 def __init__(self
, dec
):
211 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
212 self
.immz_out
= Signal(reset_less
=True)
213 self
.sv_nz
= Signal(1) # EXTRA bits from SVP64
215 def elaborate(self
, platform
):
219 # zero immediate requested
220 ra
= Signal(5, reset_less
=True)
221 comb
+= ra
.eq(self
.dec
.RA
)
222 with m
.If((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
223 (ra
== Const(0, 5)) &
224 (self
.sv_nz
== Const(0, 1))):
225 comb
+= self
.immz_out
.eq(1)
230 class DecodeB(Elaboratable
):
231 """DecodeB from instruction
233 decodes register RB, different forms of immediate (signed, unsigned),
234 and implicit SPRs. register B is basically "lane 2" into the CompUnits.
235 by industry-standard convention, "lane 2" is where fully-decoded
236 immediates are muxed in.
239 def __init__(self
, dec
, op
):
242 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
243 self
.insn_in
= Signal(32, reset_less
=True)
244 self
.reg_out
= Data(7, "reg_b")
245 self
.reg_isvec
= Signal(1, name
="reg_b_isvec") # TODO: in reg_out
246 self
.fast_out
= Data(4, "fast_b")
248 def elaborate(self
, platform
):
254 # select Register B field
255 with m
.Switch(self
.sel_in
):
256 with m
.Case(In2Sel
.FRB
):
257 comb
+= reg
.data
.eq(self
.dec
.FRB
)
259 with m
.Case(In2Sel
.RB
):
260 comb
+= reg
.data
.eq(self
.dec
.RB
)
262 with m
.Case(In2Sel
.RS
):
263 # for M-Form shiftrot
264 comb
+= reg
.data
.eq(self
.dec
.RS
)
267 # decode SPR2 based on instruction type
268 # BCREG implicitly uses LR or TAR for 2nd reg
269 # CTR however is already in fast_spr1 *not* 2.
270 with m
.If(op
.internal_op
== MicrOp
.OP_BCREG
):
271 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
272 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
274 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.LR
)
275 comb
+= self
.fast_out
.ok
.eq(1)
277 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.TAR
)
278 comb
+= self
.fast_out
.ok
.eq(1)
283 class DecodeBImm(Elaboratable
):
284 """DecodeB immediate from instruction
287 def __init__(self
, dec
):
289 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
290 self
.imm_out
= Data(64, "imm_b")
292 def elaborate(self
, platform
):
296 # select Register B Immediate
297 with m
.Switch(self
.sel_in
):
298 with m
.Case(In2Sel
.CONST_UI
): # unsigned
299 comb
+= self
.imm_out
.data
.eq(self
.dec
.UI
)
300 comb
+= self
.imm_out
.ok
.eq(1)
301 with m
.Case(In2Sel
.CONST_SI
): # sign-extended 16-bit
302 si
= Signal(16, reset_less
=True)
303 comb
+= si
.eq(self
.dec
.SI
)
304 comb
+= self
.imm_out
.data
.eq(exts(si
, 16, 64))
305 comb
+= self
.imm_out
.ok
.eq(1)
306 with m
.Case(In2Sel
.CONST_SI_HI
): # sign-extended 16+16=32 bit
307 si_hi
= Signal(32, reset_less
=True)
308 comb
+= si_hi
.eq(self
.dec
.SI
<< 16)
309 comb
+= self
.imm_out
.data
.eq(exts(si_hi
, 32, 64))
310 comb
+= self
.imm_out
.ok
.eq(1)
311 with m
.Case(In2Sel
.CONST_UI_HI
): # unsigned
312 ui
= Signal(16, reset_less
=True)
313 comb
+= ui
.eq(self
.dec
.UI
)
314 comb
+= self
.imm_out
.data
.eq(ui
<< 16)
315 comb
+= self
.imm_out
.ok
.eq(1)
316 with m
.Case(In2Sel
.CONST_LI
): # sign-extend 24+2=26 bit
317 li
= Signal(26, reset_less
=True)
318 comb
+= li
.eq(self
.dec
.LI
<< 2)
319 comb
+= self
.imm_out
.data
.eq(exts(li
, 26, 64))
320 comb
+= self
.imm_out
.ok
.eq(1)
321 with m
.Case(In2Sel
.CONST_BD
): # sign-extend (14+2)=16 bit
322 bd
= Signal(16, reset_less
=True)
323 comb
+= bd
.eq(self
.dec
.BD
<< 2)
324 comb
+= self
.imm_out
.data
.eq(exts(bd
, 16, 64))
325 comb
+= self
.imm_out
.ok
.eq(1)
326 with m
.Case(In2Sel
.CONST_DS
): # sign-extended (14+2=16) bit
327 ds
= Signal(16, reset_less
=True)
328 comb
+= ds
.eq(self
.dec
.DS
<< 2)
329 comb
+= self
.imm_out
.data
.eq(exts(ds
, 16, 64))
330 comb
+= self
.imm_out
.ok
.eq(1)
331 with m
.Case(In2Sel
.CONST_M1
): # signed (-1)
332 comb
+= self
.imm_out
.data
.eq(~
Const(0, 64)) # all 1s
333 comb
+= self
.imm_out
.ok
.eq(1)
334 with m
.Case(In2Sel
.CONST_SH
): # unsigned - for shift
335 comb
+= self
.imm_out
.data
.eq(self
.dec
.sh
)
336 comb
+= self
.imm_out
.ok
.eq(1)
337 with m
.Case(In2Sel
.CONST_SH32
): # unsigned - for shift
338 comb
+= self
.imm_out
.data
.eq(self
.dec
.SH32
)
339 comb
+= self
.imm_out
.ok
.eq(1)
340 with m
.Case(In2Sel
.CONST_XBI
): # unsigned - for grevi
341 comb
+= self
.imm_out
.data
.eq(self
.dec
.FormXB
.XBI
)
342 comb
+= self
.imm_out
.ok
.eq(1)
347 class DecodeC(Elaboratable
):
348 """DecodeC from instruction
350 decodes register RC. this is "lane 3" into some CompUnits (not many)
353 def __init__(self
, dec
, op
):
356 self
.sel_in
= Signal(In3Sel
, reset_less
=True)
357 self
.insn_in
= Signal(32, reset_less
=True)
358 self
.reg_out
= Data(5, "reg_c")
360 def elaborate(self
, platform
):
366 # select Register C field
367 with m
.Switch(self
.sel_in
):
368 with m
.Case(In3Sel
.RB
):
369 # for M-Form shiftrot
370 comb
+= reg
.data
.eq(self
.dec
.RB
)
372 with m
.Case(In3Sel
.FRS
):
373 comb
+= reg
.data
.eq(self
.dec
.FRS
)
375 with m
.Case(In3Sel
.FRA
):
376 comb
+= reg
.data
.eq(self
.dec
.FRA
)
378 with m
.Case(In3Sel
.FRC
):
379 comb
+= reg
.data
.eq(self
.dec
.FRC
)
381 with m
.Case(In3Sel
.RS
):
382 comb
+= reg
.data
.eq(self
.dec
.RS
)
384 with m
.Case(In3Sel
.RC
):
385 comb
+= reg
.data
.eq(self
.dec
.RC
)
387 with m
.Case(In3Sel
.RT
):
388 # for TLI-form ternlogi
389 comb
+= reg
.data
.eq(self
.dec
.RT
)
395 class DecodeOut(Elaboratable
):
396 """DecodeOut from instruction
398 decodes output register RA, RT, FRS, FRT, or SPR
401 def __init__(self
, dec
, op
, regreduce_en
):
402 self
.regreduce_en
= regreduce_en
403 if self
.regreduce_en
:
409 self
.sel_in
= Signal(OutSel
, reset_less
=True)
410 self
.insn_in
= Signal(32, reset_less
=True)
411 self
.reg_out
= Data(5, "reg_o")
412 self
.spr_out
= Data(SPR
, "spr_o")
413 self
.fast_out
= Data(4, "fast_o")
414 self
.state_out
= Data(3, "state_o")
416 def elaborate(self
, platform
):
419 m
.submodules
.sprmap
= sprmap
= SPRMap(self
.regreduce_en
)
423 # select Register out field
424 with m
.Switch(self
.sel_in
):
425 with m
.Case(OutSel
.FRS
):
426 comb
+= reg
.data
.eq(self
.dec
.FRS
)
428 with m
.Case(OutSel
.FRA
):
429 comb
+= reg
.data
.eq(self
.dec
.FRA
)
431 with m
.Case(OutSel
.FRT
):
432 comb
+= reg
.data
.eq(self
.dec
.FRT
)
434 with m
.Case(OutSel
.RT
):
435 comb
+= reg
.data
.eq(self
.dec
.RT
)
437 with m
.Case(OutSel
.RA
):
438 comb
+= reg
.data
.eq(self
.dec
.RA
)
440 with m
.Case(OutSel
.SPR
):
441 spr
= Signal(10, reset_less
=True)
442 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
443 # MFSPR move to SPRs - needs mapping
444 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
445 comb
+= sprmap
.spr_i
.eq(spr
)
446 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
447 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
448 comb
+= self
.state_out
.eq(sprmap
.state_o
)
451 with m
.Switch(op
.internal_op
):
453 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
454 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_BCREG
):
455 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
457 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.CTR
)
458 comb
+= self
.fast_out
.ok
.eq(1)
460 # RFID 1st spr (fast)
461 with m
.Case(MicrOp
.OP_RFID
):
462 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.SRR0
) # SRR0
463 comb
+= self
.fast_out
.ok
.eq(1)
468 class DecodeOut2(Elaboratable
):
469 """DecodeOut2 from instruction
471 decodes output registers (2nd one). note that RA is *implicit* below,
472 which now causes problems with SVP64
474 TODO: SVP64 is a little more complex, here. svp64 allows extending
475 by one more destination by having one more EXTRA field. RA-as-src
476 is not the same as RA-as-dest. limited in that it's the same first
477 5 bits (from the v3.0B opcode), but still kinda cool. mostly used
478 for operations that have src-as-dest: mostly this is LD/ST-with-update
479 but there are others.
482 def __init__(self
, dec
, op
):
485 self
.sel_in
= Signal(OutSel
, reset_less
=True)
486 self
.implicit_rs
= Signal(reset_less
=True) # SVP64 implicit RS/FRS
487 self
.implicit_from_rc
= Signal(reset_less
=True)# implicit RS from RC
488 self
.lk
= Signal(reset_less
=True)
489 self
.insn_in
= Signal(32, reset_less
=True)
490 self
.reg_out
= Data(5, "reg_o2")
491 self
.rs_en
= Signal(reset_less
=True) # FFT instruction detected
492 self
.fast_out
= Data(4, "fast_o2")
493 self
.fast_out3
= Data(4, "fast_o3")
495 def elaborate(self
, platform
):
499 #m.submodules.svdec = svdec = SVP64RegExtra()
501 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
502 #reg = Signal(5, reset_less=True)
504 if hasattr(op
, "upd"):
505 # update mode LD/ST uses read-reg A also as an output
506 with m
.If(op
.upd
== LDSTMode
.update
):
507 comb
+= self
.reg_out
.data
.eq(self
.dec
.RA
)
508 comb
+= self
.reg_out
.ok
.eq(1)
510 # B, BC or BCREG: potential implicit register (LR) output
511 # these give bl, bcl, bclrl, etc.
512 with m
.Switch(op
.internal_op
):
514 # BC* implicit register (LR)
515 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_B
, MicrOp
.OP_BCREG
):
516 with m
.If(self
.lk
): # "link" mode
517 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.LR
) # LR
518 comb
+= self
.fast_out
.ok
.eq(1)
520 # RFID 2nd and 3rd spr (fast)
521 with m
.Case(MicrOp
.OP_RFID
):
522 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.SRR1
) # SRR1
523 comb
+= self
.fast_out
.ok
.eq(1)
524 comb
+= self
.fast_out3
.data
.eq(FastRegsEnum
.SVSRR0
) # SVSRR0
525 comb
+= self
.fast_out3
.ok
.eq(1)
527 # SVP64 FFT mode, FP mul-add: 2nd output reg (FRS) same as FRT
528 # will be offset by VL in hardware
529 # with m.Case(MicrOp.OP_FP_MADD):
530 with m
.If(self
.implicit_rs
):
531 with m
.If(self
.implicit_from_rc
):
532 comb
+= self
.reg_out
.data
.eq(self
.dec
.FRC
) # same as RC
534 comb
+= self
.reg_out
.data
.eq(self
.dec
.FRT
) # same as RT
535 comb
+= self
.reg_out
.ok
.eq(1)
536 comb
+= self
.rs_en
.eq(1)
541 class DecodeRC(Elaboratable
):
542 """DecodeRc from instruction
544 decodes Record bit Rc
547 def __init__(self
, dec
):
549 self
.sel_in
= Signal(RCOE
, reset_less
=True)
550 self
.insn_in
= Signal(32, reset_less
=True)
551 self
.rc_out
= Data(1, "rc")
553 def elaborate(self
, platform
):
557 # select Record bit out field
558 with m
.Switch(self
.sel_in
):
559 with m
.Case(RCOE
.RC
, RCOE
.RC_ONLY
):
560 comb
+= self
.rc_out
.data
.eq(self
.dec
.Rc
)
561 comb
+= self
.rc_out
.ok
.eq(1)
562 with m
.Case(RCOE
.ONE
):
563 comb
+= self
.rc_out
.data
.eq(1)
564 comb
+= self
.rc_out
.ok
.eq(1)
565 with m
.Case(RCOE
.NONE
):
566 comb
+= self
.rc_out
.data
.eq(0)
567 comb
+= self
.rc_out
.ok
.eq(1)
572 class DecodeOE(Elaboratable
):
573 """DecodeOE from instruction
575 decodes OE field: uses RC decode detection which has now been
576 updated to separate out RC_ONLY. all cases RC_ONLY are *NOT*
577 listening to the OE field, here.
580 def __init__(self
, dec
, op
):
583 self
.sel_in
= Signal(RCOE
, reset_less
=True)
584 self
.insn_in
= Signal(32, reset_less
=True)
585 self
.oe_out
= Data(1, "oe")
587 def elaborate(self
, platform
):
591 with m
.Switch(self
.sel_in
):
592 with m
.Case(RCOE
.RC
):
593 comb
+= self
.oe_out
.data
.eq(self
.dec
.OE
)
594 comb
+= self
.oe_out
.ok
.eq(1)
597 comb
+= self
.oe_out
.data
.eq(0)
598 comb
+= self
.oe_out
.ok
.eq(0)
603 class DecodeCRIn(Elaboratable
):
604 """Decodes input CR from instruction
606 CR indices - insn fields - (not the data *in* the CR) require only 3
607 bits because they refer to CR0-CR7
610 def __init__(self
, dec
, op
):
613 self
.sel_in
= Signal(CRInSel
, reset_less
=True)
614 self
.insn_in
= Signal(32, reset_less
=True)
615 self
.cr_bitfield
= Data(3, "cr_bitfield")
616 self
.cr_bitfield_b
= Data(3, "cr_bitfield_b")
617 self
.cr_bitfield_o
= Data(3, "cr_bitfield_o")
618 self
.whole_reg
= Data(8, "cr_fxm")
619 self
.sv_override
= Signal(2, reset_less
=True) # do not do EXTRA spec
621 def elaborate(self
, platform
):
625 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
628 # zero-initialisation
629 comb
+= self
.cr_bitfield
.ok
.eq(0)
630 comb
+= self
.cr_bitfield_b
.ok
.eq(0)
631 comb
+= self
.cr_bitfield_o
.ok
.eq(0)
632 comb
+= self
.whole_reg
.ok
.eq(0)
633 comb
+= self
.sv_override
.eq(0)
635 # select the relevant CR bitfields
636 with m
.Switch(self
.sel_in
):
637 with m
.Case(CRInSel
.NONE
):
638 pass # No bitfield activated
639 with m
.Case(CRInSel
.CR0
):
640 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
641 comb
+= self
.cr_bitfield
.ok
.eq(1)
642 comb
+= self
.sv_override
.eq(1)
643 with m
.Case(CRInSel
.CR1
):
644 comb
+= self
.cr_bitfield
.data
.eq(1) # CR1 (MSB0 numbering)
645 comb
+= self
.cr_bitfield
.ok
.eq(1)
646 comb
+= self
.sv_override
.eq(2)
647 with m
.Case(CRInSel
.BI
):
648 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BI
[2:5])
649 comb
+= self
.cr_bitfield
.ok
.eq(1)
650 with m
.Case(CRInSel
.BFA
):
651 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BFA
)
652 comb
+= self
.cr_bitfield
.ok
.eq(1)
653 with m
.Case(CRInSel
.BA_BB
):
654 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BA
[2:5])
655 comb
+= self
.cr_bitfield
.ok
.eq(1)
656 comb
+= self
.cr_bitfield_b
.data
.eq(self
.dec
.BB
[2:5])
657 comb
+= self
.cr_bitfield_b
.ok
.eq(1)
658 comb
+= self
.cr_bitfield_o
.data
.eq(self
.dec
.BT
[2:5])
659 comb
+= self
.cr_bitfield_o
.ok
.eq(1)
660 with m
.Case(CRInSel
.BC
):
661 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BC
[2:5])
662 comb
+= self
.cr_bitfield
.ok
.eq(1)
663 with m
.Case(CRInSel
.WHOLE_REG
):
664 comb
+= self
.whole_reg
.ok
.eq(1)
665 move_one
= Signal(reset_less
=True)
666 comb
+= move_one
.eq(self
.insn_in
[20]) # MSB0 bit 11
667 with m
.If((op
.internal_op
== MicrOp
.OP_MFCR
) & move_one
):
668 # must one-hot the FXM field
669 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
670 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
672 # otherwise use all of it
673 comb
+= self
.whole_reg
.data
.eq(0xff)
678 class DecodeCROut(Elaboratable
):
679 """Decodes input CR from instruction
681 CR indices - insn fields - (not the data *in* the CR) require only 3
682 bits because they refer to CR0-CR7
685 def __init__(self
, dec
, op
):
688 self
.rc_in
= Signal(reset_less
=True)
689 self
.sel_in
= Signal(CROutSel
, reset_less
=True)
690 self
.insn_in
= Signal(32, reset_less
=True)
691 self
.cr_bitfield
= Data(3, "cr_bitfield")
692 self
.whole_reg
= Data(8, "cr_fxm")
693 self
.sv_override
= Signal(2, reset_less
=True) # do not do EXTRA spec
694 self
.cr_5bit
= Signal(reset_less
=True) # set True for 5-bit
695 self
.cr_2bit
= Signal(2, reset_less
=True) # get lowest 2 bits
697 def elaborate(self
, platform
):
701 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
704 comb
+= self
.cr_bitfield
.ok
.eq(0)
705 comb
+= self
.whole_reg
.ok
.eq(0)
706 comb
+= self
.sv_override
.eq(0)
707 comb
+= self
.cr_5bit
.eq(0)
709 # please note these MUST match (setting of cr_bitfield.ok) exactly
710 # with write_cr0 below in PowerDecoder2. the reason it's separated
711 # is to avoid having duplicate copies of DecodeCROut in multiple
712 # PowerDecoderSubsets. register decoding should be a one-off in
713 # PowerDecoder2. see https://bugs.libre-soc.org/show_bug.cgi?id=606
715 with m
.Switch(self
.sel_in
):
716 with m
.Case(CROutSel
.NONE
):
717 pass # No bitfield activated
718 with m
.Case(CROutSel
.CR0
):
719 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
720 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
721 comb
+= self
.sv_override
.eq(1)
722 with m
.Case(CROutSel
.CR1
):
723 comb
+= self
.cr_bitfield
.data
.eq(1) # CR1 (MSB0 numbering)
724 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
725 comb
+= self
.sv_override
.eq(2)
726 with m
.Case(CROutSel
.BF
):
727 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BF
)
728 comb
+= self
.cr_bitfield
.ok
.eq(1)
729 with m
.Case(CROutSel
.BT
):
730 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormXL
.BT
[2:5])
731 comb
+= self
.cr_bitfield
.ok
.eq(1)
732 comb
+= self
.cr_5bit
.eq(1)
733 comb
+= self
.cr_2bit
.eq(self
.dec
.FormXL
.BT
[0:2])
734 with m
.Case(CROutSel
.WHOLE_REG
):
735 comb
+= self
.whole_reg
.ok
.eq(1)
736 move_one
= Signal(reset_less
=True)
737 comb
+= move_one
.eq(self
.insn_in
[20])
738 with m
.If((op
.internal_op
== MicrOp
.OP_MTCRF
)):
740 # must one-hot the FXM field
741 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
742 with m
.If(ppick
.en_o
):
743 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
745 comb
+= self
.whole_reg
.data
.eq(0b00000001) # CR7
747 comb
+= self
.whole_reg
.data
.eq(self
.dec
.FXM
)
749 # otherwise use all of it
750 comb
+= self
.whole_reg
.data
.eq(0xff)
755 # dictionary of Input Record field names that, if they exist,
756 # will need a corresponding CSV Decoder file column (actually, PowerOp)
757 # to be decoded (this includes the single bit names)
758 record_names
= {'insn_type': 'internal_op',
759 'fn_unit': 'function_unit',
760 'SV_Ptype': 'SV_Ptype',
761 'SV_mode': 'SV_mode',
765 'imm_data': 'in2_sel',
766 'invert_in': 'inv_a',
767 'invert_out': 'inv_out',
770 'output_carry': 'cry_out',
771 'input_carry': 'cry_in',
772 'is_32bit': 'is_32b',
775 'data_len': 'ldst_len',
777 'byte_reverse': 'br',
778 'sign_extend': 'sgn_ext',
783 class PowerDecodeSubset(Elaboratable
):
784 """PowerDecodeSubset: dynamic subset decoder
786 only fields actually requested are copied over. hence, "subset" (duh).
789 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False, state
=None,
790 svp64_en
=True, regreduce_en
=False, fp_en
=False):
792 self
.svp64_en
= svp64_en
793 self
.regreduce_en
= regreduce_en
796 self
.is_svp64_mode
= Signal() # mark decoding as SVP64 Mode
797 self
.implicit_rs
= Signal() # implicit RS/FRS
798 self
.extend_rb_maxvl
= Signal() # jumps RB by an additional MAXVL
799 self
.extend_rc_maxvl
= Signal() # jumps RS by MAXVL from RC
800 self
.sv_rm
= SVP64Rec(name
="dec_svp64") # SVP64 RM field
801 self
.rm_dec
= SVP64RMModeDecode("svp64_rm_dec")
802 # set these to the predicate mask bits needed for the ALU
803 self
.pred_sm
= Signal() # TODO expand to SIMD mask width
804 self
.pred_dm
= Signal() # TODO expand to SIMD mask width
805 self
.sv_a_nz
= Signal(1)
808 self
.fn_name
= fn_name
810 opkls
= Decode2ToOperand
811 self
.do
= opkls(fn_name
)
813 col_subset
= self
.get_col_subset(self
.do
)
814 row_subset
= self
.rowsubsetfn
819 # "conditions" for Decoders, to enable some weird and wonderful
820 # alternatives. useful for PCR (Program Compatibility Register)
821 # amongst other things
824 # XXX NO 'SVP64FFT': self.use_svp64_fft,
829 # only needed for "main" PowerDecode2
831 self
.e
= Decode2ToExecute1Type(name
=self
.fn_name
, do
=self
.do
,
832 regreduce_en
=regreduce_en
)
834 # create decoder if one not already given
836 dec
= create_pdecode(name
=fn_name
, col_subset
=col_subset
,
837 row_subset
=row_subset
,
838 conditions
=conditions
, include_fp
=fp_en
)
841 # set up a copy of the PowerOp
842 self
.op
= PowerOp
.like(self
.dec
.op
)
844 # state information needed by the Decoder
846 state
= CoreState("dec2")
849 def get_col_subset(self
, do
):
850 subset
= {'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
851 for k
, v
in record_names
.items():
854 log("get_col_subset", self
.fn_name
, do
.fields
, subset
)
857 def rowsubsetfn(self
, opcode
, row
):
858 """select per-Function-Unit subset of opcodes to be processed
860 normally this just looks at the "unit" column. MMU is different
861 in that it processes specific SPR set/get operations that the SPR
864 return (row
['unit'] == self
.fn_name
or
865 # sigh a dreadful hack: MTSPR and MFSPR need to be processed
866 # by the MMU pipeline so we direct those opcodes to MMU **AND**
867 # SPR pipelines, then selectively weed out the SPRs that should
868 # or should not not go to each pipeline, further down.
869 # really this should be done by modifying the CSV syntax
870 # to support multiple tasks (unit column multiple entries)
871 # see https://bugs.libre-soc.org/show_bug.cgi?id=310
872 (self
.fn_name
== 'MMU' and row
['unit'] == 'SPR' and
873 row
['internal op'] in ['OP_MTSPR', 'OP_MFSPR']) or
874 # urrr... and the KAIVB SPR, which must also be redirected
875 # (to the TRAP pipeline)
876 # see https://bugs.libre-soc.org/show_bug.cgi?id=859
877 (self
.fn_name
== 'TRAP' and row
['unit'] == 'SPR' and
878 row
['internal op'] in ['OP_MTSPR', 'OP_MFSPR'])
882 ports
= self
.dec
.ports() + self
.e
.ports()
884 ports
+= self
.sv_rm
.ports()
885 ports
.append(self
.is_svp64_mode
)
886 ports
.append(self
.implicit_rs
)
889 def needs_field(self
, field
, op_field
):
894 return hasattr(do
, field
) and self
.op_get(op_field
) is not None
896 def do_get(self
, field
, final
=False):
897 if final
or self
.final
:
901 return getattr(do
, field
, None)
903 def do_copy(self
, field
, val
, final
=False):
904 df
= self
.do_get(field
, final
)
905 if df
is not None and val
is not None:
909 def op_get(self
, op_field
):
910 return getattr(self
.op
, op_field
, None)
912 def elaborate(self
, platform
):
913 if self
.regreduce_en
:
920 op
, do
= self
.dec
.op
, self
.do
921 msr
, cia
, svstate
= state
.msr
, state
.pc
, state
.svstate
922 # fill in for a normal instruction (not an exception)
923 # copy over if non-exception, non-privileged etc. is detected
925 if self
.fn_name
is None:
928 name
= self
.fn_name
+ "tmp"
929 self
.e_tmp
= Decode2ToExecute1Type(name
=name
, opkls
=self
.opkls
,
930 regreduce_en
=self
.regreduce_en
)
932 # set up submodule decoders
933 m
.submodules
.dec
= dec
= self
.dec
934 m
.submodules
.dec_rc
= self
.dec_rc
= dec_rc
= DecodeRC(self
.dec
)
935 m
.submodules
.dec_oe
= dec_oe
= DecodeOE(self
.dec
, op
)
938 # and SVP64 RM mode decoder
939 m
.submodules
.sv_rm_dec
= rm_dec
= self
.rm_dec
941 # copy op from decoder
942 comb
+= self
.op
.eq(self
.dec
.op
)
944 # copy instruction through...
945 for i
in [do
.insn
, dec_rc
.insn_in
, dec_oe
.insn_in
, ]:
946 comb
+= i
.eq(self
.dec
.opcode_in
)
948 # ...and subdecoders' input fields
949 comb
+= dec_rc
.sel_in
.eq(self
.op_get("rc_sel"))
950 comb
+= dec_oe
.sel_in
.eq(self
.op_get("rc_sel")) # XXX should be OE sel
953 comb
+= self
.do_copy("msr", msr
)
954 comb
+= self
.do_copy("cia", cia
)
955 comb
+= self
.do_copy("svstate", svstate
)
957 # set up instruction type
958 # no op: defaults to OP_ILLEGAL
959 internal_op
= self
.op_get("internal_op")
960 comb
+= self
.do_copy("insn_type", internal_op
)
962 # function unit for decoded instruction: requires minor redirect
964 fn
= self
.op_get("function_unit")
965 spr
= Signal(10, reset_less
=True)
966 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
968 # Microwatt doesn't implement the partition table
969 # instead has PRTBL register (SPR) to point to process table
970 # Kestrel has a KAIVB SPR to "rebase" exceptions. rebasing is normally
971 # done with Hypervisor Mode which is not implemented (yet)
973 is_mmu_spr
= Signal()
974 is_trap_spr
= Signal()
975 comb
+= is_spr_mv
.eq((internal_op
== MicrOp
.OP_MTSPR
) |
976 (internal_op
== MicrOp
.OP_MFSPR
))
977 comb
+= is_mmu_spr
.eq((spr
== SPR
.DSISR
.value
) |
978 (spr
== SPR
.DAR
.value
) |
979 (spr
== SPR
.PRTBL
.value
) |
980 (spr
== SPR
.PIDR
.value
))
981 comb
+= is_trap_spr
.eq((spr
== SPR
.KAIVB
.value
)
983 # MMU must receive MMU SPRs
984 with m
.If(is_spr_mv
& (fn
== Function
.SPR
) & is_mmu_spr
):
985 comb
+= self
.do_copy("fn_unit", Function
.MMU
)
986 comb
+= self
.do_copy("insn_type", internal_op
)
987 # TRAP must receive TRAP SPR KAIVB
988 with m
.If(is_spr_mv
& (fn
== Function
.SPR
) & is_trap_spr
):
989 comb
+= self
.do_copy("fn_unit", Function
.TRAP
)
990 comb
+= self
.do_copy("insn_type", internal_op
)
991 # SPR pipe must *not* receive MMU or TRAP SPRs
992 with m
.Elif(is_spr_mv
& ((fn
== Function
.MMU
) & ~is_mmu_spr
) &
993 ((fn
== Function
.TRAP
) & ~is_trap_spr
)):
994 comb
+= self
.do_copy("fn_unit", Function
.NONE
)
995 comb
+= self
.do_copy("insn_type", MicrOp
.OP_ILLEGAL
)
998 comb
+= self
.do_copy("fn_unit", fn
)
1001 if self
.needs_field("zero_a", "in1_sel"):
1002 m
.submodules
.dec_ai
= dec_ai
= DecodeAImm(self
.dec
)
1003 comb
+= dec_ai
.sv_nz
.eq(self
.sv_a_nz
)
1004 comb
+= dec_ai
.sel_in
.eq(self
.op_get("in1_sel"))
1005 comb
+= self
.do_copy("zero_a", dec_ai
.immz_out
) # RA==0 detected
1006 if self
.needs_field("imm_data", "in2_sel"):
1007 m
.submodules
.dec_bi
= dec_bi
= DecodeBImm(self
.dec
)
1008 comb
+= dec_bi
.sel_in
.eq(self
.op_get("in2_sel"))
1009 comb
+= self
.do_copy("imm_data", dec_bi
.imm_out
) # imm in RB
1011 # CR in/out - note: these MUST match with what happens in
1013 rc_out
= self
.dec_rc
.rc_out
.data
1014 with m
.Switch(self
.op_get("cr_out")):
1015 with m
.Case(CROutSel
.CR0
, CROutSel
.CR1
):
1016 comb
+= self
.do_copy("write_cr0", rc_out
) # only when RC=1
1017 with m
.Case(CROutSel
.BF
, CROutSel
.BT
):
1018 comb
+= self
.do_copy("write_cr0", 1)
1020 comb
+= self
.do_copy("input_cr", self
.op_get("cr_in")) # CR in
1021 comb
+= self
.do_copy("output_cr", self
.op_get("cr_out")) # CR out
1024 # connect up SVP64 RM Mode decoding. however... we need a shorter
1025 # path, for the LDST bit-reverse detection. so perform partial
1026 # decode when SVP64 is detected. then, bit-reverse mode can be
1027 # quickly determined, and the Decoder result MUXed over to
1028 # the alternative decoder, svdecldst. what a mess... *sigh*
1029 sv_ptype
= self
.op_get("SV_Ptype")
1030 sv_mode
= self
.op_get("SV_mode")
1031 fn
= self
.op_get("function_unit")
1032 print ("sv_mode n", sv_mode
)
1033 comb
+= rm_dec
.sv_mode
.eq(sv_mode
) # BRANCH/CROP/LDST_IMM etc.
1034 comb
+= rm_dec
.fn_in
.eq(fn
) # decode needs to know Fn type
1035 comb
+= rm_dec
.ptype_in
.eq(sv_ptype
) # Single/Twin predicated
1036 comb
+= rm_dec
.rc_in
.eq(rc_out
) # Rc=1
1037 comb
+= rm_dec
.rm_in
.eq(self
.sv_rm
) # SVP64 RM mode
1038 if self
.needs_field("imm_data", "in2_sel"):
1039 bzero
= dec_bi
.imm_out
.ok
& ~dec_bi
.imm_out
.data
.bool()
1040 comb
+= rm_dec
.ldst_imz_in
.eq(bzero
) # B immediate is zero
1042 # main PowerDecoder2 determines if different SVP64 modes enabled
1043 # detect if SVP64 FFT mode enabled (really bad hack),
1044 # exclude fcfids and others
1045 # XXX this is a REALLY bad hack, REALLY has to be done better.
1046 # likely with a sub-decoder.
1047 # what this ultimately does is enable the 2nd implicit register
1048 # (FRS) for SVP64-decoding. all of these instructions are
1049 # 3-in 2-out but there is not enough room either in the
1050 # opcode *or* EXTRA2/3 to specify a 5th operand.
1052 comb
+= major
.eq(self
.dec
.opcode_in
[26:32])
1054 comb
+= xo
.eq(self
.dec
.opcode_in
[1:11])
1055 comb
+= self
.implicit_rs
.eq(0)
1056 comb
+= self
.extend_rb_maxvl
.eq(0)
1057 comb
+= self
.extend_rc_maxvl
.eq(0)
1058 # implicit RS for major 59
1059 with m
.If((major
== 59) & xo
.matches(
1060 '-----00100', # ffmsubs
1061 '-----00101', # ffmadds
1062 '-----00110', # ffnmsubs
1063 '-----00111', # ffnmadds
1064 '1111100000', # ffadds
1065 '-----11011', # fdmadds
1067 comb
+= self
.implicit_rs
.eq(1)
1068 comb
+= self
.extend_rb_maxvl
.eq(1) # extend RB
1070 comb
+= xo6
.eq(self
.dec
.opcode_in
[0:6])
1071 # implicit RS for major 4
1072 with m
.If((major
== 4) & xo6
.matches(
1075 '111001', # maddedus
1076 '111010', # divmod2du
1080 comb
+= self
.implicit_rs
.eq(1)
1081 comb
+= self
.extend_rc_maxvl
.eq(1) # RS=RT+MAXVL or RS=RC
1082 # implicit RS for major 22, integer maddsubrs
1083 with m
.If((major
== 22) & xo6
.matches(
1084 '-01000', # maddsubrs
1087 comb
+= self
.implicit_rs
.eq(1)
1088 comb
+= self
.extend_rb_maxvl
.eq(1) # extend RB
1091 comb
+= self
.do_copy("rc", dec_rc
.rc_out
)
1093 # OE only enabled when SVP64 not active
1094 with m
.If(~self
.is_svp64_mode
):
1095 comb
+= self
.do_copy("oe", dec_oe
.oe_out
)
1096 # RC1 overrides Rc if rc type is NONE or ONE or Rc=0, in svp64_mode
1097 # for instructions with a forced-Rc=1 (stbcx., pcdec.)
1098 # the RC1 RM bit *becomes* Rc=0/1, but for instructions
1099 # that have Rc=0/1 then when Rc=0 RC1 *becomes* (replaces) Rc.
1100 with m
.Elif((dec_rc
.sel_in
.matches(RCOE
.RC
, RCOE
.RC_ONLY
) &
1101 dec_rc
.rc_out
.data
== 0) |
1102 (dec_rc
.sel_in
== RCOE
.ONE
)):
1103 RC1
= Data(1, "RC1")
1104 comb
+= RC1
.ok
.eq(rm_dec
.RC1
)
1105 comb
+= RC1
.RC1
.eq(rm_dec
.RC1
)
1106 comb
+= self
.do_copy("rc", RC1
)
1108 comb
+= self
.do_copy("oe", dec_oe
.oe_out
)
1110 # decoded/selected instruction flags
1111 comb
+= self
.do_copy("data_len", self
.op_get("ldst_len"))
1112 comb
+= self
.do_copy("invert_in", self
.op_get("inv_a"))
1113 comb
+= self
.do_copy("invert_out", self
.op_get("inv_out"))
1114 comb
+= self
.do_copy("input_carry", self
.op_get("cry_in"))
1115 comb
+= self
.do_copy("output_carry", self
.op_get("cry_out"))
1116 comb
+= self
.do_copy("is_32bit", self
.op_get("is_32b"))
1117 comb
+= self
.do_copy("is_signed", self
.op_get("sgn"))
1118 lk
= self
.op_get("lk")
1121 comb
+= self
.do_copy("lk", self
.dec
.LK
) # XXX TODO: accessor
1123 comb
+= self
.do_copy("byte_reverse", self
.op_get("br"))
1124 comb
+= self
.do_copy("sign_extend", self
.op_get("sgn_ext"))
1125 comb
+= self
.do_copy("ldst_mode", self
.op_get("upd")) # LD/ST mode
1126 comb
+= self
.do_copy("reserve", self
.op_get("rsrv")) # atomic
1128 # copy over SVP64 input record fields (if they exist)
1130 # TODO, really do we have to do these explicitly?? sigh
1131 # for (field, _) in sv_input_record_layout:
1132 # comb += self.do_copy(field, self.rm_dec.op_get(field))
1133 comb
+= self
.do_copy("sv_saturate", self
.rm_dec
.saturate
)
1134 comb
+= self
.do_copy("sv_Ptype", self
.rm_dec
.ptype_in
)
1135 comb
+= self
.do_copy("sv_ldstmode", self
.rm_dec
.ldstmode
)
1136 # these get set up based on incoming mask bits. TODO:
1137 # pass in multiple bits (later, when SIMD backends are enabled)
1138 with m
.If(self
.rm_dec
.pred_sz
):
1139 comb
+= self
.do_copy("sv_pred_sz", ~self
.pred_sm
)
1140 with m
.If(self
.rm_dec
.pred_dz
):
1141 comb
+= self
.do_copy("sv_pred_dz", ~self
.pred_dm
)
1146 class PowerDecode2(PowerDecodeSubset
):
1147 """PowerDecode2: the main instruction decoder.
1149 whilst PowerDecode is responsible for decoding the actual opcode, this
1150 module encapsulates further specialist, sparse information and
1151 expansion of fields that is inconvenient to have in the CSV files.
1152 for example: the encoding of the immediates, which are detected
1153 and expanded out to their full value from an annotated (enum)
1156 implicit register usage is also set up, here. for example: OP_BC
1157 requires implicitly reading CTR, OP_RFID requires implicitly writing
1160 in addition, PowerDecoder2 is responsible for detecting whether
1161 instructions are illegal (or privileged) or not, and instead of
1162 just leaving at that, *replacing* the instruction to execute with
1163 a suitable alternative (trap).
1165 LDSTExceptions are done the cycle _after_ they're detected (after
1166 they come out of LDSTCompUnit). basically despite the instruction
1167 being decoded, the results of the decode are completely ignored
1168 and "exception.happened" used to set the "actual" instruction to
1169 "OP_TRAP". the LDSTException data structure gets filled in,
1170 in the CompTrapOpSubset and that's what it fills in SRR.
1172 to make this work, TestIssuer must notice "exception.happened"
1173 after the (failed) LD/ST and copies the LDSTException info from
1174 the output, into here (PowerDecoder2). without incrementing PC.
1176 also instr_fault works the same way: the instruction is "rewritten"
1177 so that the "fake" op that gets created is OP_FETCH_FAILED
1180 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False,
1181 state
=None, svp64_en
=True, regreduce_en
=False, fp_en
=False):
1182 super().__init
__(dec
, opkls
, fn_name
, final
, state
, svp64_en
,
1183 regreduce_en
=False, fp_en
=fp_en
)
1184 self
.ldst_exc
= LDSTException("dec2_exc") # rewrites as OP_TRAP
1185 self
.instr_fault
= Signal() # rewrites instruction as OP_FETCH_FAILED
1186 self
.crout_5bit
= Signal() # CR out is 5-bit
1189 self
.cr_out_isvec
= Signal(1, name
="cr_out_isvec")
1190 self
.cr_in_isvec
= Signal(1, name
="cr_in_isvec")
1191 self
.cr_in_b_isvec
= Signal(1, name
="cr_in_b_isvec")
1192 self
.cr_in_o_isvec
= Signal(1, name
="cr_in_o_isvec")
1193 self
.in1_isvec
= Signal(1, name
="reg_a_isvec")
1194 self
.in2_isvec
= Signal(1, name
="reg_b_isvec")
1195 self
.in3_isvec
= Signal(1, name
="reg_c_isvec")
1196 self
.o_isvec
= Signal(7, name
="reg_o_isvec")
1197 self
.o2_isvec
= Signal(7, name
="reg_o2_isvec")
1198 self
.in1_step
= Signal(7, name
="reg_a_step")
1199 self
.in2_step
= Signal(7, name
="reg_b_step")
1200 self
.in3_step
= Signal(7, name
="reg_c_step")
1201 self
.o_step
= Signal(7, name
="reg_o_step")
1202 self
.o2_step
= Signal(7, name
="reg_o2_step")
1203 self
.remap_active
= Signal(5, name
="remap_active") # per reg
1204 self
.no_in_vec
= Signal(1, name
="no_in_vec") # no inputs vector
1205 self
.no_out_vec
= Signal(1, name
="no_out_vec") # no outputs vector
1206 self
.loop_continue
= Signal(1, name
="loop_continue")
1208 self
.no_in_vec
= Const(1, 1)
1209 self
.no_out_vec
= Const(1, 1)
1210 self
.loop_continue
= Const(0, 1)
1212 def get_col_subset(self
, opkls
):
1213 subset
= super().get_col_subset(opkls
)
1214 subset
.add("asmcode")
1215 subset
.add("in1_sel")
1216 subset
.add("in2_sel")
1217 subset
.add("in3_sel")
1218 subset
.add("out_sel")
1220 subset
.add("sv_in1")
1221 subset
.add("sv_in2")
1222 subset
.add("sv_in3")
1223 subset
.add("sv_out")
1224 subset
.add("sv_out2")
1225 subset
.add("sv_cr_in")
1226 subset
.add("sv_cr_out")
1227 subset
.add("SV_Etype")
1228 subset
.add("SV_Ptype")
1229 subset
.add("SV_mode")
1230 # from SVP64RMModeDecode
1231 for (field
, _
) in sv_input_record_layout
:
1234 subset
.add("internal_op")
1238 def elaborate(self
, platform
):
1239 m
= super().elaborate(platform
)
1242 op
, e_out
, do_out
= self
.op
, self
.e
, self
.e
.do
1243 dec_spr
, msr
, cia
, ext_irq
= state
.dec
, state
.msr
, state
.pc
, state
.eint
1244 rc_out
= self
.dec_rc
.rc_out
.data
1248 # fill in for a normal instruction (not an exception)
1249 # copy over if non-exception, non-privileged etc. is detected
1251 # set up submodule decoders
1252 m
.submodules
.dec_a
= dec_a
= DecodeA(self
.dec
, op
, self
.regreduce_en
)
1253 m
.submodules
.dec_b
= dec_b
= DecodeB(self
.dec
, op
)
1254 m
.submodules
.dec_c
= dec_c
= DecodeC(self
.dec
, op
)
1255 m
.submodules
.dec_o
= dec_o
= DecodeOut(self
.dec
, op
, self
.regreduce_en
)
1256 m
.submodules
.dec_o2
= dec_o2
= DecodeOut2(self
.dec
, op
)
1257 m
.submodules
.dec_cr_in
= self
.dec_cr_in
= DecodeCRIn(self
.dec
, op
)
1258 m
.submodules
.dec_cr_out
= self
.dec_cr_out
= DecodeCROut(self
.dec
, op
)
1259 comb
+= dec_a
.sv_nz
.eq(self
.sv_a_nz
)
1260 comb
+= self
.crout_5bit
.eq(self
.dec_cr_out
.cr_5bit
)
1263 # and SVP64 Extra decoders
1264 m
.submodules
.crout_svdec
= crout_svdec
= SVP64CRExtra()
1265 m
.submodules
.crin_svdec
= crin_svdec
= SVP64CRExtra()
1266 m
.submodules
.crin_svdec_b
= crin_svdec_b
= SVP64CRExtra()
1267 m
.submodules
.crin_svdec_o
= crin_svdec_o
= SVP64CRExtra()
1268 m
.submodules
.in1_svdec
= in1_svdec
= SVP64RegExtra()
1269 m
.submodules
.in2_svdec
= in2_svdec
= SVP64RegExtra()
1270 m
.submodules
.in3_svdec
= in3_svdec
= SVP64RegExtra()
1271 m
.submodules
.o_svdec
= o_svdec
= SVP64RegExtra()
1272 m
.submodules
.o2_svdec
= o2_svdec
= SVP64RegExtra()
1274 # debug access to cr svdec (used in get_pdecode_cr_in/out)
1275 self
.crout_svdec
= crout_svdec
1276 self
.crin_svdec
= crin_svdec
1278 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
1279 reg
= Signal(5, reset_less
=True)
1281 # copy instruction through...
1282 for i
in [do
.insn
, dec_a
.insn_in
, dec_b
.insn_in
,
1283 self
.dec_cr_in
.insn_in
, self
.dec_cr_out
.insn_in
,
1284 dec_c
.insn_in
, dec_o
.insn_in
, dec_o2
.insn_in
]:
1285 comb
+= i
.eq(self
.dec
.opcode_in
)
1288 comb
+= self
.dec_cr_in
.sel_in
.eq(self
.op_get("cr_in"))
1289 comb
+= self
.dec_cr_out
.sel_in
.eq(self
.op_get("cr_out"))
1290 comb
+= self
.dec_cr_out
.rc_in
.eq(rc_out
)
1293 comb
+= self
.do_copy("read_cr_whole", self
.dec_cr_in
.whole_reg
)
1294 comb
+= self
.do_copy("write_cr_whole", self
.dec_cr_out
.whole_reg
)
1296 # ...and subdecoders' input fields
1297 comb
+= dec_a
.sel_in
.eq(self
.op_get("in1_sel"))
1298 comb
+= dec_b
.sel_in
.eq(self
.op_get("in2_sel"))
1299 comb
+= dec_c
.sel_in
.eq(self
.op_get("in3_sel"))
1300 comb
+= dec_o
.sel_in
.eq(self
.op_get("out_sel"))
1301 comb
+= dec_o2
.sel_in
.eq(self
.op_get("out_sel"))
1303 comb
+= dec_o2
.implicit_rs
.eq(self
.implicit_rs
)
1304 comb
+= dec_o2
.implicit_from_rc
.eq(self
.extend_rc_maxvl
)
1305 if hasattr(do
, "lk"):
1306 comb
+= dec_o2
.lk
.eq(do
.lk
)
1309 # now do the SVP64 munging. op.SV_Etype and op.sv_in1 comes from
1310 # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
1311 # which in turn were auto-generated by sv_analysis.py
1312 extra
= self
.sv_rm
.extra
# SVP64 extra bits 10:18
1317 comb
+= crout_svdec
.idx
.eq(self
.op_get("sv_cr_out"))
1318 comb
+= self
.cr_out_isvec
.eq(crout_svdec
.isvec
)
1321 # CR in - selection slightly different due to shared CR field sigh
1322 cr_a_idx
= Signal(SVEXTRA
)
1323 cr_b_idx
= Signal(SVEXTRA
)
1325 # these change slightly, when decoding BA/BB. really should have
1326 # their own separate CSV column: sv_cr_in1 and sv_cr_in2, but hey
1327 comb
+= cr_a_idx
.eq(self
.op_get("sv_cr_in"))
1328 comb
+= cr_b_idx
.eq(SVEXTRA
.NONE
)
1329 with m
.If(self
.op_get("sv_cr_in") == SVEXTRA
.Idx_1_2
.value
):
1330 comb
+= cr_a_idx
.eq(SVEXTRA
.Idx1
)
1331 comb
+= cr_b_idx
.eq(SVEXTRA
.Idx2
)
1333 comb
+= self
.cr_in_isvec
.eq(crin_svdec
.isvec
)
1334 comb
+= self
.cr_in_b_isvec
.eq(crin_svdec_b
.isvec
)
1335 comb
+= self
.cr_in_o_isvec
.eq(crin_svdec_o
.isvec
)
1337 # indices are slightly different, BA/BB mess sorted above
1338 comb
+= crin_svdec
.idx
.eq(cr_a_idx
) # SVP64 CR in A
1339 comb
+= crin_svdec_b
.idx
.eq(cr_b_idx
) # SVP64 CR in B
1341 comb
+= crin_svdec_o
.idx
.eq(self
.op_get("sv_cr_out"))
1343 # get SVSTATE srcstep (TODO: elwidth etc.) needed below
1344 vl
= Signal
.like(self
.state
.svstate
.vl
)
1345 maxvl
= Signal
.like(self
.state
.svstate
.maxvl
)
1346 subvl
= Signal
.like(self
.rm_dec
.rm_in
.subvl
)
1347 srcstep
= Signal
.like(self
.state
.svstate
.srcstep
)
1348 dststep
= Signal
.like(self
.state
.svstate
.dststep
)
1349 ssubstep
= Signal
.like(self
.state
.svstate
.ssubstep
)
1350 dsubstep
= Signal
.like(self
.state
.svstate
.ssubstep
)
1351 comb
+= vl
.eq(self
.state
.svstate
.vl
)
1352 comb
+= maxvl
.eq(self
.state
.svstate
.maxvl
)
1353 comb
+= subvl
.eq(self
.rm_dec
.rm_in
.subvl
)
1354 comb
+= srcstep
.eq(self
.state
.svstate
.srcstep
)
1355 comb
+= dststep
.eq(self
.state
.svstate
.dststep
)
1356 comb
+= ssubstep
.eq(self
.state
.svstate
.ssubstep
)
1357 comb
+= dsubstep
.eq(self
.state
.svstate
.dsubstep
)
1359 in1_step
, in2_step
= self
.in1_step
, self
.in2_step
1360 in3_step
= self
.in3_step
1361 o_step
, o2_step
= self
.o_step
, self
.o2_step
1363 # multiply vl by subvl - note that this is only 7 bit!
1364 # when elwidth overrides get involved this will have to go up
1366 comb
+= vmax
.eq(vl
*(subvl
+1))
1368 # registers a, b, c and out and out2 (LD/ST EA)
1369 sv_etype
= self
.op_get("SV_Etype")
1370 for i
, stuff
in enumerate((
1371 ("RA", e
.read_reg1
, dec_a
.reg_out
, in1_svdec
, in1_step
, False),
1372 ("RB", e
.read_reg2
, dec_b
.reg_out
, in2_svdec
, in2_step
, False),
1373 ("RC", e
.read_reg3
, dec_c
.reg_out
, in3_svdec
, in3_step
, False),
1374 ("RT", e
.write_reg
, dec_o
.reg_out
, o_svdec
, o_step
, True),
1375 ("EA", e
.write_ea
, dec_o2
.reg_out
, o2_svdec
, o2_step
, True))):
1376 rname
, to_reg
, fromreg
, svdec
, remapstep
, out
= stuff
1377 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1378 comb
+= svdec
.etype
.eq(sv_etype
) # EXTRA2/3 for this insn
1379 comb
+= svdec
.reg_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1380 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1381 # *screaam* FFT mode needs an extra offset for RB
1382 # similar to FRS/FRT (below). all of this needs cleanup
1383 offs
= Signal(7, name
="offs_"+rname
, reset_less
=True)
1386 # when FFT sv.ffmadd detected, and REMAP not in use,
1387 # automagically add on an extra offset to RB.
1388 # however when REMAP is active, the FFT REMAP
1389 # schedule takes care of this offset.
1390 with m
.If(dec_o2
.reg_out
.ok
& dec_o2
.rs_en
&
1391 self
.extend_rb_maxvl
):
1392 with m
.If(~self
.remap_active
[i
]):
1393 with m
.If(svdec
.isvec
):
1394 comb
+= offs
.eq(maxvl
) # MAXVL for Vectors
1395 # detect if Vectorised: add srcstep/dststep if yes.
1396 # to_reg is 7-bits, outs get dststep added, ins get srcstep
1397 with m
.If(svdec
.isvec
):
1398 selectstep
= dststep
if out
else srcstep
1399 subselect
= dsubstep
if out
else ssubstep
1400 step
= Signal(7, name
="step_%s" % rname
.lower())
1401 with m
.If(self
.remap_active
[i
]):
1402 comb
+= step
.eq((remapstep
*(subvl
+1))+subselect
)
1404 comb
+= step
.eq((selectstep
*(subvl
+1))+subselect
)
1405 # reverse gear goes the opposite way
1406 with m
.If(self
.rm_dec
.reverse_gear
):
1407 comb
+= to_reg
.offs
.eq(offs
+(vmax
-1-step
))
1409 comb
+= to_reg
.offs
.eq(offs
+step
)
1411 comb
+= to_reg
.offs
.eq(offs
)
1412 comb
+= to_reg
.base
.eq(svdec
.reg_out
)
1413 comb
+= to_reg
.data
.eq(to_reg
.base
+ to_reg
.offs
)
1415 # SVP64 in/out fields
1416 comb
+= in1_svdec
.idx
.eq(self
.op_get("sv_in1")) # reg #1 (in1_sel)
1417 comb
+= in2_svdec
.idx
.eq(self
.op_get("sv_in2")) # reg #2 (in2_sel)
1418 comb
+= in3_svdec
.idx
.eq(self
.op_get("sv_in3")) # reg #3 (in3_sel)
1419 comb
+= o_svdec
.idx
.eq(self
.op_get("sv_out")) # output (out_sel)
1421 comb
+= o2_svdec
.idx
.eq(self
.op_get("sv_out2"))
1422 # XXX TODO - work out where this should come from. the problem is
1423 # that LD-with-update is implied (computed from "is instruction in
1424 # "update mode" rather than specified cleanly as its own CSV column
1426 # output reg-is-vectorised (and when no in/out is vectorised)
1427 comb
+= self
.in1_isvec
.eq(in1_svdec
.isvec
)
1428 comb
+= self
.in2_isvec
.eq(in2_svdec
.isvec
)
1429 comb
+= self
.in3_isvec
.eq(in3_svdec
.isvec
)
1430 comb
+= self
.o_isvec
.eq(o_svdec
.isvec
)
1431 comb
+= self
.o2_isvec
.eq(o2_svdec
.isvec
)
1433 # urrr... don't ask... the implicit register FRS in FFT mode
1434 # "tracks" FRT exactly except it's offset by MAXVL. rather than
1435 # mess up the above with if-statements, override it here.
1436 # same trick is applied to FRB, above, but it's a lot cleaner there
1437 with m
.If(dec_o2
.reg_out
.ok
& dec_o2
.rs_en
):
1438 imp_reg_out
= Signal(7)
1439 imp_isvec
= Signal(1)
1440 with m
.If(self
.extend_rc_maxvl
): # maddedu etc. from RC
1441 comb
+= imp_isvec
.eq(in3_svdec
.isvec
)
1442 comb
+= imp_reg_out
.eq(in3_svdec
.reg_out
)
1444 comb
+= imp_isvec
.eq(o_svdec
.isvec
)
1445 comb
+= imp_reg_out
.eq(o_svdec
.reg_out
)
1447 with m
.If(~self
.remap_active
[4]):
1448 with m
.If(imp_isvec
):
1449 comb
+= offs
.eq(maxvl
) # MAXVL for Vectors
1450 with m
.Elif(self
.extend_rc_maxvl
): # maddedu etc. from RC
1451 comb
+= offs
.eq(0) # keep as RC
1453 comb
+= offs
.eq(1) # add 1 if scalar
1454 with m
.If(imp_isvec
):
1455 step
= Signal(7, name
="step_%s" % rname
.lower())
1456 with m
.If(self
.remap_active
[4]):
1457 with m
.If(self
.extend_rc_maxvl
): # maddedu etc. from RC
1458 comb
+= step
.eq(in3_step
)
1460 comb
+= step
.eq(o2_step
)
1462 comb
+= step
.eq(dststep
)
1463 # reverse gear goes the opposite way
1464 with m
.If(self
.rm_dec
.reverse_gear
):
1465 roffs
= offs
+(vl
-1-step
)
1466 comb
+= e
.write_ea
.data
.eq(roffs
)
1468 comb
+= e
.write_ea
.data
.eq(offs
+step
)
1470 comb
+= e
.write_ea
.offs
.eq(offs
)
1471 comb
+= e
.write_ea
.base
.eq(imp_reg_out
)
1472 comb
+= e
.write_ea
.data
.eq(e
.write_ea
.base
+ e
.write_ea
.offs
)
1473 # ... but write to *second* output
1474 comb
+= self
.o2_isvec
.eq(imp_isvec
)
1475 comb
+= o2_svdec
.idx
.eq(self
.op_get("sv_out"))
1477 # TODO add SPRs here. must be True when *all* are scalar
1478 l
= map(lambda svdec
: svdec
.isvec
, [in1_svdec
, in2_svdec
, in3_svdec
,
1479 crin_svdec
, crin_svdec_b
,
1481 comb
+= self
.no_in_vec
.eq(~
Cat(*l
).bool()) # all input scalar
1482 l
= map(lambda svdec
: svdec
.isvec
, [
1483 o2_svdec
, o_svdec
, crout_svdec
])
1484 # in mapreduce mode, scalar out is *allowed*
1485 with m
.If(self
.rm_dec
.mode
== SVP64RMMode
.MAPREDUCE
.value
):
1486 comb
+= self
.no_out_vec
.eq(0)
1489 comb
+= self
.no_out_vec
.eq(~
Cat(*l
).bool())
1490 # now create a general-purpose "test" as to whether looping
1491 # should continue. this doesn't include predication bit-tests
1492 loop
= self
.loop_continue
1493 with m
.Switch(self
.op_get("SV_Ptype")):
1494 with m
.Case(SVPType
.P2
.value
):
1496 # TODO: *and cache-inhibited LD/ST!*
1497 comb
+= loop
.eq(~
(self
.no_in_vec | self
.no_out_vec
))
1498 with m
.Case(SVPType
.P1
.value
):
1499 # single-predication, test relies on dest only
1500 comb
+= loop
.eq(~self
.no_out_vec
)
1502 # not an SV operation, no looping
1505 # condition registers (CR)
1506 for to_reg
, cr
, name
, svdec
, out
in (
1507 (e
.read_cr1
, self
.dec_cr_in
, "cr_bitfield", crin_svdec
, 0),
1508 (e
.read_cr2
, self
.dec_cr_in
, "cr_bitfield_b", crin_svdec_b
, 0),
1509 (e
.read_cr3
, self
.dec_cr_in
, "cr_bitfield_o", crin_svdec_o
, 0),
1510 (e
.write_cr
, self
.dec_cr_out
, "cr_bitfield", crout_svdec
, 1)):
1511 fromreg
= getattr(cr
, name
)
1512 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1513 comb
+= svdec
.etype
.eq(sv_etype
) # EXTRA2/3 for this insn
1514 comb
+= svdec
.cr_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1515 with m
.If(svdec
.isvec
):
1516 # check if this is CR0 or CR1: treated differently
1517 # (does not "listen" to EXTRA2/3 spec for a start)
1518 # also: the CRs start from completely different locations
1519 step
= dststep
if out
else srcstep
1520 with m
.If(cr
.sv_override
== 1): # CR0
1521 offs
= SVP64CROffs
.CR0
1522 comb
+= to_reg
.data
.eq(step
+offs
)
1523 with m
.Elif(cr
.sv_override
== 2): # CR1
1524 offs
= SVP64CROffs
.CR1
1525 comb
+= to_reg
.data
.eq(step
+1)
1527 comb
+= to_reg
.data
.eq(step
+svdec
.cr_out
) # 7-bit out
1529 comb
+= to_reg
.data
.eq(svdec
.cr_out
) # 7-bit output
1530 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1532 # sigh must determine if RA is nonzero (7 bit)
1533 comb
+= self
.sv_a_nz
.eq(e
.read_reg1
.data
!= Const(0, 7))
1535 # connect up to/from read/write GPRs
1536 for to_reg
, fromreg
in ((e
.read_reg1
, dec_a
.reg_out
),
1537 (e
.read_reg2
, dec_b
.reg_out
),
1538 (e
.read_reg3
, dec_c
.reg_out
),
1539 (e
.write_reg
, dec_o
.reg_out
),
1540 (e
.write_ea
, dec_o2
.reg_out
)):
1541 comb
+= to_reg
.data
.eq(fromreg
.data
)
1542 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1544 # connect up to/from read/write CRs
1545 for to_reg
, cr
, name
in (
1546 (e
.read_cr1
, self
.dec_cr_in
, "cr_bitfield", ),
1547 (e
.read_cr2
, self
.dec_cr_in
, "cr_bitfield_b", ),
1548 (e
.read_cr3
, self
.dec_cr_in
, "cr_bitfield_o", ),
1549 (e
.write_cr
, self
.dec_cr_out
, "cr_bitfield", )):
1550 fromreg
= getattr(cr
, name
)
1551 comb
+= to_reg
.data
.eq(fromreg
.data
)
1552 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1555 comb
+= self
.rm_dec
.ldst_ra_vec
.eq(self
.in1_isvec
) # RA is vector
1556 comb
+= self
.rm_dec
.cr_5bit_in
.eq(self
.crout_5bit
) # CR is 5-bit
1557 # take bottom 2 bits of CR out (CR field selector)
1558 with m
.If(self
.crout_5bit
):
1559 comb
+= self
.rm_dec
.cr_2bit_in
.eq(self
.dec_cr_out
.cr_2bit
)
1562 comb
+= e
.read_spr1
.eq(dec_a
.spr_out
)
1563 comb
+= e
.write_spr
.eq(dec_o
.spr_out
)
1565 # Fast regs out including SRR0/1/SVSRR0
1566 comb
+= e
.read_fast1
.eq(dec_a
.fast_out
)
1567 comb
+= e
.read_fast2
.eq(dec_b
.fast_out
)
1568 comb
+= e
.write_fast1
.eq(dec_o
.fast_out
) # SRR0 (OP_RFID)
1569 comb
+= e
.write_fast2
.eq(dec_o2
.fast_out
) # SRR1 (ditto)
1570 comb
+= e
.write_fast3
.eq(dec_o2
.fast_out3
) # SVSRR0 (ditto)
1571 # and State regs (DEC, TB)
1572 comb
+= e
.read_state1
.eq(dec_a
.state_out
) # DEC/TB
1573 comb
+= e
.write_state1
.eq(dec_o
.state_out
) # DEC/TB
1575 # sigh this is exactly the sort of thing for which the
1576 # decoder is designed to not need. MTSPR, MFSPR and others need
1577 # access to the XER bits. however setting e.oe is not appropriate
1578 internal_op
= self
.op_get("internal_op")
1579 with m
.If(internal_op
== MicrOp
.OP_MFSPR
):
1580 comb
+= e
.xer_in
.eq(0b111) # SO, CA, OV
1581 with m
.If(internal_op
== MicrOp
.OP_CMP
):
1582 comb
+= e
.xer_in
.eq(1 << XERRegsEnum
.SO
) # SO
1583 with m
.If(internal_op
== MicrOp
.OP_MTSPR
):
1584 comb
+= e
.xer_out
.eq(1)
1586 # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
1587 with m
.If(op
.internal_op
== MicrOp
.OP_TRAP
):
1588 # *DO NOT* call self.trap here. that would reset absolutely
1589 # everything including destroying read of RA and RB.
1590 comb
+= self
.do_copy("trapaddr", 0x70) # strip first nibble
1592 ####################
1593 # ok so the instruction's been decoded, blah blah, however
1594 # now we need to determine if it's actually going to go ahead...
1595 # *or* if in fact it's a privileged operation, whether there's
1596 # an external interrupt, etc. etc. this is a simple priority
1597 # if-elif-elif sequence. decrement takes highest priority,
1598 # EINT next highest, privileged operation third.
1600 # check if instruction is privileged
1601 is_priv_insn
= instr_is_priv(m
, op
.internal_op
, e
.do
.insn
)
1603 # different IRQ conditions
1604 ext_irq_ok
= Signal()
1605 dec_irq_ok
= Signal()
1608 ldst_exc
= self
.ldst_exc
1610 comb
+= ext_irq_ok
.eq(ext_irq
& msr
[MSR
.EE
]) # v3.0B p944 (MSR.EE)
1611 comb
+= dec_irq_ok
.eq(dec_spr
[63] & msr
[MSR
.EE
]) # 6.5.11 p1076
1612 comb
+= priv_ok
.eq(is_priv_insn
& msr
[MSR
.PR
])
1613 comb
+= illeg_ok
.eq(op
.internal_op
== MicrOp
.OP_ILLEGAL
)
1615 # absolute top priority: check for an instruction failed
1616 with m
.If(self
.instr_fault
):
1617 comb
+= self
.e
.eq(0) # reset eeeeeverything
1618 comb
+= self
.do_copy("insn", self
.dec
.opcode_in
, True)
1619 comb
+= self
.do_copy("insn_type", MicrOp
.OP_FETCH_FAILED
, True)
1620 comb
+= self
.do_copy("fn_unit", Function
.MMU
, True)
1621 comb
+= self
.do_copy("cia", self
.state
.pc
, True) # PC
1622 comb
+= self
.do_copy("msr", self
.state
.msr
, True) # MSR
1623 # special override on internal_op, due to being a "fake" op
1624 comb
+= self
.dec
.op
.internal_op
.eq(MicrOp
.OP_FETCH_FAILED
)
1626 # LD/ST exceptions. TestIssuer copies the exception info at us
1627 # after a failed LD/ST.
1628 with m
.Elif(ldst_exc
.happened
):
1629 with m
.If(ldst_exc
.alignment
):
1630 self
.trap(m
, TT
.MEMEXC
, 0x600)
1631 with m
.Elif(ldst_exc
.instr_fault
):
1632 with m
.If(ldst_exc
.segment_fault
):
1633 self
.trap(m
, TT
.MEMEXC
, 0x480)
1635 # pass exception info to trap to create SRR1
1636 self
.trap(m
, TT
.MEMEXC
, 0x400, ldst_exc
)
1638 with m
.If(ldst_exc
.segment_fault
):
1639 self
.trap(m
, TT
.MEMEXC
, 0x380)
1641 self
.trap(m
, TT
.MEMEXC
, 0x300)
1643 # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
1644 with m
.Elif(dec_irq_ok
):
1645 self
.trap(m
, TT
.DEC
, 0x900) # v3.0B 6.5 p1065
1647 # external interrupt? only if MSR.EE set
1648 with m
.Elif(ext_irq_ok
):
1649 self
.trap(m
, TT
.EINT
, 0x500)
1651 # privileged instruction trap
1652 with m
.Elif(priv_ok
):
1653 self
.trap(m
, TT
.PRIV
, 0x700)
1655 # illegal instruction must redirect to trap. this is done by
1656 # *overwriting* the decoded instruction and starting again.
1657 # (note: the same goes for interrupts and for privileged operations,
1658 # just with different trapaddr and traptype)
1659 with m
.Elif(illeg_ok
):
1660 # illegal instruction trap
1661 self
.trap(m
, TT
.ILLEG
, 0x700)
1663 # no exception, just copy things to the output
1667 ####################
1668 # follow-up after trap/irq to set up SRR0/1
1670 # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
1671 # Note: OP_SC could actually be modified to just be a trap
1672 with m
.If((do_out
.insn_type
== MicrOp
.OP_TRAP
) |
1673 (do_out
.insn_type
== MicrOp
.OP_SC
)):
1674 # TRAP write fast1 = SRR0
1675 comb
+= e_out
.write_fast1
.data
.eq(FastRegsEnum
.SRR0
) # SRR0
1676 comb
+= e_out
.write_fast1
.ok
.eq(1)
1677 # TRAP write fast2 = SRR1
1678 comb
+= e_out
.write_fast2
.data
.eq(FastRegsEnum
.SRR1
) # SRR1
1679 comb
+= e_out
.write_fast2
.ok
.eq(1)
1680 # TRAP write fast2 = SRR1
1681 comb
+= e_out
.write_fast3
.data
.eq(FastRegsEnum
.SVSRR0
) # SVSRR0
1682 comb
+= e_out
.write_fast3
.ok
.eq(1)
1684 # RFID: needs to read SRR0/1
1685 with m
.If(do_out
.insn_type
== MicrOp
.OP_RFID
):
1686 # TRAP read fast1 = SRR0
1687 comb
+= e_out
.read_fast1
.data
.eq(FastRegsEnum
.SRR0
) # SRR0
1688 comb
+= e_out
.read_fast1
.ok
.eq(1)
1689 # TRAP read fast2 = SRR1
1690 comb
+= e_out
.read_fast2
.data
.eq(FastRegsEnum
.SRR1
) # SRR1
1691 comb
+= e_out
.read_fast2
.ok
.eq(1)
1692 # TRAP read fast2 = SVSRR0
1693 comb
+= e_out
.read_fast3
.data
.eq(FastRegsEnum
.SVSRR0
) # SVSRR0
1694 comb
+= e_out
.read_fast3
.ok
.eq(1)
1696 # annoying simulator bug.
1697 # asmcode may end up getting used for perfcounters?
1698 asmcode
= self
.op_get("asmcode")
1699 if hasattr(e_out
, "asmcode") and asmcode
is not None:
1700 comb
+= e_out
.asmcode
.eq(asmcode
)
1704 def trap(self
, m
, traptype
, trapaddr
, ldst_exc
=None):
1705 """trap: this basically "rewrites" the decoded instruction as a trap
1709 comb
+= e
.eq(0) # reset eeeeeverything
1712 comb
+= self
.do_copy("insn", self
.dec
.opcode_in
, True)
1713 comb
+= self
.do_copy("insn_type", MicrOp
.OP_TRAP
, True)
1714 comb
+= self
.do_copy("fn_unit", Function
.TRAP
, True)
1715 comb
+= self
.do_copy("trapaddr", trapaddr
>> 4, True) # bottom 4 bits
1716 comb
+= self
.do_copy("traptype", traptype
, True) # request type
1717 comb
+= self
.do_copy("ldst_exc", ldst_exc
, True) # request type
1718 comb
+= self
.do_copy("msr", self
.state
.msr
,
1719 True) # copy of MSR "state"
1720 comb
+= self
.do_copy("cia", self
.state
.pc
, True) # copy of PC "state"
1721 comb
+= self
.do_copy("svstate", self
.state
.svstate
, True) # SVSTATE
1724 def get_rdflags(m
, e
, cu
):
1725 """returns a sequential list of the read "ok" flags for a given FU.
1726 this list is in order of the CompUnit input specs
1729 for idx
in range(cu
.n_src
):
1730 regfile
, regname
, _
= cu
.get_in_spec(idx
)
1731 decinfo
= regspec_decode_read(m
, e
, regfile
, regname
)
1732 rdl
.append(decinfo
.okflag
)
1737 if __name__
== '__main__':
1738 pdecode
= create_pdecode()
1739 dec2
= PowerDecode2(pdecode
, svp64_en
=True)
1740 vl
= rtlil
.convert(dec2
, ports
=dec2
.ports() + pdecode
.ports())
1741 with
open("dec2.il", "w") as f
: