1 """Power ISA Decoder second stage
3 based on Anton Blanchard microwatt decode2.vhdl
5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
6 over-riding the internal opcode when an exception is needed.
9 from nmigen
import Module
, Elaboratable
, Signal
, Mux
, Const
, Cat
, Repl
, Record
10 from nmigen
.cli
import rtlil
11 from nmutil
.util
import sel
13 from nmutil
.picker
import PriorityPicker
14 from nmutil
.iocontrol
import RecordObject
15 from nmutil
.extend
import exts
17 from openpower
.exceptions
import LDSTException
19 from openpower
.decoder
.power_svp64_prefix
import SVP64PrefixDecoder
20 from openpower
.decoder
.power_svp64_extra
import SVP64CRExtra
, SVP64RegExtra
21 from openpower
.decoder
.power_svp64_rm
import (SVP64RMModeDecode
,
22 sv_input_record_layout
,
24 from openpower
.sv
.svp64
import SVP64Rec
26 from openpower
.decoder
.power_regspec_map
import regspec_decode_read
27 from openpower
.decoder
.power_decoder
import (create_pdecode
,
28 create_pdecode_svp64_ldst
,
30 from openpower
.decoder
.power_enums
import (MicrOp
, CryIn
, Function
,
32 LdstLen
, In1Sel
, In2Sel
, In3Sel
,
33 OutSel
, SPRfull
, SPRreduced
,
34 RCOE
, SVP64LDSTmode
, LDSTMode
,
35 SVEXTRA
, SVEtype
, SVPtype
)
36 from openpower
.decoder
.decode2execute1
import (Decode2ToExecute1Type
, Data
,
39 from openpower
.consts
import (MSR
, SPEC
, EXTRA2
, EXTRA3
, SVP64P
, field
,
40 SPEC_SIZE
, SPECb
, SPEC_AUG_SIZE
, SVP64CROffs
,
41 FastRegsEnum
, XERRegsEnum
, TT
)
43 from openpower
.state
import CoreState
44 from openpower
.util
import (spr_to_fast
, spr_to_state
, log
)
47 def decode_spr_num(spr
):
48 return Cat(spr
[5:10], spr
[0:5])
51 def instr_is_priv(m
, op
, insn
):
52 """determines if the instruction is privileged or not
55 is_priv_insn
= Signal(reset_less
=True)
57 with m
.Case(MicrOp
.OP_ATTN
, MicrOp
.OP_MFMSR
, MicrOp
.OP_MTMSRD
,
58 MicrOp
.OP_MTMSR
, MicrOp
.OP_RFID
):
59 comb
+= is_priv_insn
.eq(1)
60 with m
.Case(MicrOp
.OP_TLBIE
):
61 comb
+= is_priv_insn
.eq(1)
62 with m
.Case(MicrOp
.OP_MFSPR
, MicrOp
.OP_MTSPR
):
63 with m
.If(insn
[20]): # field XFX.spr[-1] i think
64 comb
+= is_priv_insn
.eq(1)
68 class SPRMap(Elaboratable
):
69 """SPRMap: maps POWER9 SPR numbers to internal enum values, fast and slow
72 def __init__(self
, regreduce_en
):
73 self
.regreduce_en
= regreduce_en
79 self
.spr_i
= Signal(10, reset_less
=True)
80 self
.spr_o
= Data(SPR
, name
="spr_o")
81 self
.fast_o
= Data(4, name
="fast_o")
82 self
.state_o
= Data(3, name
="state_o")
84 def elaborate(self
, platform
):
90 with m
.Switch(self
.spr_i
):
91 for i
, x
in enumerate(SPR
):
93 m
.d
.comb
+= self
.spr_o
.data
.eq(i
)
94 m
.d
.comb
+= self
.spr_o
.ok
.eq(1)
95 for x
, v
in spr_to_fast
.items():
97 m
.d
.comb
+= self
.fast_o
.data
.eq(v
)
98 m
.d
.comb
+= self
.fast_o
.ok
.eq(1)
99 for x
, v
in spr_to_state
.items():
100 with m
.Case(x
.value
):
101 m
.d
.comb
+= self
.state_o
.data
.eq(v
)
102 m
.d
.comb
+= self
.state_o
.ok
.eq(1)
106 class DecodeA(Elaboratable
):
107 """DecodeA from instruction
109 decodes register RA, implicit and explicit CSRs
112 def __init__(self
, dec
, op
, regreduce_en
):
113 self
.regreduce_en
= regreduce_en
114 if self
.regreduce_en
:
120 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
121 self
.insn_in
= Signal(32, reset_less
=True)
122 self
.reg_out
= Data(5, name
="reg_a")
123 self
.spr_out
= Data(SPR
, "spr_a")
124 self
.fast_out
= Data(4, "fast_a")
125 self
.state_out
= Data(3, "state_a")
126 self
.sv_nz
= Signal(1)
128 def elaborate(self
, platform
):
133 m
.submodules
.sprmap
= sprmap
= SPRMap(self
.regreduce_en
)
135 # select Register A field, if *full 7 bits* are zero (2 more from SVP64)
136 ra
= Signal(5, reset_less
=True)
137 comb
+= ra
.eq(self
.dec
.RA
)
138 with m
.If((self
.sel_in
== In1Sel
.RA
) |
139 ((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
140 ((ra
!= Const(0, 5)) |
(self
.sv_nz
!= Const(0, 1))))):
141 comb
+= reg
.data
.eq(ra
)
144 # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
145 # moved it to 1st position (in1_sel)... because
146 rs
= Signal(5, reset_less
=True)
147 comb
+= rs
.eq(self
.dec
.RS
)
148 with m
.If(self
.sel_in
== In1Sel
.RS
):
149 comb
+= reg
.data
.eq(rs
)
152 # select Register FRA field,
153 fra
= Signal(5, reset_less
=True)
154 comb
+= fra
.eq(self
.dec
.FRA
)
155 with m
.If(self
.sel_in
== In1Sel
.FRA
):
156 comb
+= reg
.data
.eq(fra
)
159 # select Register FRS field,
160 frs
= Signal(5, reset_less
=True)
161 comb
+= frs
.eq(self
.dec
.FRS
)
162 with m
.If(self
.sel_in
== In1Sel
.FRS
):
163 comb
+= reg
.data
.eq(frs
)
166 # decode Fast-SPR based on instruction type
167 with m
.Switch(op
.internal_op
):
169 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
170 with m
.Case(MicrOp
.OP_BC
):
171 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
173 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.CTR
)
174 comb
+= self
.fast_out
.ok
.eq(1)
175 with m
.Case(MicrOp
.OP_BCREG
):
176 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
177 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
178 with m
.If(xo9
& ~xo5
):
180 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.CTR
)
181 comb
+= self
.fast_out
.ok
.eq(1)
183 # MFSPR move from SPRs
184 with m
.Case(MicrOp
.OP_MFSPR
):
185 spr
= Signal(10, reset_less
=True)
186 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
187 comb
+= sprmap
.spr_i
.eq(spr
)
188 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
189 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
190 comb
+= self
.state_out
.eq(sprmap
.state_o
)
195 class DecodeAImm(Elaboratable
):
196 """DecodeA immediate from instruction
198 decodes register RA, whether immediate-zero, implicit and
199 explicit CSRs. SVP64 mode requires 2 extra bits
202 def __init__(self
, dec
):
204 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
205 self
.immz_out
= Signal(reset_less
=True)
206 self
.sv_nz
= Signal(1) # EXTRA bits from SVP64
208 def elaborate(self
, platform
):
212 # zero immediate requested
213 ra
= Signal(5, reset_less
=True)
214 comb
+= ra
.eq(self
.dec
.RA
)
215 with m
.If((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
216 (ra
== Const(0, 5)) &
217 (self
.sv_nz
== Const(0, 1))):
218 comb
+= self
.immz_out
.eq(1)
223 class DecodeB(Elaboratable
):
224 """DecodeB from instruction
226 decodes register RB, different forms of immediate (signed, unsigned),
227 and implicit SPRs. register B is basically "lane 2" into the CompUnits.
228 by industry-standard convention, "lane 2" is where fully-decoded
229 immediates are muxed in.
232 def __init__(self
, dec
, op
):
235 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
236 self
.insn_in
= Signal(32, reset_less
=True)
237 self
.reg_out
= Data(7, "reg_b")
238 self
.reg_isvec
= Signal(1, name
="reg_b_isvec") # TODO: in reg_out
239 self
.fast_out
= Data(4, "fast_b")
241 def elaborate(self
, platform
):
247 # select Register B field
248 with m
.Switch(self
.sel_in
):
249 with m
.Case(In2Sel
.FRB
):
250 comb
+= reg
.data
.eq(self
.dec
.FRB
)
252 with m
.Case(In2Sel
.RB
):
253 comb
+= reg
.data
.eq(self
.dec
.RB
)
255 with m
.Case(In2Sel
.RS
):
256 # for M-Form shiftrot
257 comb
+= reg
.data
.eq(self
.dec
.RS
)
260 # decode SPR2 based on instruction type
261 # BCREG implicitly uses LR or TAR for 2nd reg
262 # CTR however is already in fast_spr1 *not* 2.
263 with m
.If(op
.internal_op
== MicrOp
.OP_BCREG
):
264 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
265 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
267 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.LR
)
268 comb
+= self
.fast_out
.ok
.eq(1)
270 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.TAR
)
271 comb
+= self
.fast_out
.ok
.eq(1)
276 class DecodeBImm(Elaboratable
):
277 """DecodeB immediate from instruction
280 def __init__(self
, dec
):
282 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
283 self
.imm_out
= Data(64, "imm_b")
285 def elaborate(self
, platform
):
289 # select Register B Immediate
290 with m
.Switch(self
.sel_in
):
291 with m
.Case(In2Sel
.CONST_UI
): # unsigned
292 comb
+= self
.imm_out
.data
.eq(self
.dec
.UI
)
293 comb
+= self
.imm_out
.ok
.eq(1)
294 with m
.Case(In2Sel
.CONST_SI
): # sign-extended 16-bit
295 si
= Signal(16, reset_less
=True)
296 comb
+= si
.eq(self
.dec
.SI
)
297 comb
+= self
.imm_out
.data
.eq(exts(si
, 16, 64))
298 comb
+= self
.imm_out
.ok
.eq(1)
299 with m
.Case(In2Sel
.CONST_SI_HI
): # sign-extended 16+16=32 bit
300 si_hi
= Signal(32, reset_less
=True)
301 comb
+= si_hi
.eq(self
.dec
.SI
<< 16)
302 comb
+= self
.imm_out
.data
.eq(exts(si_hi
, 32, 64))
303 comb
+= self
.imm_out
.ok
.eq(1)
304 with m
.Case(In2Sel
.CONST_UI_HI
): # unsigned
305 ui
= Signal(16, reset_less
=True)
306 comb
+= ui
.eq(self
.dec
.UI
)
307 comb
+= self
.imm_out
.data
.eq(ui
<< 16)
308 comb
+= self
.imm_out
.ok
.eq(1)
309 with m
.Case(In2Sel
.CONST_LI
): # sign-extend 24+2=26 bit
310 li
= Signal(26, reset_less
=True)
311 comb
+= li
.eq(self
.dec
.LI
<< 2)
312 comb
+= self
.imm_out
.data
.eq(exts(li
, 26, 64))
313 comb
+= self
.imm_out
.ok
.eq(1)
314 with m
.Case(In2Sel
.CONST_BD
): # sign-extend (14+2)=16 bit
315 bd
= Signal(16, reset_less
=True)
316 comb
+= bd
.eq(self
.dec
.BD
<< 2)
317 comb
+= self
.imm_out
.data
.eq(exts(bd
, 16, 64))
318 comb
+= self
.imm_out
.ok
.eq(1)
319 with m
.Case(In2Sel
.CONST_DS
): # sign-extended (14+2=16) bit
320 ds
= Signal(16, reset_less
=True)
321 comb
+= ds
.eq(self
.dec
.DS
<< 2)
322 comb
+= self
.imm_out
.data
.eq(exts(ds
, 16, 64))
323 comb
+= self
.imm_out
.ok
.eq(1)
324 with m
.Case(In2Sel
.CONST_M1
): # signed (-1)
325 comb
+= self
.imm_out
.data
.eq(~
Const(0, 64)) # all 1s
326 comb
+= self
.imm_out
.ok
.eq(1)
327 with m
.Case(In2Sel
.CONST_SH
): # unsigned - for shift
328 comb
+= self
.imm_out
.data
.eq(self
.dec
.sh
)
329 comb
+= self
.imm_out
.ok
.eq(1)
330 with m
.Case(In2Sel
.CONST_SH32
): # unsigned - for shift
331 comb
+= self
.imm_out
.data
.eq(self
.dec
.SH32
)
332 comb
+= self
.imm_out
.ok
.eq(1)
333 with m
.Case(In2Sel
.CONST_XBI
): # unsigned - for grevi
334 comb
+= self
.imm_out
.data
.eq(self
.dec
.FormXB
.XBI
)
335 comb
+= self
.imm_out
.ok
.eq(1)
340 class DecodeC(Elaboratable
):
341 """DecodeC from instruction
343 decodes register RC. this is "lane 3" into some CompUnits (not many)
346 def __init__(self
, dec
, op
):
349 self
.sel_in
= Signal(In3Sel
, reset_less
=True)
350 self
.insn_in
= Signal(32, reset_less
=True)
351 self
.reg_out
= Data(5, "reg_c")
353 def elaborate(self
, platform
):
359 # select Register C field
360 with m
.Switch(self
.sel_in
):
361 with m
.Case(In3Sel
.RB
):
362 # for M-Form shiftrot
363 comb
+= reg
.data
.eq(self
.dec
.RB
)
365 with m
.Case(In3Sel
.FRS
):
366 comb
+= reg
.data
.eq(self
.dec
.FRS
)
368 with m
.Case(In3Sel
.FRC
):
369 comb
+= reg
.data
.eq(self
.dec
.FRC
)
371 with m
.Case(In3Sel
.RS
):
372 comb
+= reg
.data
.eq(self
.dec
.RS
)
374 with m
.Case(In3Sel
.RC
):
375 comb
+= reg
.data
.eq(self
.dec
.RC
)
377 with m
.Case(In3Sel
.RT
):
378 # for TLI-form ternlogi
379 comb
+= reg
.data
.eq(self
.dec
.RT
)
385 class DecodeOut(Elaboratable
):
386 """DecodeOut from instruction
388 decodes output register RA, RT, FRS, FRT, or SPR
391 def __init__(self
, dec
, op
, regreduce_en
):
392 self
.regreduce_en
= regreduce_en
393 if self
.regreduce_en
:
399 self
.sel_in
= Signal(OutSel
, reset_less
=True)
400 self
.insn_in
= Signal(32, reset_less
=True)
401 self
.reg_out
= Data(5, "reg_o")
402 self
.spr_out
= Data(SPR
, "spr_o")
403 self
.fast_out
= Data(4, "fast_o")
404 self
.state_out
= Data(3, "state_o")
406 def elaborate(self
, platform
):
409 m
.submodules
.sprmap
= sprmap
= SPRMap(self
.regreduce_en
)
413 # select Register out field
414 with m
.Switch(self
.sel_in
):
415 with m
.Case(OutSel
.FRS
):
416 comb
+= reg
.data
.eq(self
.dec
.FRS
)
418 with m
.Case(OutSel
.FRT
):
419 comb
+= reg
.data
.eq(self
.dec
.FRT
)
421 with m
.Case(OutSel
.RT
):
422 comb
+= reg
.data
.eq(self
.dec
.RT
)
424 with m
.Case(OutSel
.RA
):
425 comb
+= reg
.data
.eq(self
.dec
.RA
)
427 with m
.Case(OutSel
.SPR
):
428 spr
= Signal(10, reset_less
=True)
429 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
430 # MFSPR move to SPRs - needs mapping
431 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
432 comb
+= sprmap
.spr_i
.eq(spr
)
433 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
434 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
435 comb
+= self
.state_out
.eq(sprmap
.state_o
)
438 with m
.Switch(op
.internal_op
):
440 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
441 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_BCREG
):
442 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
444 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.CTR
)
445 comb
+= self
.fast_out
.ok
.eq(1)
447 # RFID 1st spr (fast)
448 with m
.Case(MicrOp
.OP_RFID
):
449 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.SRR0
) # SRR0
450 comb
+= self
.fast_out
.ok
.eq(1)
455 class DecodeOut2(Elaboratable
):
456 """DecodeOut2 from instruction
458 decodes output registers (2nd one). note that RA is *implicit* below,
459 which now causes problems with SVP64
461 TODO: SVP64 is a little more complex, here. svp64 allows extending
462 by one more destination by having one more EXTRA field. RA-as-src
463 is not the same as RA-as-dest. limited in that it's the same first
464 5 bits (from the v3.0B opcode), but still kinda cool. mostly used
465 for operations that have src-as-dest: mostly this is LD/ST-with-update
466 but there are others.
469 def __init__(self
, dec
, op
):
472 self
.sel_in
= Signal(OutSel
, reset_less
=True)
473 self
.implicit_rs
= Signal(reset_less
=True) # SVP64 implicit RS/FRS
474 self
.implicit_from_rc
= Signal(reset_less
=True)# implicit RS from RC
475 self
.lk
= Signal(reset_less
=True)
476 self
.insn_in
= Signal(32, reset_less
=True)
477 self
.reg_out
= Data(5, "reg_o2")
478 self
.rs_en
= Signal(reset_less
=True) # FFT instruction detected
479 self
.fast_out
= Data(4, "fast_o2")
480 self
.fast_out3
= Data(4, "fast_o3")
482 def elaborate(self
, platform
):
486 #m.submodules.svdec = svdec = SVP64RegExtra()
488 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
489 #reg = Signal(5, reset_less=True)
491 if hasattr(op
, "upd"):
492 # update mode LD/ST uses read-reg A also as an output
493 with m
.If(op
.upd
== LDSTMode
.update
):
494 comb
+= self
.reg_out
.data
.eq(self
.dec
.RA
)
495 comb
+= self
.reg_out
.ok
.eq(1)
497 # B, BC or BCREG: potential implicit register (LR) output
498 # these give bl, bcl, bclrl, etc.
499 with m
.Switch(op
.internal_op
):
501 # BC* implicit register (LR)
502 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_B
, MicrOp
.OP_BCREG
):
503 with m
.If(self
.lk
): # "link" mode
504 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.LR
) # LR
505 comb
+= self
.fast_out
.ok
.eq(1)
507 # RFID 2nd and 3rd spr (fast)
508 with m
.Case(MicrOp
.OP_RFID
):
509 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.SRR1
) # SRR1
510 comb
+= self
.fast_out
.ok
.eq(1)
511 comb
+= self
.fast_out3
.data
.eq(FastRegsEnum
.SVSRR0
) # SVSRR0
512 comb
+= self
.fast_out3
.ok
.eq(1)
514 # SVP64 FFT mode, FP mul-add: 2nd output reg (FRS) same as FRT
515 # will be offset by VL in hardware
516 # with m.Case(MicrOp.OP_FP_MADD):
517 with m
.If(self
.implicit_rs
):
518 with m
.If(self
.implicit_from_rc
):
519 comb
+= self
.reg_out
.data
.eq(self
.dec
.FRC
) # same as RC
521 comb
+= self
.reg_out
.data
.eq(self
.dec
.FRT
) # same as RT
522 comb
+= self
.reg_out
.ok
.eq(1)
523 comb
+= self
.rs_en
.eq(1)
528 class DecodeRC(Elaboratable
):
529 """DecodeRc from instruction
531 decodes Record bit Rc
534 def __init__(self
, dec
):
536 self
.sel_in
= Signal(RCOE
, reset_less
=True)
537 self
.insn_in
= Signal(32, reset_less
=True)
538 self
.rc_out
= Data(1, "rc")
540 def elaborate(self
, platform
):
544 # select Record bit out field
545 with m
.Switch(self
.sel_in
):
546 with m
.Case(RCOE
.RC
, RCOE
.RC_ONLY
):
547 comb
+= self
.rc_out
.data
.eq(self
.dec
.Rc
)
548 comb
+= self
.rc_out
.ok
.eq(1)
549 with m
.Case(RCOE
.ONE
):
550 comb
+= self
.rc_out
.data
.eq(1)
551 comb
+= self
.rc_out
.ok
.eq(1)
552 with m
.Case(RCOE
.NONE
):
553 comb
+= self
.rc_out
.data
.eq(0)
554 comb
+= self
.rc_out
.ok
.eq(1)
559 class DecodeOE(Elaboratable
):
560 """DecodeOE from instruction
562 decodes OE field: uses RC decode detection which has now been
563 updated to separate out RC_ONLY. all cases RC_ONLY are *NOT*
564 listening to the OE field, here.
567 def __init__(self
, dec
, op
):
570 self
.sel_in
= Signal(RCOE
, reset_less
=True)
571 self
.insn_in
= Signal(32, reset_less
=True)
572 self
.oe_out
= Data(1, "oe")
574 def elaborate(self
, platform
):
578 with m
.Switch(self
.sel_in
):
579 with m
.Case(RCOE
.RC
):
580 comb
+= self
.oe_out
.data
.eq(self
.dec
.OE
)
581 comb
+= self
.oe_out
.ok
.eq(1)
584 comb
+= self
.oe_out
.data
.eq(0)
585 comb
+= self
.oe_out
.ok
.eq(0)
590 class DecodeCRIn(Elaboratable
):
591 """Decodes input CR from instruction
593 CR indices - insn fields - (not the data *in* the CR) require only 3
594 bits because they refer to CR0-CR7
597 def __init__(self
, dec
, op
):
600 self
.sel_in
= Signal(CRInSel
, reset_less
=True)
601 self
.insn_in
= Signal(32, reset_less
=True)
602 self
.cr_bitfield
= Data(3, "cr_bitfield")
603 self
.cr_bitfield_b
= Data(3, "cr_bitfield_b")
604 self
.cr_bitfield_o
= Data(3, "cr_bitfield_o")
605 self
.whole_reg
= Data(8, "cr_fxm")
606 self
.sv_override
= Signal(2, reset_less
=True) # do not do EXTRA spec
608 def elaborate(self
, platform
):
612 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
615 # zero-initialisation
616 comb
+= self
.cr_bitfield
.ok
.eq(0)
617 comb
+= self
.cr_bitfield_b
.ok
.eq(0)
618 comb
+= self
.cr_bitfield_o
.ok
.eq(0)
619 comb
+= self
.whole_reg
.ok
.eq(0)
620 comb
+= self
.sv_override
.eq(0)
622 # select the relevant CR bitfields
623 with m
.Switch(self
.sel_in
):
624 with m
.Case(CRInSel
.NONE
):
625 pass # No bitfield activated
626 with m
.Case(CRInSel
.CR0
):
627 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
628 comb
+= self
.cr_bitfield
.ok
.eq(1)
629 comb
+= self
.sv_override
.eq(1)
630 with m
.Case(CRInSel
.CR1
):
631 comb
+= self
.cr_bitfield
.data
.eq(1) # CR1 (MSB0 numbering)
632 comb
+= self
.cr_bitfield
.ok
.eq(1)
633 comb
+= self
.sv_override
.eq(2)
634 with m
.Case(CRInSel
.BI
):
635 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BI
[2:5])
636 comb
+= self
.cr_bitfield
.ok
.eq(1)
637 with m
.Case(CRInSel
.BFA
):
638 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BFA
)
639 comb
+= self
.cr_bitfield
.ok
.eq(1)
640 with m
.Case(CRInSel
.BA_BB
):
641 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BA
[2:5])
642 comb
+= self
.cr_bitfield
.ok
.eq(1)
643 comb
+= self
.cr_bitfield_b
.data
.eq(self
.dec
.BB
[2:5])
644 comb
+= self
.cr_bitfield_b
.ok
.eq(1)
645 comb
+= self
.cr_bitfield_o
.data
.eq(self
.dec
.BT
[2:5])
646 comb
+= self
.cr_bitfield_o
.ok
.eq(1)
647 with m
.Case(CRInSel
.BC
):
648 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BC
[2:5])
649 comb
+= self
.cr_bitfield
.ok
.eq(1)
650 with m
.Case(CRInSel
.WHOLE_REG
):
651 comb
+= self
.whole_reg
.ok
.eq(1)
652 move_one
= Signal(reset_less
=True)
653 comb
+= move_one
.eq(self
.insn_in
[20]) # MSB0 bit 11
654 with m
.If((op
.internal_op
== MicrOp
.OP_MFCR
) & move_one
):
655 # must one-hot the FXM field
656 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
657 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
659 # otherwise use all of it
660 comb
+= self
.whole_reg
.data
.eq(0xff)
665 class DecodeCROut(Elaboratable
):
666 """Decodes input CR from instruction
668 CR indices - insn fields - (not the data *in* the CR) require only 3
669 bits because they refer to CR0-CR7
672 def __init__(self
, dec
, op
):
675 self
.rc_in
= Signal(reset_less
=True)
676 self
.sel_in
= Signal(CROutSel
, reset_less
=True)
677 self
.insn_in
= Signal(32, reset_less
=True)
678 self
.cr_bitfield
= Data(3, "cr_bitfield")
679 self
.whole_reg
= Data(8, "cr_fxm")
680 self
.sv_override
= Signal(2, reset_less
=True) # do not do EXTRA spec
682 def elaborate(self
, platform
):
686 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
689 comb
+= self
.cr_bitfield
.ok
.eq(0)
690 comb
+= self
.whole_reg
.ok
.eq(0)
691 comb
+= self
.sv_override
.eq(0)
693 # please note these MUST match (setting of cr_bitfield.ok) exactly
694 # with write_cr0 below in PowerDecoder2. the reason it's separated
695 # is to avoid having duplicate copies of DecodeCROut in multiple
696 # PowerDecoderSubsets. register decoding should be a one-off in
697 # PowerDecoder2. see https://bugs.libre-soc.org/show_bug.cgi?id=606
699 with m
.Switch(self
.sel_in
):
700 with m
.Case(CROutSel
.NONE
):
701 pass # No bitfield activated
702 with m
.Case(CROutSel
.CR0
):
703 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
704 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
705 comb
+= self
.sv_override
.eq(1)
706 with m
.Case(CROutSel
.CR1
):
707 comb
+= self
.cr_bitfield
.data
.eq(1) # CR1 (MSB0 numbering)
708 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
709 comb
+= self
.sv_override
.eq(2)
710 with m
.Case(CROutSel
.BF
):
711 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BF
)
712 comb
+= self
.cr_bitfield
.ok
.eq(1)
713 with m
.Case(CROutSel
.BT
):
714 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormXL
.BT
[2:5])
715 comb
+= self
.cr_bitfield
.ok
.eq(1)
716 with m
.Case(CROutSel
.WHOLE_REG
):
717 comb
+= self
.whole_reg
.ok
.eq(1)
718 move_one
= Signal(reset_less
=True)
719 comb
+= move_one
.eq(self
.insn_in
[20])
720 with m
.If((op
.internal_op
== MicrOp
.OP_MTCRF
)):
722 # must one-hot the FXM field
723 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
724 with m
.If(ppick
.en_o
):
725 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
727 comb
+= self
.whole_reg
.data
.eq(0b00000001) # CR7
729 comb
+= self
.whole_reg
.data
.eq(self
.dec
.FXM
)
731 # otherwise use all of it
732 comb
+= self
.whole_reg
.data
.eq(0xff)
737 # dictionary of Input Record field names that, if they exist,
738 # will need a corresponding CSV Decoder file column (actually, PowerOp)
739 # to be decoded (this includes the single bit names)
740 record_names
= {'insn_type': 'internal_op',
741 'fn_unit': 'function_unit',
742 'SV_Ptype': 'SV_Ptype',
746 'imm_data': 'in2_sel',
747 'invert_in': 'inv_a',
748 'invert_out': 'inv_out',
751 'output_carry': 'cry_out',
752 'input_carry': 'cry_in',
753 'is_32bit': 'is_32b',
756 'data_len': 'ldst_len',
758 'byte_reverse': 'br',
759 'sign_extend': 'sgn_ext',
764 class PowerDecodeSubset(Elaboratable
):
765 """PowerDecodeSubset: dynamic subset decoder
767 only fields actually requested are copied over. hence, "subset" (duh).
770 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False, state
=None,
771 svp64_en
=True, regreduce_en
=False, fp_en
=False):
773 self
.svp64_en
= svp64_en
774 self
.regreduce_en
= regreduce_en
777 self
.is_svp64_mode
= Signal() # mark decoding as SVP64 Mode
778 self
.implicit_rs
= Signal() # implicit RS/FRS
779 self
.extend_rb_maxvl
= Signal() # jumps RB by an additional MAXVL
780 self
.extend_rc_maxvl
= Signal() # jumps RS by MAXVL from RC
781 self
.sv_rm
= SVP64Rec(name
="dec_svp64") # SVP64 RM field
782 self
.rm_dec
= SVP64RMModeDecode("svp64_rm_dec")
783 # set these to the predicate mask bits needed for the ALU
784 self
.pred_sm
= Signal() # TODO expand to SIMD mask width
785 self
.pred_dm
= Signal() # TODO expand to SIMD mask width
786 self
.sv_a_nz
= Signal(1)
789 self
.fn_name
= fn_name
791 opkls
= Decode2ToOperand
792 self
.do
= opkls(fn_name
)
794 col_subset
= self
.get_col_subset(self
.do
)
795 row_subset
= self
.rowsubsetfn
800 # "conditions" for Decoders, to enable some weird and wonderful
801 # alternatives. useful for PCR (Program Compatibility Register)
802 # amongst other things
805 # XXX NO 'SVP64FFT': self.use_svp64_fft,
810 # only needed for "main" PowerDecode2
812 self
.e
= Decode2ToExecute1Type(name
=self
.fn_name
, do
=self
.do
,
813 regreduce_en
=regreduce_en
)
815 # create decoder if one not already given
817 dec
= create_pdecode(name
=fn_name
, col_subset
=col_subset
,
818 row_subset
=row_subset
,
819 conditions
=conditions
, include_fp
=fp_en
)
822 # set up a copy of the PowerOp
823 self
.op
= PowerOp
.like(self
.dec
.op
)
825 # state information needed by the Decoder
827 state
= CoreState("dec2")
830 def get_col_subset(self
, do
):
831 subset
= {'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
832 for k
, v
in record_names
.items():
835 log("get_col_subset", self
.fn_name
, do
.fields
, subset
)
838 def rowsubsetfn(self
, opcode
, row
):
839 """select per-Function-Unit subset of opcodes to be processed
841 normally this just looks at the "unit" column. MMU is different
842 in that it processes specific SPR set/get operations that the SPR
845 return (row
['unit'] == self
.fn_name
or
846 # sigh a dreadful hack: MTSPR and MFSPR need to be processed
847 # by the MMU pipeline so we direct those opcodes to MMU **AND**
848 # SPR pipelines, then selectively weed out the SPRs that should
849 # or should not not go to each pipeline, further down.
850 # really this should be done by modifying the CSV syntax
851 # to support multiple tasks (unit column multiple entries)
852 # see https://bugs.libre-soc.org/show_bug.cgi?id=310
853 (self
.fn_name
== 'MMU' and row
['unit'] == 'SPR' and
854 row
['internal op'] in ['OP_MTSPR', 'OP_MFSPR']) or
855 # urrr... and the KAIVB SPR, which must also be redirected
856 # (to the TRAP pipeline)
857 # see https://bugs.libre-soc.org/show_bug.cgi?id=859
858 (self
.fn_name
== 'TRAP' and row
['unit'] == 'SPR' and
859 row
['internal op'] in ['OP_MTSPR', 'OP_MFSPR'])
863 ports
= self
.dec
.ports() + self
.e
.ports()
865 ports
+= self
.sv_rm
.ports()
866 ports
.append(self
.is_svp64_mode
)
867 ports
.append(self
.implicit_rs
)
870 def needs_field(self
, field
, op_field
):
875 return hasattr(do
, field
) and self
.op_get(op_field
) is not None
877 def do_get(self
, field
, final
=False):
878 if final
or self
.final
:
882 return getattr(do
, field
, None)
884 def do_copy(self
, field
, val
, final
=False):
885 df
= self
.do_get(field
, final
)
886 if df
is not None and val
is not None:
890 def op_get(self
, op_field
):
891 return getattr(self
.op
, op_field
, None)
893 def elaborate(self
, platform
):
894 if self
.regreduce_en
:
901 op
, do
= self
.dec
.op
, self
.do
902 msr
, cia
, svstate
= state
.msr
, state
.pc
, state
.svstate
903 # fill in for a normal instruction (not an exception)
904 # copy over if non-exception, non-privileged etc. is detected
906 if self
.fn_name
is None:
909 name
= self
.fn_name
+ "tmp"
910 self
.e_tmp
= Decode2ToExecute1Type(name
=name
, opkls
=self
.opkls
,
911 regreduce_en
=self
.regreduce_en
)
913 # set up submodule decoders
914 m
.submodules
.dec
= dec
= self
.dec
915 m
.submodules
.dec_rc
= self
.dec_rc
= dec_rc
= DecodeRC(self
.dec
)
916 m
.submodules
.dec_oe
= dec_oe
= DecodeOE(self
.dec
, op
)
919 # and SVP64 RM mode decoder
920 m
.submodules
.sv_rm_dec
= rm_dec
= self
.rm_dec
922 # copy op from decoder
923 comb
+= self
.op
.eq(self
.dec
.op
)
925 # copy instruction through...
926 for i
in [do
.insn
, dec_rc
.insn_in
, dec_oe
.insn_in
, ]:
927 comb
+= i
.eq(self
.dec
.opcode_in
)
929 # ...and subdecoders' input fields
930 comb
+= dec_rc
.sel_in
.eq(self
.op_get("rc_sel"))
931 comb
+= dec_oe
.sel_in
.eq(self
.op_get("rc_sel")) # XXX should be OE sel
934 comb
+= self
.do_copy("msr", msr
)
935 comb
+= self
.do_copy("cia", cia
)
936 comb
+= self
.do_copy("svstate", svstate
)
938 # set up instruction type
939 # no op: defaults to OP_ILLEGAL
940 internal_op
= self
.op_get("internal_op")
941 comb
+= self
.do_copy("insn_type", internal_op
)
943 # function unit for decoded instruction: requires minor redirect
945 fn
= self
.op_get("function_unit")
946 spr
= Signal(10, reset_less
=True)
947 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
949 # Microwatt doesn't implement the partition table
950 # instead has PRTBL register (SPR) to point to process table
951 # Kestrel has a KAIVB SPR to "rebase" exceptions. rebasing is normally
952 # done with Hypervisor Mode which is not implemented (yet)
954 is_mmu_spr
= Signal()
955 is_trap_spr
= Signal()
956 comb
+= is_spr_mv
.eq((internal_op
== MicrOp
.OP_MTSPR
) |
957 (internal_op
== MicrOp
.OP_MFSPR
))
958 comb
+= is_mmu_spr
.eq((spr
== SPR
.DSISR
.value
) |
959 (spr
== SPR
.DAR
.value
) |
960 (spr
== SPR
.PRTBL
.value
) |
961 (spr
== SPR
.PIDR
.value
))
962 comb
+= is_trap_spr
.eq((spr
== SPR
.KAIVB
.value
)
964 # MMU must receive MMU SPRs
965 with m
.If(is_spr_mv
& (fn
== Function
.SPR
) & is_mmu_spr
):
966 comb
+= self
.do_copy("fn_unit", Function
.MMU
)
967 comb
+= self
.do_copy("insn_type", internal_op
)
968 # TRAP must receive TRAP SPR KAIVB
969 with m
.If(is_spr_mv
& (fn
== Function
.SPR
) & is_trap_spr
):
970 comb
+= self
.do_copy("fn_unit", Function
.TRAP
)
971 comb
+= self
.do_copy("insn_type", internal_op
)
972 # SPR pipe must *not* receive MMU or TRAP SPRs
973 with m
.Elif(is_spr_mv
& ((fn
== Function
.MMU
) & ~is_mmu_spr
) &
974 ((fn
== Function
.TRAP
) & ~is_trap_spr
)):
975 comb
+= self
.do_copy("fn_unit", Function
.NONE
)
976 comb
+= self
.do_copy("insn_type", MicrOp
.OP_ILLEGAL
)
979 comb
+= self
.do_copy("fn_unit", fn
)
982 if self
.needs_field("zero_a", "in1_sel"):
983 m
.submodules
.dec_ai
= dec_ai
= DecodeAImm(self
.dec
)
984 comb
+= dec_ai
.sv_nz
.eq(self
.sv_a_nz
)
985 comb
+= dec_ai
.sel_in
.eq(self
.op_get("in1_sel"))
986 comb
+= self
.do_copy("zero_a", dec_ai
.immz_out
) # RA==0 detected
987 if self
.needs_field("imm_data", "in2_sel"):
988 m
.submodules
.dec_bi
= dec_bi
= DecodeBImm(self
.dec
)
989 comb
+= dec_bi
.sel_in
.eq(self
.op_get("in2_sel"))
990 comb
+= self
.do_copy("imm_data", dec_bi
.imm_out
) # imm in RB
992 # CR in/out - note: these MUST match with what happens in
994 rc_out
= self
.dec_rc
.rc_out
.data
995 with m
.Switch(self
.op_get("cr_out")):
996 with m
.Case(CROutSel
.CR0
, CROutSel
.CR1
):
997 comb
+= self
.do_copy("write_cr0", rc_out
) # only when RC=1
998 with m
.Case(CROutSel
.BF
, CROutSel
.BT
):
999 comb
+= self
.do_copy("write_cr0", 1)
1001 comb
+= self
.do_copy("input_cr", self
.op_get("cr_in")) # CR in
1002 comb
+= self
.do_copy("output_cr", self
.op_get("cr_out")) # CR out
1005 # connect up SVP64 RM Mode decoding. however... we need a shorter
1006 # path, for the LDST bit-reverse detection. so perform partial
1007 # decode when SVP64 is detected. then, bit-reverse mode can be
1008 # quickly determined, and the Decoder result MUXed over to
1009 # the alternative decoder, svdecldst. what a mess... *sigh*
1010 sv_ptype
= self
.op_get("SV_Ptype")
1011 fn
= self
.op_get("function_unit")
1012 comb
+= rm_dec
.fn_in
.eq(fn
) # decode needs to know Fn type
1013 comb
+= rm_dec
.ptype_in
.eq(sv_ptype
) # Single/Twin predicated
1014 comb
+= rm_dec
.rc_in
.eq(rc_out
) # Rc=1
1015 comb
+= rm_dec
.rm_in
.eq(self
.sv_rm
) # SVP64 RM mode
1016 if self
.needs_field("imm_data", "in2_sel"):
1017 bzero
= dec_bi
.imm_out
.ok
& ~dec_bi
.imm_out
.data
.bool()
1018 comb
+= rm_dec
.ldst_imz_in
.eq(bzero
) # B immediate is zero
1020 # main PowerDecoder2 determines if different SVP64 modes enabled
1021 # detect if SVP64 FFT mode enabled (really bad hack),
1022 # exclude fcfids and others
1023 # XXX this is a REALLY bad hack, REALLY has to be done better.
1024 # likely with a sub-decoder.
1025 # what this ultimately does is enable the 2nd implicit register
1026 # (FRS) for SVP64-decoding. all of these instructions are
1027 # 3-in 2-out but there is not enough room either in the
1028 # opcode *or* EXTRA2/3 to specify a 5th operand.
1030 comb
+= major
.eq(self
.dec
.opcode_in
[26:32])
1032 comb
+= xo
.eq(self
.dec
.opcode_in
[1:11])
1033 comb
+= self
.implicit_rs
.eq(0)
1034 comb
+= self
.extend_rb_maxvl
.eq(0)
1035 comb
+= self
.extend_rc_maxvl
.eq(0)
1036 with m
.If((major
== 59) & xo
.matches(
1037 '-----00100', # ffmsubs
1038 '-----00101', # ffmadds
1039 '-----00110', # ffnmsubs
1040 '-----00111', # ffnmadds
1041 '1111100000', # ffadds
1042 '-----11011', # fdmadds
1044 comb
+= self
.implicit_rs
.eq(1)
1045 comb
+= self
.extend_rb_maxvl
.eq(1) # extend RB
1047 comb
+= xo6
.eq(self
.dec
.opcode_in
[0:6])
1048 with m
.If((major
== 4) & xo6
.matches(
1051 '110100', # divmod2du
1053 comb
+= self
.implicit_rs
.eq(1)
1054 comb
+= self
.extend_rc_maxvl
.eq(1) # RS=RT+MAXVL or RS=RC
1057 comb
+= self
.do_copy("rc", dec_rc
.rc_out
)
1059 # OE only enabled when SVP64 not active
1060 with m
.If(~self
.is_svp64_mode
):
1061 comb
+= self
.do_copy("oe", dec_oe
.oe_out
)
1062 # RC1 overrides Rc if rc type is NONE or ONE or Rc=0, in svp64_mode
1063 # for instructions with a forced-Rc=1 (stbcx., pcdec.)
1064 # the RC1 RM bit *becomes* Rc=0/1, but for instructions
1065 # that have Rc=0/1 then when Rc=0 RC1 *becomes* (replaces) Rc.
1066 with m
.Elif((dec_rc
.sel_in
.matches(RCOE
.RC
, RCOE
.RC_ONLY
) &
1067 dec_rc
.rc_out
.data
== 0) |
1068 (dec_rc
.sel_in
== RCOE
.ONE
)):
1069 RC1
= Data(1, "RC1")
1070 comb
+= RC1
.ok
.eq(rm_dec
.RC1
)
1071 comb
+= RC1
.RC1
.eq(rm_dec
.RC1
)
1072 comb
+= self
.do_copy("rc", RC1
)
1074 comb
+= self
.do_copy("oe", dec_oe
.oe_out
)
1076 # decoded/selected instruction flags
1077 comb
+= self
.do_copy("data_len", self
.op_get("ldst_len"))
1078 comb
+= self
.do_copy("invert_in", self
.op_get("inv_a"))
1079 comb
+= self
.do_copy("invert_out", self
.op_get("inv_out"))
1080 comb
+= self
.do_copy("input_carry", self
.op_get("cry_in"))
1081 comb
+= self
.do_copy("output_carry", self
.op_get("cry_out"))
1082 comb
+= self
.do_copy("is_32bit", self
.op_get("is_32b"))
1083 comb
+= self
.do_copy("is_signed", self
.op_get("sgn"))
1084 lk
= self
.op_get("lk")
1087 comb
+= self
.do_copy("lk", self
.dec
.LK
) # XXX TODO: accessor
1089 comb
+= self
.do_copy("byte_reverse", self
.op_get("br"))
1090 comb
+= self
.do_copy("sign_extend", self
.op_get("sgn_ext"))
1091 comb
+= self
.do_copy("ldst_mode", self
.op_get("upd")) # LD/ST mode
1092 comb
+= self
.do_copy("reserve", self
.op_get("rsrv")) # atomic
1094 # copy over SVP64 input record fields (if they exist)
1096 # TODO, really do we have to do these explicitly?? sigh
1097 # for (field, _) in sv_input_record_layout:
1098 # comb += self.do_copy(field, self.rm_dec.op_get(field))
1099 comb
+= self
.do_copy("sv_saturate", self
.rm_dec
.saturate
)
1100 comb
+= self
.do_copy("sv_Ptype", self
.rm_dec
.ptype_in
)
1101 comb
+= self
.do_copy("sv_ldstmode", self
.rm_dec
.ldstmode
)
1102 # these get set up based on incoming mask bits. TODO:
1103 # pass in multiple bits (later, when SIMD backends are enabled)
1104 with m
.If(self
.rm_dec
.pred_sz
):
1105 comb
+= self
.do_copy("sv_pred_sz", ~self
.pred_sm
)
1106 with m
.If(self
.rm_dec
.pred_dz
):
1107 comb
+= self
.do_copy("sv_pred_dz", ~self
.pred_dm
)
1112 class PowerDecode2(PowerDecodeSubset
):
1113 """PowerDecode2: the main instruction decoder.
1115 whilst PowerDecode is responsible for decoding the actual opcode, this
1116 module encapsulates further specialist, sparse information and
1117 expansion of fields that is inconvenient to have in the CSV files.
1118 for example: the encoding of the immediates, which are detected
1119 and expanded out to their full value from an annotated (enum)
1122 implicit register usage is also set up, here. for example: OP_BC
1123 requires implicitly reading CTR, OP_RFID requires implicitly writing
1126 in addition, PowerDecoder2 is responsible for detecting whether
1127 instructions are illegal (or privileged) or not, and instead of
1128 just leaving at that, *replacing* the instruction to execute with
1129 a suitable alternative (trap).
1131 LDSTExceptions are done the cycle _after_ they're detected (after
1132 they come out of LDSTCompUnit). basically despite the instruction
1133 being decoded, the results of the decode are completely ignored
1134 and "exception.happened" used to set the "actual" instruction to
1135 "OP_TRAP". the LDSTException data structure gets filled in,
1136 in the CompTrapOpSubset and that's what it fills in SRR.
1138 to make this work, TestIssuer must notice "exception.happened"
1139 after the (failed) LD/ST and copies the LDSTException info from
1140 the output, into here (PowerDecoder2). without incrementing PC.
1142 also instr_fault works the same way: the instruction is "rewritten"
1143 so that the "fake" op that gets created is OP_FETCH_FAILED
1146 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False,
1147 state
=None, svp64_en
=True, regreduce_en
=False, fp_en
=False):
1148 super().__init
__(dec
, opkls
, fn_name
, final
, state
, svp64_en
,
1149 regreduce_en
=False, fp_en
=fp_en
)
1150 self
.ldst_exc
= LDSTException("dec2_exc") # rewrites as OP_TRAP
1151 self
.instr_fault
= Signal() # rewrites instruction as OP_FETCH_FAILED
1154 self
.cr_out_isvec
= Signal(1, name
="cr_out_isvec")
1155 self
.cr_in_isvec
= Signal(1, name
="cr_in_isvec")
1156 self
.cr_in_b_isvec
= Signal(1, name
="cr_in_b_isvec")
1157 self
.cr_in_o_isvec
= Signal(1, name
="cr_in_o_isvec")
1158 self
.in1_isvec
= Signal(1, name
="reg_a_isvec")
1159 self
.in2_isvec
= Signal(1, name
="reg_b_isvec")
1160 self
.in3_isvec
= Signal(1, name
="reg_c_isvec")
1161 self
.o_isvec
= Signal(7, name
="reg_o_isvec")
1162 self
.o2_isvec
= Signal(7, name
="reg_o2_isvec")
1163 self
.in1_step
= Signal(7, name
="reg_a_step")
1164 self
.in2_step
= Signal(7, name
="reg_b_step")
1165 self
.in3_step
= Signal(7, name
="reg_c_step")
1166 self
.o_step
= Signal(7, name
="reg_o_step")
1167 self
.o2_step
= Signal(7, name
="reg_o2_step")
1168 self
.remap_active
= Signal(5, name
="remap_active") # per reg
1169 self
.no_in_vec
= Signal(1, name
="no_in_vec") # no inputs vector
1170 self
.no_out_vec
= Signal(1, name
="no_out_vec") # no outputs vector
1171 self
.loop_continue
= Signal(1, name
="loop_continue")
1173 self
.no_in_vec
= Const(1, 1)
1174 self
.no_out_vec
= Const(1, 1)
1175 self
.loop_continue
= Const(0, 1)
1177 def get_col_subset(self
, opkls
):
1178 subset
= super().get_col_subset(opkls
)
1179 subset
.add("asmcode")
1180 subset
.add("in1_sel")
1181 subset
.add("in2_sel")
1182 subset
.add("in3_sel")
1183 subset
.add("out_sel")
1185 subset
.add("sv_in1")
1186 subset
.add("sv_in2")
1187 subset
.add("sv_in3")
1188 subset
.add("sv_out")
1189 subset
.add("sv_out2")
1190 subset
.add("sv_cr_in")
1191 subset
.add("sv_cr_out")
1192 subset
.add("SV_Etype")
1193 subset
.add("SV_Ptype")
1194 # from SVP64RMModeDecode
1195 for (field
, _
) in sv_input_record_layout
:
1198 subset
.add("internal_op")
1202 def elaborate(self
, platform
):
1203 m
= super().elaborate(platform
)
1206 op
, e_out
, do_out
= self
.op
, self
.e
, self
.e
.do
1207 dec_spr
, msr
, cia
, ext_irq
= state
.dec
, state
.msr
, state
.pc
, state
.eint
1208 rc_out
= self
.dec_rc
.rc_out
.data
1212 # fill in for a normal instruction (not an exception)
1213 # copy over if non-exception, non-privileged etc. is detected
1215 # set up submodule decoders
1216 m
.submodules
.dec_a
= dec_a
= DecodeA(self
.dec
, op
, self
.regreduce_en
)
1217 m
.submodules
.dec_b
= dec_b
= DecodeB(self
.dec
, op
)
1218 m
.submodules
.dec_c
= dec_c
= DecodeC(self
.dec
, op
)
1219 m
.submodules
.dec_o
= dec_o
= DecodeOut(self
.dec
, op
, self
.regreduce_en
)
1220 m
.submodules
.dec_o2
= dec_o2
= DecodeOut2(self
.dec
, op
)
1221 m
.submodules
.dec_cr_in
= self
.dec_cr_in
= DecodeCRIn(self
.dec
, op
)
1222 m
.submodules
.dec_cr_out
= self
.dec_cr_out
= DecodeCROut(self
.dec
, op
)
1223 comb
+= dec_a
.sv_nz
.eq(self
.sv_a_nz
)
1226 # and SVP64 Extra decoders
1227 m
.submodules
.crout_svdec
= crout_svdec
= SVP64CRExtra()
1228 m
.submodules
.crin_svdec
= crin_svdec
= SVP64CRExtra()
1229 m
.submodules
.crin_svdec_b
= crin_svdec_b
= SVP64CRExtra()
1230 m
.submodules
.crin_svdec_o
= crin_svdec_o
= SVP64CRExtra()
1231 m
.submodules
.in1_svdec
= in1_svdec
= SVP64RegExtra()
1232 m
.submodules
.in2_svdec
= in2_svdec
= SVP64RegExtra()
1233 m
.submodules
.in3_svdec
= in3_svdec
= SVP64RegExtra()
1234 m
.submodules
.o_svdec
= o_svdec
= SVP64RegExtra()
1235 m
.submodules
.o2_svdec
= o2_svdec
= SVP64RegExtra()
1237 # debug access to cr svdec (used in get_pdecode_cr_in/out)
1238 self
.crout_svdec
= crout_svdec
1239 self
.crin_svdec
= crin_svdec
1241 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
1242 reg
= Signal(5, reset_less
=True)
1244 # copy instruction through...
1245 for i
in [do
.insn
, dec_a
.insn_in
, dec_b
.insn_in
,
1246 self
.dec_cr_in
.insn_in
, self
.dec_cr_out
.insn_in
,
1247 dec_c
.insn_in
, dec_o
.insn_in
, dec_o2
.insn_in
]:
1248 comb
+= i
.eq(self
.dec
.opcode_in
)
1251 comb
+= self
.dec_cr_in
.sel_in
.eq(self
.op_get("cr_in"))
1252 comb
+= self
.dec_cr_out
.sel_in
.eq(self
.op_get("cr_out"))
1253 comb
+= self
.dec_cr_out
.rc_in
.eq(rc_out
)
1256 comb
+= self
.do_copy("read_cr_whole", self
.dec_cr_in
.whole_reg
)
1257 comb
+= self
.do_copy("write_cr_whole", self
.dec_cr_out
.whole_reg
)
1259 # ...and subdecoders' input fields
1260 comb
+= dec_a
.sel_in
.eq(self
.op_get("in1_sel"))
1261 comb
+= dec_b
.sel_in
.eq(self
.op_get("in2_sel"))
1262 comb
+= dec_c
.sel_in
.eq(self
.op_get("in3_sel"))
1263 comb
+= dec_o
.sel_in
.eq(self
.op_get("out_sel"))
1264 comb
+= dec_o2
.sel_in
.eq(self
.op_get("out_sel"))
1266 comb
+= dec_o2
.implicit_rs
.eq(self
.implicit_rs
)
1267 comb
+= dec_o2
.implicit_from_rc
.eq(self
.extend_rc_maxvl
)
1268 if hasattr(do
, "lk"):
1269 comb
+= dec_o2
.lk
.eq(do
.lk
)
1272 # now do the SVP64 munging. op.SV_Etype and op.sv_in1 comes from
1273 # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
1274 # which in turn were auto-generated by sv_analysis.py
1275 extra
= self
.sv_rm
.extra
# SVP64 extra bits 10:18
1280 comb
+= crout_svdec
.idx
.eq(self
.op_get("sv_cr_out"))
1281 comb
+= self
.cr_out_isvec
.eq(crout_svdec
.isvec
)
1284 # CR in - selection slightly different due to shared CR field sigh
1285 cr_a_idx
= Signal(SVEXTRA
)
1286 cr_b_idx
= Signal(SVEXTRA
)
1288 # these change slightly, when decoding BA/BB. really should have
1289 # their own separate CSV column: sv_cr_in1 and sv_cr_in2, but hey
1290 comb
+= cr_a_idx
.eq(self
.op_get("sv_cr_in"))
1291 comb
+= cr_b_idx
.eq(SVEXTRA
.NONE
)
1292 with m
.If(self
.op_get("sv_cr_in") == SVEXTRA
.Idx_1_2
.value
):
1293 comb
+= cr_a_idx
.eq(SVEXTRA
.Idx1
)
1294 comb
+= cr_b_idx
.eq(SVEXTRA
.Idx2
)
1296 comb
+= self
.cr_in_isvec
.eq(crin_svdec
.isvec
)
1297 comb
+= self
.cr_in_b_isvec
.eq(crin_svdec_b
.isvec
)
1298 comb
+= self
.cr_in_o_isvec
.eq(crin_svdec_o
.isvec
)
1300 # indices are slightly different, BA/BB mess sorted above
1301 comb
+= crin_svdec
.idx
.eq(cr_a_idx
) # SVP64 CR in A
1302 comb
+= crin_svdec_b
.idx
.eq(cr_b_idx
) # SVP64 CR in B
1304 comb
+= crin_svdec_o
.idx
.eq(self
.op_get("sv_cr_out"))
1306 # get SVSTATE srcstep (TODO: elwidth etc.) needed below
1307 vl
= Signal
.like(self
.state
.svstate
.vl
)
1308 maxvl
= Signal
.like(self
.state
.svstate
.maxvl
)
1309 subvl
= Signal
.like(self
.rm_dec
.rm_in
.subvl
)
1310 srcstep
= Signal
.like(self
.state
.svstate
.srcstep
)
1311 dststep
= Signal
.like(self
.state
.svstate
.dststep
)
1312 ssubstep
= Signal
.like(self
.state
.svstate
.ssubstep
)
1313 dsubstep
= Signal
.like(self
.state
.svstate
.ssubstep
)
1314 comb
+= vl
.eq(self
.state
.svstate
.vl
)
1315 comb
+= maxvl
.eq(self
.state
.svstate
.maxvl
)
1316 comb
+= subvl
.eq(self
.rm_dec
.rm_in
.subvl
)
1317 comb
+= srcstep
.eq(self
.state
.svstate
.srcstep
)
1318 comb
+= dststep
.eq(self
.state
.svstate
.dststep
)
1319 comb
+= ssubstep
.eq(self
.state
.svstate
.ssubstep
)
1320 comb
+= dsubstep
.eq(self
.state
.svstate
.dsubstep
)
1322 in1_step
, in2_step
= self
.in1_step
, self
.in2_step
1323 in3_step
= self
.in3_step
1324 o_step
, o2_step
= self
.o_step
, self
.o2_step
1326 # multiply vl by subvl - note that this is only 7 bit!
1327 # when elwidth overrides get involved this will have to go up
1329 comb
+= vmax
.eq(vl
*(subvl
+1))
1331 # registers a, b, c and out and out2 (LD/ST EA)
1332 sv_etype
= self
.op_get("SV_Etype")
1333 for i
, stuff
in enumerate((
1334 ("RA", e
.read_reg1
, dec_a
.reg_out
, in1_svdec
, in1_step
, False),
1335 ("RB", e
.read_reg2
, dec_b
.reg_out
, in2_svdec
, in2_step
, False),
1336 ("RC", e
.read_reg3
, dec_c
.reg_out
, in3_svdec
, in3_step
, False),
1337 ("RT", e
.write_reg
, dec_o
.reg_out
, o_svdec
, o_step
, True),
1338 ("EA", e
.write_ea
, dec_o2
.reg_out
, o2_svdec
, o2_step
, True))):
1339 rname
, to_reg
, fromreg
, svdec
, remapstep
, out
= stuff
1340 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1341 comb
+= svdec
.etype
.eq(sv_etype
) # EXTRA2/3 for this insn
1342 comb
+= svdec
.reg_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1343 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1344 # *screaam* FFT mode needs an extra offset for RB
1345 # similar to FRS/FRT (below). all of this needs cleanup
1346 offs
= Signal(7, name
="offs_"+rname
, reset_less
=True)
1349 # when FFT sv.ffmadd detected, and REMAP not in use,
1350 # automagically add on an extra offset to RB.
1351 # however when REMAP is active, the FFT REMAP
1352 # schedule takes care of this offset.
1353 with m
.If(dec_o2
.reg_out
.ok
& dec_o2
.rs_en
&
1354 self
.extend_rb_maxvl
):
1355 with m
.If(~self
.remap_active
[i
]):
1356 with m
.If(svdec
.isvec
):
1357 comb
+= offs
.eq(maxvl
) # MAXVL for Vectors
1358 # detect if Vectorised: add srcstep/dststep if yes.
1359 # to_reg is 7-bits, outs get dststep added, ins get srcstep
1360 with m
.If(svdec
.isvec
):
1361 selectstep
= dststep
if out
else srcstep
1362 subselect
= dsubstep
if out
else ssubstep
1363 step
= Signal(7, name
="step_%s" % rname
.lower())
1364 with m
.If(self
.remap_active
[i
]):
1365 comb
+= step
.eq((remapstep
*(subvl
+1))+subselect
)
1367 comb
+= step
.eq((selectstep
*(subvl
+1))+subselect
)
1368 # reverse gear goes the opposite way
1369 with m
.If(self
.rm_dec
.reverse_gear
):
1370 comb
+= to_reg
.data
.eq(offs
+svdec
.reg_out
+(vmax
-1-step
))
1372 comb
+= to_reg
.data
.eq(offs
+step
+svdec
.reg_out
)
1374 comb
+= to_reg
.data
.eq(offs
+svdec
.reg_out
)
1376 # SVP64 in/out fields
1377 comb
+= in1_svdec
.idx
.eq(self
.op_get("sv_in1")) # reg #1 (in1_sel)
1378 comb
+= in2_svdec
.idx
.eq(self
.op_get("sv_in2")) # reg #2 (in2_sel)
1379 comb
+= in3_svdec
.idx
.eq(self
.op_get("sv_in3")) # reg #3 (in3_sel)
1380 comb
+= o_svdec
.idx
.eq(self
.op_get("sv_out")) # output (out_sel)
1382 comb
+= o2_svdec
.idx
.eq(self
.op_get("sv_out2"))
1383 # XXX TODO - work out where this should come from. the problem is
1384 # that LD-with-update is implied (computed from "is instruction in
1385 # "update mode" rather than specified cleanly as its own CSV column
1387 # output reg-is-vectorised (and when no in/out is vectorised)
1388 comb
+= self
.in1_isvec
.eq(in1_svdec
.isvec
)
1389 comb
+= self
.in2_isvec
.eq(in2_svdec
.isvec
)
1390 comb
+= self
.in3_isvec
.eq(in3_svdec
.isvec
)
1391 comb
+= self
.o_isvec
.eq(o_svdec
.isvec
)
1392 comb
+= self
.o2_isvec
.eq(o2_svdec
.isvec
)
1394 # urrr... don't ask... the implicit register FRS in FFT mode
1395 # "tracks" FRT exactly except it's offset by MAXVL. rather than
1396 # mess up the above with if-statements, override it here.
1397 # same trick is applied to FRB, above, but it's a lot cleaner there
1398 with m
.If(dec_o2
.reg_out
.ok
& dec_o2
.rs_en
):
1399 imp_reg_out
= Signal(7)
1400 imp_isvec
= Signal(1)
1401 with m
.If(self
.extend_rc_maxvl
): # maddedu etc. from RC
1402 comb
+= imp_isvec
.eq(in3_svdec
.isvec
)
1403 comb
+= imp_reg_out
.eq(in3_svdec
.reg_out
)
1405 comb
+= imp_isvec
.eq(o_svdec
.isvec
)
1406 comb
+= imp_reg_out
.eq(o_svdec
.reg_out
)
1408 with m
.If(~self
.remap_active
[4]):
1409 with m
.If(imp_isvec
):
1410 comb
+= offs
.eq(maxvl
) # MAXVL for Vectors
1411 with m
.Elif(self
.extend_rc_maxvl
): # maddedu etc. from RC
1412 comb
+= offs
.eq(0) # keep as RC
1414 comb
+= offs
.eq(1) # add 1 if scalar
1415 with m
.If(imp_isvec
):
1416 step
= Signal(7, name
="step_%s" % rname
.lower())
1417 with m
.If(self
.remap_active
[4]):
1418 with m
.If(self
.extend_rc_maxvl
): # maddedu etc. from RC
1419 comb
+= step
.eq(in3_step
)
1421 comb
+= step
.eq(o2_step
)
1423 comb
+= step
.eq(dststep
)
1424 # reverse gear goes the opposite way
1425 with m
.If(self
.rm_dec
.reverse_gear
):
1426 roffs
= offs
+(vl
-1-step
)
1427 comb
+= to_reg
.data
.eq(roffs
+imp_reg_out
)
1429 comb
+= to_reg
.data
.eq(offs
+step
+imp_reg_out
)
1431 comb
+= to_reg
.data
.eq(offs
+imp_reg_out
)
1432 # ... but write to *second* output
1433 comb
+= self
.o2_isvec
.eq(imp_isvec
)
1434 comb
+= o2_svdec
.idx
.eq(self
.op_get("sv_out"))
1436 # TODO add SPRs here. must be True when *all* are scalar
1437 l
= map(lambda svdec
: svdec
.isvec
, [in1_svdec
, in2_svdec
, in3_svdec
,
1438 crin_svdec
, crin_svdec_b
,
1440 comb
+= self
.no_in_vec
.eq(~
Cat(*l
).bool()) # all input scalar
1441 l
= map(lambda svdec
: svdec
.isvec
, [
1442 o2_svdec
, o_svdec
, crout_svdec
])
1443 # in mapreduce mode, scalar out is *allowed*
1444 with m
.If(self
.rm_dec
.mode
== SVP64RMMode
.MAPREDUCE
.value
):
1445 comb
+= self
.no_out_vec
.eq(0)
1448 comb
+= self
.no_out_vec
.eq(~
Cat(*l
).bool())
1449 # now create a general-purpose "test" as to whether looping
1450 # should continue. this doesn't include predication bit-tests
1451 loop
= self
.loop_continue
1452 with m
.Switch(self
.op_get("SV_Ptype")):
1453 with m
.Case(SVPtype
.P2
.value
):
1455 # TODO: *and cache-inhibited LD/ST!*
1456 comb
+= loop
.eq(~
(self
.no_in_vec | self
.no_out_vec
))
1457 with m
.Case(SVPtype
.P1
.value
):
1458 # single-predication, test relies on dest only
1459 comb
+= loop
.eq(~self
.no_out_vec
)
1461 # not an SV operation, no looping
1464 # condition registers (CR)
1465 for to_reg
, cr
, name
, svdec
, out
in (
1466 (e
.read_cr1
, self
.dec_cr_in
, "cr_bitfield", crin_svdec
, 0),
1467 (e
.read_cr2
, self
.dec_cr_in
, "cr_bitfield_b", crin_svdec_b
, 0),
1468 (e
.read_cr3
, self
.dec_cr_in
, "cr_bitfield_o", crin_svdec_o
, 0),
1469 (e
.write_cr
, self
.dec_cr_out
, "cr_bitfield", crout_svdec
, 1)):
1470 fromreg
= getattr(cr
, name
)
1471 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1472 comb
+= svdec
.etype
.eq(sv_etype
) # EXTRA2/3 for this insn
1473 comb
+= svdec
.cr_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1474 with m
.If(svdec
.isvec
):
1475 # check if this is CR0 or CR1: treated differently
1476 # (does not "listen" to EXTRA2/3 spec for a start)
1477 # also: the CRs start from completely different locations
1478 step
= dststep
if out
else srcstep
1479 with m
.If(cr
.sv_override
== 1): # CR0
1480 offs
= SVP64CROffs
.CR0
1481 comb
+= to_reg
.data
.eq(step
+offs
)
1482 with m
.Elif(cr
.sv_override
== 2): # CR1
1483 offs
= SVP64CROffs
.CR1
1484 comb
+= to_reg
.data
.eq(step
+1)
1486 comb
+= to_reg
.data
.eq(step
+svdec
.cr_out
) # 7-bit out
1488 comb
+= to_reg
.data
.eq(svdec
.cr_out
) # 7-bit output
1489 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1491 # sigh must determine if RA is nonzero (7 bit)
1492 comb
+= self
.sv_a_nz
.eq(e
.read_reg1
.data
!= Const(0, 7))
1494 # connect up to/from read/write GPRs
1495 for to_reg
, fromreg
in ((e
.read_reg1
, dec_a
.reg_out
),
1496 (e
.read_reg2
, dec_b
.reg_out
),
1497 (e
.read_reg3
, dec_c
.reg_out
),
1498 (e
.write_reg
, dec_o
.reg_out
),
1499 (e
.write_ea
, dec_o2
.reg_out
)):
1500 comb
+= to_reg
.data
.eq(fromreg
.data
)
1501 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1503 # connect up to/from read/write CRs
1504 for to_reg
, cr
, name
in (
1505 (e
.read_cr1
, self
.dec_cr_in
, "cr_bitfield", ),
1506 (e
.read_cr2
, self
.dec_cr_in
, "cr_bitfield_b", ),
1507 (e
.read_cr3
, self
.dec_cr_in
, "cr_bitfield_o", ),
1508 (e
.write_cr
, self
.dec_cr_out
, "cr_bitfield", )):
1509 fromreg
= getattr(cr
, name
)
1510 comb
+= to_reg
.data
.eq(fromreg
.data
)
1511 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1514 comb
+= self
.rm_dec
.ldst_ra_vec
.eq(self
.in1_isvec
) # RA is vector
1517 comb
+= e
.read_spr1
.eq(dec_a
.spr_out
)
1518 comb
+= e
.write_spr
.eq(dec_o
.spr_out
)
1520 # Fast regs out including SRR0/1/SVSRR0
1521 comb
+= e
.read_fast1
.eq(dec_a
.fast_out
)
1522 comb
+= e
.read_fast2
.eq(dec_b
.fast_out
)
1523 comb
+= e
.write_fast1
.eq(dec_o
.fast_out
) # SRR0 (OP_RFID)
1524 comb
+= e
.write_fast2
.eq(dec_o2
.fast_out
) # SRR1 (ditto)
1525 comb
+= e
.write_fast3
.eq(dec_o2
.fast_out3
) # SVSRR0 (ditto)
1526 # and State regs (DEC, TB)
1527 comb
+= e
.read_state1
.eq(dec_a
.state_out
) # DEC/TB
1528 comb
+= e
.write_state1
.eq(dec_o
.state_out
) # DEC/TB
1530 # sigh this is exactly the sort of thing for which the
1531 # decoder is designed to not need. MTSPR, MFSPR and others need
1532 # access to the XER bits. however setting e.oe is not appropriate
1533 internal_op
= self
.op_get("internal_op")
1534 with m
.If(internal_op
== MicrOp
.OP_MFSPR
):
1535 comb
+= e
.xer_in
.eq(0b111) # SO, CA, OV
1536 with m
.If(internal_op
== MicrOp
.OP_CMP
):
1537 comb
+= e
.xer_in
.eq(1 << XERRegsEnum
.SO
) # SO
1538 with m
.If(internal_op
== MicrOp
.OP_MTSPR
):
1539 comb
+= e
.xer_out
.eq(1)
1541 # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
1542 with m
.If(op
.internal_op
== MicrOp
.OP_TRAP
):
1543 # *DO NOT* call self.trap here. that would reset absolutely
1544 # everything including destroying read of RA and RB.
1545 comb
+= self
.do_copy("trapaddr", 0x70) # strip first nibble
1547 ####################
1548 # ok so the instruction's been decoded, blah blah, however
1549 # now we need to determine if it's actually going to go ahead...
1550 # *or* if in fact it's a privileged operation, whether there's
1551 # an external interrupt, etc. etc. this is a simple priority
1552 # if-elif-elif sequence. decrement takes highest priority,
1553 # EINT next highest, privileged operation third.
1555 # check if instruction is privileged
1556 is_priv_insn
= instr_is_priv(m
, op
.internal_op
, e
.do
.insn
)
1558 # different IRQ conditions
1559 ext_irq_ok
= Signal()
1560 dec_irq_ok
= Signal()
1563 ldst_exc
= self
.ldst_exc
1565 comb
+= ext_irq_ok
.eq(ext_irq
& msr
[MSR
.EE
]) # v3.0B p944 (MSR.EE)
1566 comb
+= dec_irq_ok
.eq(dec_spr
[63] & msr
[MSR
.EE
]) # 6.5.11 p1076
1567 comb
+= priv_ok
.eq(is_priv_insn
& msr
[MSR
.PR
])
1568 comb
+= illeg_ok
.eq(op
.internal_op
== MicrOp
.OP_ILLEGAL
)
1570 # absolute top priority: check for an instruction failed
1571 with m
.If(self
.instr_fault
):
1572 comb
+= self
.e
.eq(0) # reset eeeeeverything
1573 comb
+= self
.do_copy("insn", self
.dec
.opcode_in
, True)
1574 comb
+= self
.do_copy("insn_type", MicrOp
.OP_FETCH_FAILED
, True)
1575 comb
+= self
.do_copy("fn_unit", Function
.MMU
, True)
1576 comb
+= self
.do_copy("cia", self
.state
.pc
, True) # PC
1577 comb
+= self
.do_copy("msr", self
.state
.msr
, True) # MSR
1578 # special override on internal_op, due to being a "fake" op
1579 comb
+= self
.dec
.op
.internal_op
.eq(MicrOp
.OP_FETCH_FAILED
)
1581 # LD/ST exceptions. TestIssuer copies the exception info at us
1582 # after a failed LD/ST.
1583 with m
.Elif(ldst_exc
.happened
):
1584 with m
.If(ldst_exc
.alignment
):
1585 self
.trap(m
, TT
.MEMEXC
, 0x600)
1586 with m
.Elif(ldst_exc
.instr_fault
):
1587 with m
.If(ldst_exc
.segment_fault
):
1588 self
.trap(m
, TT
.MEMEXC
, 0x480)
1590 # pass exception info to trap to create SRR1
1591 self
.trap(m
, TT
.MEMEXC
, 0x400, ldst_exc
)
1593 with m
.If(ldst_exc
.segment_fault
):
1594 self
.trap(m
, TT
.MEMEXC
, 0x380)
1596 self
.trap(m
, TT
.MEMEXC
, 0x300)
1598 # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
1599 with m
.Elif(dec_irq_ok
):
1600 self
.trap(m
, TT
.DEC
, 0x900) # v3.0B 6.5 p1065
1602 # external interrupt? only if MSR.EE set
1603 with m
.Elif(ext_irq_ok
):
1604 self
.trap(m
, TT
.EINT
, 0x500)
1606 # privileged instruction trap
1607 with m
.Elif(priv_ok
):
1608 self
.trap(m
, TT
.PRIV
, 0x700)
1610 # illegal instruction must redirect to trap. this is done by
1611 # *overwriting* the decoded instruction and starting again.
1612 # (note: the same goes for interrupts and for privileged operations,
1613 # just with different trapaddr and traptype)
1614 with m
.Elif(illeg_ok
):
1615 # illegal instruction trap
1616 self
.trap(m
, TT
.ILLEG
, 0x700)
1618 # no exception, just copy things to the output
1622 ####################
1623 # follow-up after trap/irq to set up SRR0/1
1625 # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
1626 # Note: OP_SC could actually be modified to just be a trap
1627 with m
.If((do_out
.insn_type
== MicrOp
.OP_TRAP
) |
1628 (do_out
.insn_type
== MicrOp
.OP_SC
)):
1629 # TRAP write fast1 = SRR0
1630 comb
+= e_out
.write_fast1
.data
.eq(FastRegsEnum
.SRR0
) # SRR0
1631 comb
+= e_out
.write_fast1
.ok
.eq(1)
1632 # TRAP write fast2 = SRR1
1633 comb
+= e_out
.write_fast2
.data
.eq(FastRegsEnum
.SRR1
) # SRR1
1634 comb
+= e_out
.write_fast2
.ok
.eq(1)
1635 # TRAP write fast2 = SRR1
1636 comb
+= e_out
.write_fast3
.data
.eq(FastRegsEnum
.SVSRR0
) # SVSRR0
1637 comb
+= e_out
.write_fast3
.ok
.eq(1)
1639 # RFID: needs to read SRR0/1
1640 with m
.If(do_out
.insn_type
== MicrOp
.OP_RFID
):
1641 # TRAP read fast1 = SRR0
1642 comb
+= e_out
.read_fast1
.data
.eq(FastRegsEnum
.SRR0
) # SRR0
1643 comb
+= e_out
.read_fast1
.ok
.eq(1)
1644 # TRAP read fast2 = SRR1
1645 comb
+= e_out
.read_fast2
.data
.eq(FastRegsEnum
.SRR1
) # SRR1
1646 comb
+= e_out
.read_fast2
.ok
.eq(1)
1647 # TRAP read fast2 = SVSRR0
1648 comb
+= e_out
.read_fast3
.data
.eq(FastRegsEnum
.SVSRR0
) # SVSRR0
1649 comb
+= e_out
.read_fast3
.ok
.eq(1)
1651 # annoying simulator bug.
1652 # asmcode may end up getting used for perfcounters?
1653 asmcode
= self
.op_get("asmcode")
1654 if hasattr(e_out
, "asmcode") and asmcode
is not None:
1655 comb
+= e_out
.asmcode
.eq(asmcode
)
1659 def trap(self
, m
, traptype
, trapaddr
, ldst_exc
=None):
1660 """trap: this basically "rewrites" the decoded instruction as a trap
1664 comb
+= e
.eq(0) # reset eeeeeverything
1667 comb
+= self
.do_copy("insn", self
.dec
.opcode_in
, True)
1668 comb
+= self
.do_copy("insn_type", MicrOp
.OP_TRAP
, True)
1669 comb
+= self
.do_copy("fn_unit", Function
.TRAP
, True)
1670 comb
+= self
.do_copy("trapaddr", trapaddr
>> 4, True) # bottom 4 bits
1671 comb
+= self
.do_copy("traptype", traptype
, True) # request type
1672 comb
+= self
.do_copy("ldst_exc", ldst_exc
, True) # request type
1673 comb
+= self
.do_copy("msr", self
.state
.msr
,
1674 True) # copy of MSR "state"
1675 comb
+= self
.do_copy("cia", self
.state
.pc
, True) # copy of PC "state"
1676 comb
+= self
.do_copy("svstate", self
.state
.svstate
, True) # SVSTATE
1679 def get_rdflags(m
, e
, cu
):
1680 """returns a sequential list of the read "ok" flags for a given FU.
1681 this list is in order of the CompUnit input specs
1684 for idx
in range(cu
.n_src
):
1685 regfile
, regname
, _
= cu
.get_in_spec(idx
)
1686 decinfo
= regspec_decode_read(m
, e
, regfile
, regname
)
1687 rdl
.append(decinfo
.okflag
)
1692 if __name__
== '__main__':
1693 pdecode
= create_pdecode()
1694 dec2
= PowerDecode2(pdecode
, svp64_en
=True)
1695 vl
= rtlil
.convert(dec2
, ports
=dec2
.ports() + pdecode
.ports())
1696 with
open("dec2.il", "w") as f
: