1 """Power ISA Decoder second stage
3 based on Anton Blanchard microwatt decode2.vhdl
5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
6 over-riding the internal opcode when an exception is needed.
9 from nmigen
import Module
, Elaboratable
, Signal
, Mux
, Const
, Cat
, Repl
, Record
10 from nmigen
.cli
import rtlil
11 from nmutil
.util
import sel
13 from nmutil
.picker
import PriorityPicker
14 from nmutil
.iocontrol
import RecordObject
15 from nmutil
.extend
import exts
17 from openpower
.exceptions
import LDSTException
19 from openpower
.decoder
.power_svp64_prefix
import SVP64PrefixDecoder
20 from openpower
.decoder
.power_svp64_extra
import SVP64CRExtra
, SVP64RegExtra
21 from openpower
.decoder
.power_svp64_rm
import (SVP64RMModeDecode
,
22 sv_input_record_layout
,
24 from openpower
.sv
.svp64
import SVP64Rec
26 from openpower
.decoder
.power_regspec_map
import regspec_decode_read
27 from openpower
.decoder
.power_decoder
import (create_pdecode
,
28 create_pdecode_svp64_ldst
,
30 from openpower
.decoder
.power_enums
import (MicrOp
, CryIn
, Function
,
32 LdstLen
, In1Sel
, In2Sel
, In3Sel
,
33 OutSel
, SPRfull
, SPRreduced
,
34 RCOE
, SVP64LDSTmode
, LDSTMode
,
35 SVEXTRA
, SVEtype
, SVPtype
)
36 from openpower
.decoder
.decode2execute1
import (Decode2ToExecute1Type
, Data
,
39 from openpower
.consts
import (MSR
, SPEC
, EXTRA2
, EXTRA3
, SVP64P
, field
,
40 SPEC_SIZE
, SPECb
, SPEC_AUG_SIZE
, SVP64CROffs
,
41 FastRegsEnum
, XERRegsEnum
, TT
)
43 from openpower
.state
import CoreState
44 from openpower
.util
import (spr_to_fast
, spr_to_state
, log
)
47 def decode_spr_num(spr
):
48 return Cat(spr
[5:10], spr
[0:5])
51 def instr_is_priv(m
, op
, insn
):
52 """determines if the instruction is privileged or not
55 is_priv_insn
= Signal(reset_less
=True)
57 with m
.Case(MicrOp
.OP_ATTN
, MicrOp
.OP_MFMSR
, MicrOp
.OP_MTMSRD
,
58 MicrOp
.OP_MTMSR
, MicrOp
.OP_RFID
):
59 comb
+= is_priv_insn
.eq(1)
60 with m
.Case(MicrOp
.OP_TLBIE
):
61 comb
+= is_priv_insn
.eq(1)
62 with m
.Case(MicrOp
.OP_MFSPR
, MicrOp
.OP_MTSPR
):
63 with m
.If(insn
[20]): # field XFX.spr[-1] i think
64 comb
+= is_priv_insn
.eq(1)
68 class SPRMap(Elaboratable
):
69 """SPRMap: maps POWER9 SPR numbers to internal enum values, fast and slow
72 def __init__(self
, regreduce_en
):
73 self
.regreduce_en
= regreduce_en
79 self
.spr_i
= Signal(10, reset_less
=True)
80 self
.spr_o
= Data(SPR
, name
="spr_o")
81 self
.fast_o
= Data(4, name
="fast_o")
82 self
.state_o
= Data(3, name
="state_o")
84 def elaborate(self
, platform
):
90 with m
.Switch(self
.spr_i
):
91 for i
, x
in enumerate(SPR
):
93 m
.d
.comb
+= self
.spr_o
.data
.eq(i
)
94 m
.d
.comb
+= self
.spr_o
.ok
.eq(1)
95 for x
, v
in spr_to_fast
.items():
97 m
.d
.comb
+= self
.fast_o
.data
.eq(v
)
98 m
.d
.comb
+= self
.fast_o
.ok
.eq(1)
99 for x
, v
in spr_to_state
.items():
100 with m
.Case(x
.value
):
101 m
.d
.comb
+= self
.state_o
.data
.eq(v
)
102 m
.d
.comb
+= self
.state_o
.ok
.eq(1)
106 class DecodeA(Elaboratable
):
107 """DecodeA from instruction
109 decodes register RA, implicit and explicit CSRs
112 def __init__(self
, dec
, op
, regreduce_en
):
113 self
.regreduce_en
= regreduce_en
114 if self
.regreduce_en
:
120 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
121 self
.insn_in
= Signal(32, reset_less
=True)
122 self
.reg_out
= Data(5, name
="reg_a")
123 self
.spr_out
= Data(SPR
, "spr_a")
124 self
.fast_out
= Data(4, "fast_a")
125 self
.state_out
= Data(3, "state_a")
126 self
.sv_nz
= Signal(1)
128 def elaborate(self
, platform
):
133 m
.submodules
.sprmap
= sprmap
= SPRMap(self
.regreduce_en
)
135 # select Register A field, if *full 7 bits* are zero (2 more from SVP64)
136 ra
= Signal(5, reset_less
=True)
137 comb
+= ra
.eq(self
.dec
.RA
)
138 with m
.If((self
.sel_in
== In1Sel
.RA
) |
139 ((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
140 ((ra
!= Const(0, 5)) |
(self
.sv_nz
!= Const(0, 1))))):
141 comb
+= reg
.data
.eq(ra
)
144 # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
145 # moved it to 1st position (in1_sel)... because
146 rs
= Signal(5, reset_less
=True)
147 comb
+= rs
.eq(self
.dec
.RS
)
148 with m
.If(self
.sel_in
== In1Sel
.RS
):
149 comb
+= reg
.data
.eq(rs
)
152 # select Register FRA field,
153 fra
= Signal(5, reset_less
=True)
154 comb
+= fra
.eq(self
.dec
.FRA
)
155 with m
.If(self
.sel_in
== In1Sel
.FRA
):
156 comb
+= reg
.data
.eq(fra
)
159 # select Register FRS field,
160 frs
= Signal(5, reset_less
=True)
161 comb
+= frs
.eq(self
.dec
.FRS
)
162 with m
.If(self
.sel_in
== In1Sel
.FRS
):
163 comb
+= reg
.data
.eq(frs
)
166 # decode Fast-SPR based on instruction type
167 with m
.Switch(op
.internal_op
):
169 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
170 with m
.Case(MicrOp
.OP_BC
):
171 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
173 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.CTR
)
174 comb
+= self
.fast_out
.ok
.eq(1)
175 with m
.Case(MicrOp
.OP_BCREG
):
176 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
177 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
178 with m
.If(xo9
& ~xo5
):
180 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.CTR
)
181 comb
+= self
.fast_out
.ok
.eq(1)
183 # MFSPR move from SPRs
184 with m
.Case(MicrOp
.OP_MFSPR
):
185 spr
= Signal(10, reset_less
=True)
186 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
187 comb
+= sprmap
.spr_i
.eq(spr
)
188 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
189 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
190 comb
+= self
.state_out
.eq(sprmap
.state_o
)
195 class DecodeAImm(Elaboratable
):
196 """DecodeA immediate from instruction
198 decodes register RA, whether immediate-zero, implicit and
199 explicit CSRs. SVP64 mode requires 2 extra bits
202 def __init__(self
, dec
):
204 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
205 self
.immz_out
= Signal(reset_less
=True)
206 self
.sv_nz
= Signal(1) # EXTRA bits from SVP64
208 def elaborate(self
, platform
):
212 # zero immediate requested
213 ra
= Signal(5, reset_less
=True)
214 comb
+= ra
.eq(self
.dec
.RA
)
215 with m
.If((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
216 (ra
== Const(0, 5)) &
217 (self
.sv_nz
== Const(0, 1))):
218 comb
+= self
.immz_out
.eq(1)
223 class DecodeB(Elaboratable
):
224 """DecodeB from instruction
226 decodes register RB, different forms of immediate (signed, unsigned),
227 and implicit SPRs. register B is basically "lane 2" into the CompUnits.
228 by industry-standard convention, "lane 2" is where fully-decoded
229 immediates are muxed in.
232 def __init__(self
, dec
, op
):
235 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
236 self
.insn_in
= Signal(32, reset_less
=True)
237 self
.reg_out
= Data(7, "reg_b")
238 self
.reg_isvec
= Signal(1, name
="reg_b_isvec") # TODO: in reg_out
239 self
.fast_out
= Data(4, "fast_b")
241 def elaborate(self
, platform
):
247 # select Register B field
248 with m
.Switch(self
.sel_in
):
249 with m
.Case(In2Sel
.FRB
):
250 comb
+= reg
.data
.eq(self
.dec
.FRB
)
252 with m
.Case(In2Sel
.RB
):
253 comb
+= reg
.data
.eq(self
.dec
.RB
)
255 with m
.Case(In2Sel
.RS
):
256 # for M-Form shiftrot
257 comb
+= reg
.data
.eq(self
.dec
.RS
)
260 # decode SPR2 based on instruction type
261 # BCREG implicitly uses LR or TAR for 2nd reg
262 # CTR however is already in fast_spr1 *not* 2.
263 with m
.If(op
.internal_op
== MicrOp
.OP_BCREG
):
264 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
265 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
267 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.LR
)
268 comb
+= self
.fast_out
.ok
.eq(1)
270 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.TAR
)
271 comb
+= self
.fast_out
.ok
.eq(1)
276 class DecodeBImm(Elaboratable
):
277 """DecodeB immediate from instruction
280 def __init__(self
, dec
):
282 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
283 self
.imm_out
= Data(64, "imm_b")
285 def elaborate(self
, platform
):
289 # select Register B Immediate
290 with m
.Switch(self
.sel_in
):
291 with m
.Case(In2Sel
.CONST_UI
): # unsigned
292 comb
+= self
.imm_out
.data
.eq(self
.dec
.UI
)
293 comb
+= self
.imm_out
.ok
.eq(1)
294 with m
.Case(In2Sel
.CONST_SI
): # sign-extended 16-bit
295 si
= Signal(16, reset_less
=True)
296 comb
+= si
.eq(self
.dec
.SI
)
297 comb
+= self
.imm_out
.data
.eq(exts(si
, 16, 64))
298 comb
+= self
.imm_out
.ok
.eq(1)
299 with m
.Case(In2Sel
.CONST_SI_HI
): # sign-extended 16+16=32 bit
300 si_hi
= Signal(32, reset_less
=True)
301 comb
+= si_hi
.eq(self
.dec
.SI
<< 16)
302 comb
+= self
.imm_out
.data
.eq(exts(si_hi
, 32, 64))
303 comb
+= self
.imm_out
.ok
.eq(1)
304 with m
.Case(In2Sel
.CONST_UI_HI
): # unsigned
305 ui
= Signal(16, reset_less
=True)
306 comb
+= ui
.eq(self
.dec
.UI
)
307 comb
+= self
.imm_out
.data
.eq(ui
<< 16)
308 comb
+= self
.imm_out
.ok
.eq(1)
309 with m
.Case(In2Sel
.CONST_LI
): # sign-extend 24+2=26 bit
310 li
= Signal(26, reset_less
=True)
311 comb
+= li
.eq(self
.dec
.LI
<< 2)
312 comb
+= self
.imm_out
.data
.eq(exts(li
, 26, 64))
313 comb
+= self
.imm_out
.ok
.eq(1)
314 with m
.Case(In2Sel
.CONST_BD
): # sign-extend (14+2)=16 bit
315 bd
= Signal(16, reset_less
=True)
316 comb
+= bd
.eq(self
.dec
.BD
<< 2)
317 comb
+= self
.imm_out
.data
.eq(exts(bd
, 16, 64))
318 comb
+= self
.imm_out
.ok
.eq(1)
319 with m
.Case(In2Sel
.CONST_DS
): # sign-extended (14+2=16) bit
320 ds
= Signal(16, reset_less
=True)
321 comb
+= ds
.eq(self
.dec
.DS
<< 2)
322 comb
+= self
.imm_out
.data
.eq(exts(ds
, 16, 64))
323 comb
+= self
.imm_out
.ok
.eq(1)
324 with m
.Case(In2Sel
.CONST_M1
): # signed (-1)
325 comb
+= self
.imm_out
.data
.eq(~
Const(0, 64)) # all 1s
326 comb
+= self
.imm_out
.ok
.eq(1)
327 with m
.Case(In2Sel
.CONST_SH
): # unsigned - for shift
328 comb
+= self
.imm_out
.data
.eq(self
.dec
.sh
)
329 comb
+= self
.imm_out
.ok
.eq(1)
330 with m
.Case(In2Sel
.CONST_SH32
): # unsigned - for shift
331 comb
+= self
.imm_out
.data
.eq(self
.dec
.SH32
)
332 comb
+= self
.imm_out
.ok
.eq(1)
333 with m
.Case(In2Sel
.CONST_XBI
): # unsigned - for grevi
334 comb
+= self
.imm_out
.data
.eq(self
.dec
.FormXB
.XBI
)
335 comb
+= self
.imm_out
.ok
.eq(1)
340 class DecodeC(Elaboratable
):
341 """DecodeC from instruction
343 decodes register RC. this is "lane 3" into some CompUnits (not many)
346 def __init__(self
, dec
, op
):
349 self
.sel_in
= Signal(In3Sel
, reset_less
=True)
350 self
.insn_in
= Signal(32, reset_less
=True)
351 self
.reg_out
= Data(5, "reg_c")
353 def elaborate(self
, platform
):
359 # select Register C field
360 with m
.Switch(self
.sel_in
):
361 with m
.Case(In3Sel
.RB
):
362 # for M-Form shiftrot
363 comb
+= reg
.data
.eq(self
.dec
.RB
)
365 with m
.Case(In3Sel
.FRS
):
366 comb
+= reg
.data
.eq(self
.dec
.FRS
)
368 with m
.Case(In3Sel
.FRC
):
369 comb
+= reg
.data
.eq(self
.dec
.FRC
)
371 with m
.Case(In3Sel
.RS
):
372 comb
+= reg
.data
.eq(self
.dec
.RS
)
374 with m
.Case(In3Sel
.RC
):
375 comb
+= reg
.data
.eq(self
.dec
.RC
)
377 with m
.Case(In3Sel
.RT
):
378 # for TLI-form ternlogi
379 comb
+= reg
.data
.eq(self
.dec
.RT
)
385 class DecodeOut(Elaboratable
):
386 """DecodeOut from instruction
388 decodes output register RA, RT, FRS, FRT, or SPR
391 def __init__(self
, dec
, op
, regreduce_en
):
392 self
.regreduce_en
= regreduce_en
393 if self
.regreduce_en
:
399 self
.sel_in
= Signal(OutSel
, reset_less
=True)
400 self
.insn_in
= Signal(32, reset_less
=True)
401 self
.reg_out
= Data(5, "reg_o")
402 self
.spr_out
= Data(SPR
, "spr_o")
403 self
.fast_out
= Data(4, "fast_o")
404 self
.state_out
= Data(3, "state_o")
406 def elaborate(self
, platform
):
409 m
.submodules
.sprmap
= sprmap
= SPRMap(self
.regreduce_en
)
413 # select Register out field
414 with m
.Switch(self
.sel_in
):
415 with m
.Case(OutSel
.FRS
):
416 comb
+= reg
.data
.eq(self
.dec
.FRS
)
418 with m
.Case(OutSel
.FRT
):
419 comb
+= reg
.data
.eq(self
.dec
.FRT
)
421 with m
.Case(OutSel
.RT
):
422 comb
+= reg
.data
.eq(self
.dec
.RT
)
424 with m
.Case(OutSel
.RA
):
425 comb
+= reg
.data
.eq(self
.dec
.RA
)
427 with m
.Case(OutSel
.SPR
):
428 spr
= Signal(10, reset_less
=True)
429 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
430 # MFSPR move to SPRs - needs mapping
431 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
432 comb
+= sprmap
.spr_i
.eq(spr
)
433 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
434 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
435 comb
+= self
.state_out
.eq(sprmap
.state_o
)
438 with m
.Switch(op
.internal_op
):
440 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
441 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_BCREG
):
442 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
444 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.CTR
)
445 comb
+= self
.fast_out
.ok
.eq(1)
447 # RFID 1st spr (fast)
448 with m
.Case(MicrOp
.OP_RFID
):
449 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.SRR0
) # SRR0
450 comb
+= self
.fast_out
.ok
.eq(1)
455 class DecodeOut2(Elaboratable
):
456 """DecodeOut2 from instruction
458 decodes output registers (2nd one). note that RA is *implicit* below,
459 which now causes problems with SVP64
461 TODO: SVP64 is a little more complex, here. svp64 allows extending
462 by one more destination by having one more EXTRA field. RA-as-src
463 is not the same as RA-as-dest. limited in that it's the same first
464 5 bits (from the v3.0B opcode), but still kinda cool. mostly used
465 for operations that have src-as-dest: mostly this is LD/ST-with-update
466 but there are others.
469 def __init__(self
, dec
, op
):
472 self
.sel_in
= Signal(OutSel
, reset_less
=True)
473 self
.implicit_rs
= Signal(reset_less
=True) # SVP64 implicit RS/FRS
474 self
.implicit_from_rc
= Signal(reset_less
=True)# implicit RS from RC
475 self
.lk
= Signal(reset_less
=True)
476 self
.insn_in
= Signal(32, reset_less
=True)
477 self
.reg_out
= Data(5, "reg_o2")
478 self
.rs_en
= Signal(reset_less
=True) # FFT instruction detected
479 self
.fast_out
= Data(4, "fast_o2")
480 self
.fast_out3
= Data(4, "fast_o3")
482 def elaborate(self
, platform
):
486 #m.submodules.svdec = svdec = SVP64RegExtra()
488 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
489 #reg = Signal(5, reset_less=True)
491 if hasattr(op
, "upd"):
492 # update mode LD/ST uses read-reg A also as an output
493 with m
.If(op
.upd
== LDSTMode
.update
):
494 comb
+= self
.reg_out
.data
.eq(self
.dec
.RA
)
495 comb
+= self
.reg_out
.ok
.eq(1)
497 # B, BC or BCREG: potential implicit register (LR) output
498 # these give bl, bcl, bclrl, etc.
499 with m
.Switch(op
.internal_op
):
501 # BC* implicit register (LR)
502 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_B
, MicrOp
.OP_BCREG
):
503 with m
.If(self
.lk
): # "link" mode
504 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.LR
) # LR
505 comb
+= self
.fast_out
.ok
.eq(1)
507 # RFID 2nd and 3rd spr (fast)
508 with m
.Case(MicrOp
.OP_RFID
):
509 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.SRR1
) # SRR1
510 comb
+= self
.fast_out
.ok
.eq(1)
511 comb
+= self
.fast_out3
.data
.eq(FastRegsEnum
.SVSRR0
) # SVSRR0
512 comb
+= self
.fast_out3
.ok
.eq(1)
514 # SVP64 FFT mode, FP mul-add: 2nd output reg (FRS) same as FRT
515 # will be offset by VL in hardware
516 # with m.Case(MicrOp.OP_FP_MADD):
517 with m
.If(self
.implicit_rs
):
518 with m
.If(self
.implicit_from_rc
):
519 comb
+= self
.reg_out
.data
.eq(self
.dec
.FRC
) # same as RC
521 comb
+= self
.reg_out
.data
.eq(self
.dec
.FRT
) # same as RT
522 comb
+= self
.reg_out
.ok
.eq(1)
523 comb
+= self
.rs_en
.eq(1)
528 class DecodeRC(Elaboratable
):
529 """DecodeRc from instruction
531 decodes Record bit Rc
534 def __init__(self
, dec
):
536 self
.sel_in
= Signal(RCOE
, reset_less
=True)
537 self
.insn_in
= Signal(32, reset_less
=True)
538 self
.rc_out
= Data(1, "rc")
540 def elaborate(self
, platform
):
544 # select Record bit out field
545 with m
.Switch(self
.sel_in
):
546 with m
.Case(RCOE
.RC
, RCOE
.RC_ONLY
):
547 comb
+= self
.rc_out
.data
.eq(self
.dec
.Rc
)
548 comb
+= self
.rc_out
.ok
.eq(1)
549 with m
.Case(RCOE
.ONE
):
550 comb
+= self
.rc_out
.data
.eq(1)
551 comb
+= self
.rc_out
.ok
.eq(1)
552 with m
.Case(RCOE
.NONE
):
553 comb
+= self
.rc_out
.data
.eq(0)
554 comb
+= self
.rc_out
.ok
.eq(1)
559 class DecodeOE(Elaboratable
):
560 """DecodeOE from instruction
562 decodes OE field: uses RC decode detection which has now been
563 updated to separate out RC_ONLY. all cases RC_ONLY are *NOT*
564 listening to the OE field, here.
567 def __init__(self
, dec
, op
):
570 self
.sel_in
= Signal(RCOE
, reset_less
=True)
571 self
.insn_in
= Signal(32, reset_less
=True)
572 self
.oe_out
= Data(1, "oe")
574 def elaborate(self
, platform
):
578 with m
.Switch(self
.sel_in
):
579 with m
.Case(RCOE
.RC
):
580 comb
+= self
.oe_out
.data
.eq(self
.dec
.OE
)
581 comb
+= self
.oe_out
.ok
.eq(1)
584 comb
+= self
.oe_out
.data
.eq(0)
585 comb
+= self
.oe_out
.ok
.eq(0)
590 class DecodeCRIn(Elaboratable
):
591 """Decodes input CR from instruction
593 CR indices - insn fields - (not the data *in* the CR) require only 3
594 bits because they refer to CR0-CR7
597 def __init__(self
, dec
, op
):
600 self
.sel_in
= Signal(CRInSel
, reset_less
=True)
601 self
.insn_in
= Signal(32, reset_less
=True)
602 self
.cr_bitfield
= Data(3, "cr_bitfield")
603 self
.cr_bitfield_b
= Data(3, "cr_bitfield_b")
604 self
.cr_bitfield_o
= Data(3, "cr_bitfield_o")
605 self
.whole_reg
= Data(8, "cr_fxm")
606 self
.sv_override
= Signal(2, reset_less
=True) # do not do EXTRA spec
608 def elaborate(self
, platform
):
612 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
615 # zero-initialisation
616 comb
+= self
.cr_bitfield
.ok
.eq(0)
617 comb
+= self
.cr_bitfield_b
.ok
.eq(0)
618 comb
+= self
.cr_bitfield_o
.ok
.eq(0)
619 comb
+= self
.whole_reg
.ok
.eq(0)
620 comb
+= self
.sv_override
.eq(0)
622 # select the relevant CR bitfields
623 with m
.Switch(self
.sel_in
):
624 with m
.Case(CRInSel
.NONE
):
625 pass # No bitfield activated
626 with m
.Case(CRInSel
.CR0
):
627 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
628 comb
+= self
.cr_bitfield
.ok
.eq(1)
629 comb
+= self
.sv_override
.eq(1)
630 with m
.Case(CRInSel
.CR1
):
631 comb
+= self
.cr_bitfield
.data
.eq(1) # CR1 (MSB0 numbering)
632 comb
+= self
.cr_bitfield
.ok
.eq(1)
633 comb
+= self
.sv_override
.eq(2)
634 with m
.Case(CRInSel
.BI
):
635 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BI
[2:5])
636 comb
+= self
.cr_bitfield
.ok
.eq(1)
637 with m
.Case(CRInSel
.BFA
):
638 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BFA
)
639 comb
+= self
.cr_bitfield
.ok
.eq(1)
640 with m
.Case(CRInSel
.BA_BB
):
641 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BA
[2:5])
642 comb
+= self
.cr_bitfield
.ok
.eq(1)
643 comb
+= self
.cr_bitfield_b
.data
.eq(self
.dec
.BB
[2:5])
644 comb
+= self
.cr_bitfield_b
.ok
.eq(1)
645 comb
+= self
.cr_bitfield_o
.data
.eq(self
.dec
.BT
[2:5])
646 comb
+= self
.cr_bitfield_o
.ok
.eq(1)
647 with m
.Case(CRInSel
.BC
):
648 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BC
[2:5])
649 comb
+= self
.cr_bitfield
.ok
.eq(1)
650 with m
.Case(CRInSel
.WHOLE_REG
):
651 comb
+= self
.whole_reg
.ok
.eq(1)
652 move_one
= Signal(reset_less
=True)
653 comb
+= move_one
.eq(self
.insn_in
[20]) # MSB0 bit 11
654 with m
.If((op
.internal_op
== MicrOp
.OP_MFCR
) & move_one
):
655 # must one-hot the FXM field
656 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
657 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
659 # otherwise use all of it
660 comb
+= self
.whole_reg
.data
.eq(0xff)
665 class DecodeCROut(Elaboratable
):
666 """Decodes input CR from instruction
668 CR indices - insn fields - (not the data *in* the CR) require only 3
669 bits because they refer to CR0-CR7
672 def __init__(self
, dec
, op
):
675 self
.rc_in
= Signal(reset_less
=True)
676 self
.sel_in
= Signal(CROutSel
, reset_less
=True)
677 self
.insn_in
= Signal(32, reset_less
=True)
678 self
.cr_bitfield
= Data(3, "cr_bitfield")
679 self
.whole_reg
= Data(8, "cr_fxm")
680 self
.sv_override
= Signal(2, reset_less
=True) # do not do EXTRA spec
681 self
.cr_5bit
= Signal(reset_less
=True) # set True for 5-bit
682 self
.cr_2bit
= Signal(2, reset_less
=True) # get lowest 2 bits
684 def elaborate(self
, platform
):
688 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
691 comb
+= self
.cr_bitfield
.ok
.eq(0)
692 comb
+= self
.whole_reg
.ok
.eq(0)
693 comb
+= self
.sv_override
.eq(0)
694 comb
+= self
.cr_5bit
.eq(0)
696 # please note these MUST match (setting of cr_bitfield.ok) exactly
697 # with write_cr0 below in PowerDecoder2. the reason it's separated
698 # is to avoid having duplicate copies of DecodeCROut in multiple
699 # PowerDecoderSubsets. register decoding should be a one-off in
700 # PowerDecoder2. see https://bugs.libre-soc.org/show_bug.cgi?id=606
702 with m
.Switch(self
.sel_in
):
703 with m
.Case(CROutSel
.NONE
):
704 pass # No bitfield activated
705 with m
.Case(CROutSel
.CR0
):
706 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
707 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
708 comb
+= self
.sv_override
.eq(1)
709 with m
.Case(CROutSel
.CR1
):
710 comb
+= self
.cr_bitfield
.data
.eq(1) # CR1 (MSB0 numbering)
711 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
712 comb
+= self
.sv_override
.eq(2)
713 with m
.Case(CROutSel
.BF
):
714 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BF
)
715 comb
+= self
.cr_bitfield
.ok
.eq(1)
716 with m
.Case(CROutSel
.BT
):
717 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormXL
.BT
[2:5])
718 comb
+= self
.cr_bitfield
.ok
.eq(1)
719 comb
+= self
.cr_5bit
.eq(1)
720 comb
+= self
.cr_2bit
.eq(self
.dec
.FormXL
.BT
[0:2])
721 with m
.Case(CROutSel
.WHOLE_REG
):
722 comb
+= self
.whole_reg
.ok
.eq(1)
723 move_one
= Signal(reset_less
=True)
724 comb
+= move_one
.eq(self
.insn_in
[20])
725 with m
.If((op
.internal_op
== MicrOp
.OP_MTCRF
)):
727 # must one-hot the FXM field
728 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
729 with m
.If(ppick
.en_o
):
730 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
732 comb
+= self
.whole_reg
.data
.eq(0b00000001) # CR7
734 comb
+= self
.whole_reg
.data
.eq(self
.dec
.FXM
)
736 # otherwise use all of it
737 comb
+= self
.whole_reg
.data
.eq(0xff)
742 # dictionary of Input Record field names that, if they exist,
743 # will need a corresponding CSV Decoder file column (actually, PowerOp)
744 # to be decoded (this includes the single bit names)
745 record_names
= {'insn_type': 'internal_op',
746 'fn_unit': 'function_unit',
747 'SV_Ptype': 'SV_Ptype',
748 'SV_mode': 'SV_mode',
752 'imm_data': 'in2_sel',
753 'invert_in': 'inv_a',
754 'invert_out': 'inv_out',
757 'output_carry': 'cry_out',
758 'input_carry': 'cry_in',
759 'is_32bit': 'is_32b',
762 'data_len': 'ldst_len',
764 'byte_reverse': 'br',
765 'sign_extend': 'sgn_ext',
770 class PowerDecodeSubset(Elaboratable
):
771 """PowerDecodeSubset: dynamic subset decoder
773 only fields actually requested are copied over. hence, "subset" (duh).
776 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False, state
=None,
777 svp64_en
=True, regreduce_en
=False, fp_en
=False):
779 self
.svp64_en
= svp64_en
780 self
.regreduce_en
= regreduce_en
783 self
.is_svp64_mode
= Signal() # mark decoding as SVP64 Mode
784 self
.implicit_rs
= Signal() # implicit RS/FRS
785 self
.extend_rb_maxvl
= Signal() # jumps RB by an additional MAXVL
786 self
.extend_rc_maxvl
= Signal() # jumps RS by MAXVL from RC
787 self
.sv_rm
= SVP64Rec(name
="dec_svp64") # SVP64 RM field
788 self
.rm_dec
= SVP64RMModeDecode("svp64_rm_dec")
789 # set these to the predicate mask bits needed for the ALU
790 self
.pred_sm
= Signal() # TODO expand to SIMD mask width
791 self
.pred_dm
= Signal() # TODO expand to SIMD mask width
792 self
.sv_a_nz
= Signal(1)
795 self
.fn_name
= fn_name
797 opkls
= Decode2ToOperand
798 self
.do
= opkls(fn_name
)
800 col_subset
= self
.get_col_subset(self
.do
)
801 row_subset
= self
.rowsubsetfn
806 # "conditions" for Decoders, to enable some weird and wonderful
807 # alternatives. useful for PCR (Program Compatibility Register)
808 # amongst other things
811 # XXX NO 'SVP64FFT': self.use_svp64_fft,
816 # only needed for "main" PowerDecode2
818 self
.e
= Decode2ToExecute1Type(name
=self
.fn_name
, do
=self
.do
,
819 regreduce_en
=regreduce_en
)
821 # create decoder if one not already given
823 dec
= create_pdecode(name
=fn_name
, col_subset
=col_subset
,
824 row_subset
=row_subset
,
825 conditions
=conditions
, include_fp
=fp_en
)
828 # set up a copy of the PowerOp
829 self
.op
= PowerOp
.like(self
.dec
.op
)
831 # state information needed by the Decoder
833 state
= CoreState("dec2")
836 def get_col_subset(self
, do
):
837 subset
= {'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
838 for k
, v
in record_names
.items():
841 log("get_col_subset", self
.fn_name
, do
.fields
, subset
)
844 def rowsubsetfn(self
, opcode
, row
):
845 """select per-Function-Unit subset of opcodes to be processed
847 normally this just looks at the "unit" column. MMU is different
848 in that it processes specific SPR set/get operations that the SPR
851 return (row
['unit'] == self
.fn_name
or
852 # sigh a dreadful hack: MTSPR and MFSPR need to be processed
853 # by the MMU pipeline so we direct those opcodes to MMU **AND**
854 # SPR pipelines, then selectively weed out the SPRs that should
855 # or should not not go to each pipeline, further down.
856 # really this should be done by modifying the CSV syntax
857 # to support multiple tasks (unit column multiple entries)
858 # see https://bugs.libre-soc.org/show_bug.cgi?id=310
859 (self
.fn_name
== 'MMU' and row
['unit'] == 'SPR' and
860 row
['internal op'] in ['OP_MTSPR', 'OP_MFSPR']) or
861 # urrr... and the KAIVB SPR, which must also be redirected
862 # (to the TRAP pipeline)
863 # see https://bugs.libre-soc.org/show_bug.cgi?id=859
864 (self
.fn_name
== 'TRAP' and row
['unit'] == 'SPR' and
865 row
['internal op'] in ['OP_MTSPR', 'OP_MFSPR'])
869 ports
= self
.dec
.ports() + self
.e
.ports()
871 ports
+= self
.sv_rm
.ports()
872 ports
.append(self
.is_svp64_mode
)
873 ports
.append(self
.implicit_rs
)
876 def needs_field(self
, field
, op_field
):
881 return hasattr(do
, field
) and self
.op_get(op_field
) is not None
883 def do_get(self
, field
, final
=False):
884 if final
or self
.final
:
888 return getattr(do
, field
, None)
890 def do_copy(self
, field
, val
, final
=False):
891 df
= self
.do_get(field
, final
)
892 if df
is not None and val
is not None:
896 def op_get(self
, op_field
):
897 return getattr(self
.op
, op_field
, None)
899 def elaborate(self
, platform
):
900 if self
.regreduce_en
:
907 op
, do
= self
.dec
.op
, self
.do
908 msr
, cia
, svstate
= state
.msr
, state
.pc
, state
.svstate
909 # fill in for a normal instruction (not an exception)
910 # copy over if non-exception, non-privileged etc. is detected
912 if self
.fn_name
is None:
915 name
= self
.fn_name
+ "tmp"
916 self
.e_tmp
= Decode2ToExecute1Type(name
=name
, opkls
=self
.opkls
,
917 regreduce_en
=self
.regreduce_en
)
919 # set up submodule decoders
920 m
.submodules
.dec
= dec
= self
.dec
921 m
.submodules
.dec_rc
= self
.dec_rc
= dec_rc
= DecodeRC(self
.dec
)
922 m
.submodules
.dec_oe
= dec_oe
= DecodeOE(self
.dec
, op
)
925 # and SVP64 RM mode decoder
926 m
.submodules
.sv_rm_dec
= rm_dec
= self
.rm_dec
928 # copy op from decoder
929 comb
+= self
.op
.eq(self
.dec
.op
)
931 # copy instruction through...
932 for i
in [do
.insn
, dec_rc
.insn_in
, dec_oe
.insn_in
, ]:
933 comb
+= i
.eq(self
.dec
.opcode_in
)
935 # ...and subdecoders' input fields
936 comb
+= dec_rc
.sel_in
.eq(self
.op_get("rc_sel"))
937 comb
+= dec_oe
.sel_in
.eq(self
.op_get("rc_sel")) # XXX should be OE sel
940 comb
+= self
.do_copy("msr", msr
)
941 comb
+= self
.do_copy("cia", cia
)
942 comb
+= self
.do_copy("svstate", svstate
)
944 # set up instruction type
945 # no op: defaults to OP_ILLEGAL
946 internal_op
= self
.op_get("internal_op")
947 comb
+= self
.do_copy("insn_type", internal_op
)
949 # function unit for decoded instruction: requires minor redirect
951 fn
= self
.op_get("function_unit")
952 spr
= Signal(10, reset_less
=True)
953 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
955 # Microwatt doesn't implement the partition table
956 # instead has PRTBL register (SPR) to point to process table
957 # Kestrel has a KAIVB SPR to "rebase" exceptions. rebasing is normally
958 # done with Hypervisor Mode which is not implemented (yet)
960 is_mmu_spr
= Signal()
961 is_trap_spr
= Signal()
962 comb
+= is_spr_mv
.eq((internal_op
== MicrOp
.OP_MTSPR
) |
963 (internal_op
== MicrOp
.OP_MFSPR
))
964 comb
+= is_mmu_spr
.eq((spr
== SPR
.DSISR
.value
) |
965 (spr
== SPR
.DAR
.value
) |
966 (spr
== SPR
.PRTBL
.value
) |
967 (spr
== SPR
.PIDR
.value
))
968 comb
+= is_trap_spr
.eq((spr
== SPR
.KAIVB
.value
)
970 # MMU must receive MMU SPRs
971 with m
.If(is_spr_mv
& (fn
== Function
.SPR
) & is_mmu_spr
):
972 comb
+= self
.do_copy("fn_unit", Function
.MMU
)
973 comb
+= self
.do_copy("insn_type", internal_op
)
974 # TRAP must receive TRAP SPR KAIVB
975 with m
.If(is_spr_mv
& (fn
== Function
.SPR
) & is_trap_spr
):
976 comb
+= self
.do_copy("fn_unit", Function
.TRAP
)
977 comb
+= self
.do_copy("insn_type", internal_op
)
978 # SPR pipe must *not* receive MMU or TRAP SPRs
979 with m
.Elif(is_spr_mv
& ((fn
== Function
.MMU
) & ~is_mmu_spr
) &
980 ((fn
== Function
.TRAP
) & ~is_trap_spr
)):
981 comb
+= self
.do_copy("fn_unit", Function
.NONE
)
982 comb
+= self
.do_copy("insn_type", MicrOp
.OP_ILLEGAL
)
985 comb
+= self
.do_copy("fn_unit", fn
)
988 if self
.needs_field("zero_a", "in1_sel"):
989 m
.submodules
.dec_ai
= dec_ai
= DecodeAImm(self
.dec
)
990 comb
+= dec_ai
.sv_nz
.eq(self
.sv_a_nz
)
991 comb
+= dec_ai
.sel_in
.eq(self
.op_get("in1_sel"))
992 comb
+= self
.do_copy("zero_a", dec_ai
.immz_out
) # RA==0 detected
993 if self
.needs_field("imm_data", "in2_sel"):
994 m
.submodules
.dec_bi
= dec_bi
= DecodeBImm(self
.dec
)
995 comb
+= dec_bi
.sel_in
.eq(self
.op_get("in2_sel"))
996 comb
+= self
.do_copy("imm_data", dec_bi
.imm_out
) # imm in RB
998 # CR in/out - note: these MUST match with what happens in
1000 rc_out
= self
.dec_rc
.rc_out
.data
1001 with m
.Switch(self
.op_get("cr_out")):
1002 with m
.Case(CROutSel
.CR0
, CROutSel
.CR1
):
1003 comb
+= self
.do_copy("write_cr0", rc_out
) # only when RC=1
1004 with m
.Case(CROutSel
.BF
, CROutSel
.BT
):
1005 comb
+= self
.do_copy("write_cr0", 1)
1007 comb
+= self
.do_copy("input_cr", self
.op_get("cr_in")) # CR in
1008 comb
+= self
.do_copy("output_cr", self
.op_get("cr_out")) # CR out
1011 # connect up SVP64 RM Mode decoding. however... we need a shorter
1012 # path, for the LDST bit-reverse detection. so perform partial
1013 # decode when SVP64 is detected. then, bit-reverse mode can be
1014 # quickly determined, and the Decoder result MUXed over to
1015 # the alternative decoder, svdecldst. what a mess... *sigh*
1016 sv_ptype
= self
.op_get("SV_Ptype")
1017 sv_mode
= self
.op_get("SV_mode")
1018 fn
= self
.op_get("function_unit")
1019 print ("sv_mode n", sv_mode
)
1020 comb
+= rm_dec
.sv_mode
.eq(sv_mode
) # BRANCH/CROP/LDST_IMM etc.
1021 comb
+= rm_dec
.fn_in
.eq(fn
) # decode needs to know Fn type
1022 comb
+= rm_dec
.ptype_in
.eq(sv_ptype
) # Single/Twin predicated
1023 comb
+= rm_dec
.rc_in
.eq(rc_out
) # Rc=1
1024 comb
+= rm_dec
.rm_in
.eq(self
.sv_rm
) # SVP64 RM mode
1025 if self
.needs_field("imm_data", "in2_sel"):
1026 bzero
= dec_bi
.imm_out
.ok
& ~dec_bi
.imm_out
.data
.bool()
1027 comb
+= rm_dec
.ldst_imz_in
.eq(bzero
) # B immediate is zero
1029 # main PowerDecoder2 determines if different SVP64 modes enabled
1030 # detect if SVP64 FFT mode enabled (really bad hack),
1031 # exclude fcfids and others
1032 # XXX this is a REALLY bad hack, REALLY has to be done better.
1033 # likely with a sub-decoder.
1034 # what this ultimately does is enable the 2nd implicit register
1035 # (FRS) for SVP64-decoding. all of these instructions are
1036 # 3-in 2-out but there is not enough room either in the
1037 # opcode *or* EXTRA2/3 to specify a 5th operand.
1039 comb
+= major
.eq(self
.dec
.opcode_in
[26:32])
1041 comb
+= xo
.eq(self
.dec
.opcode_in
[1:11])
1042 comb
+= self
.implicit_rs
.eq(0)
1043 comb
+= self
.extend_rb_maxvl
.eq(0)
1044 comb
+= self
.extend_rc_maxvl
.eq(0)
1045 with m
.If((major
== 59) & xo
.matches(
1046 '-----00100', # ffmsubs
1047 '-----00101', # ffmadds
1048 '-----00110', # ffnmsubs
1049 '-----00111', # ffnmadds
1050 '1111100000', # ffadds
1051 '-----11011', # fdmadds
1053 comb
+= self
.implicit_rs
.eq(1)
1054 comb
+= self
.extend_rb_maxvl
.eq(1) # extend RB
1056 comb
+= xo6
.eq(self
.dec
.opcode_in
[0:6])
1057 with m
.If((major
== 4) & xo6
.matches(
1060 '110100', # divmod2du
1062 comb
+= self
.implicit_rs
.eq(1)
1063 comb
+= self
.extend_rc_maxvl
.eq(1) # RS=RT+MAXVL or RS=RC
1066 comb
+= self
.do_copy("rc", dec_rc
.rc_out
)
1068 # OE only enabled when SVP64 not active
1069 with m
.If(~self
.is_svp64_mode
):
1070 comb
+= self
.do_copy("oe", dec_oe
.oe_out
)
1071 # RC1 overrides Rc if rc type is NONE or ONE or Rc=0, in svp64_mode
1072 # for instructions with a forced-Rc=1 (stbcx., pcdec.)
1073 # the RC1 RM bit *becomes* Rc=0/1, but for instructions
1074 # that have Rc=0/1 then when Rc=0 RC1 *becomes* (replaces) Rc.
1075 with m
.Elif((dec_rc
.sel_in
.matches(RCOE
.RC
, RCOE
.RC_ONLY
) &
1076 dec_rc
.rc_out
.data
== 0) |
1077 (dec_rc
.sel_in
== RCOE
.ONE
)):
1078 RC1
= Data(1, "RC1")
1079 comb
+= RC1
.ok
.eq(rm_dec
.RC1
)
1080 comb
+= RC1
.RC1
.eq(rm_dec
.RC1
)
1081 comb
+= self
.do_copy("rc", RC1
)
1083 comb
+= self
.do_copy("oe", dec_oe
.oe_out
)
1085 # decoded/selected instruction flags
1086 comb
+= self
.do_copy("data_len", self
.op_get("ldst_len"))
1087 comb
+= self
.do_copy("invert_in", self
.op_get("inv_a"))
1088 comb
+= self
.do_copy("invert_out", self
.op_get("inv_out"))
1089 comb
+= self
.do_copy("input_carry", self
.op_get("cry_in"))
1090 comb
+= self
.do_copy("output_carry", self
.op_get("cry_out"))
1091 comb
+= self
.do_copy("is_32bit", self
.op_get("is_32b"))
1092 comb
+= self
.do_copy("is_signed", self
.op_get("sgn"))
1093 lk
= self
.op_get("lk")
1096 comb
+= self
.do_copy("lk", self
.dec
.LK
) # XXX TODO: accessor
1098 comb
+= self
.do_copy("byte_reverse", self
.op_get("br"))
1099 comb
+= self
.do_copy("sign_extend", self
.op_get("sgn_ext"))
1100 comb
+= self
.do_copy("ldst_mode", self
.op_get("upd")) # LD/ST mode
1101 comb
+= self
.do_copy("reserve", self
.op_get("rsrv")) # atomic
1103 # copy over SVP64 input record fields (if they exist)
1105 # TODO, really do we have to do these explicitly?? sigh
1106 # for (field, _) in sv_input_record_layout:
1107 # comb += self.do_copy(field, self.rm_dec.op_get(field))
1108 comb
+= self
.do_copy("sv_saturate", self
.rm_dec
.saturate
)
1109 comb
+= self
.do_copy("sv_Ptype", self
.rm_dec
.ptype_in
)
1110 comb
+= self
.do_copy("sv_ldstmode", self
.rm_dec
.ldstmode
)
1111 # these get set up based on incoming mask bits. TODO:
1112 # pass in multiple bits (later, when SIMD backends are enabled)
1113 with m
.If(self
.rm_dec
.pred_sz
):
1114 comb
+= self
.do_copy("sv_pred_sz", ~self
.pred_sm
)
1115 with m
.If(self
.rm_dec
.pred_dz
):
1116 comb
+= self
.do_copy("sv_pred_dz", ~self
.pred_dm
)
1121 class PowerDecode2(PowerDecodeSubset
):
1122 """PowerDecode2: the main instruction decoder.
1124 whilst PowerDecode is responsible for decoding the actual opcode, this
1125 module encapsulates further specialist, sparse information and
1126 expansion of fields that is inconvenient to have in the CSV files.
1127 for example: the encoding of the immediates, which are detected
1128 and expanded out to their full value from an annotated (enum)
1131 implicit register usage is also set up, here. for example: OP_BC
1132 requires implicitly reading CTR, OP_RFID requires implicitly writing
1135 in addition, PowerDecoder2 is responsible for detecting whether
1136 instructions are illegal (or privileged) or not, and instead of
1137 just leaving at that, *replacing* the instruction to execute with
1138 a suitable alternative (trap).
1140 LDSTExceptions are done the cycle _after_ they're detected (after
1141 they come out of LDSTCompUnit). basically despite the instruction
1142 being decoded, the results of the decode are completely ignored
1143 and "exception.happened" used to set the "actual" instruction to
1144 "OP_TRAP". the LDSTException data structure gets filled in,
1145 in the CompTrapOpSubset and that's what it fills in SRR.
1147 to make this work, TestIssuer must notice "exception.happened"
1148 after the (failed) LD/ST and copies the LDSTException info from
1149 the output, into here (PowerDecoder2). without incrementing PC.
1151 also instr_fault works the same way: the instruction is "rewritten"
1152 so that the "fake" op that gets created is OP_FETCH_FAILED
1155 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False,
1156 state
=None, svp64_en
=True, regreduce_en
=False, fp_en
=False):
1157 super().__init
__(dec
, opkls
, fn_name
, final
, state
, svp64_en
,
1158 regreduce_en
=False, fp_en
=fp_en
)
1159 self
.ldst_exc
= LDSTException("dec2_exc") # rewrites as OP_TRAP
1160 self
.instr_fault
= Signal() # rewrites instruction as OP_FETCH_FAILED
1161 self
.crout_5bit
= Signal() # CR out is 5-bit
1164 self
.cr_out_isvec
= Signal(1, name
="cr_out_isvec")
1165 self
.cr_in_isvec
= Signal(1, name
="cr_in_isvec")
1166 self
.cr_in_b_isvec
= Signal(1, name
="cr_in_b_isvec")
1167 self
.cr_in_o_isvec
= Signal(1, name
="cr_in_o_isvec")
1168 self
.in1_isvec
= Signal(1, name
="reg_a_isvec")
1169 self
.in2_isvec
= Signal(1, name
="reg_b_isvec")
1170 self
.in3_isvec
= Signal(1, name
="reg_c_isvec")
1171 self
.o_isvec
= Signal(7, name
="reg_o_isvec")
1172 self
.o2_isvec
= Signal(7, name
="reg_o2_isvec")
1173 self
.in1_step
= Signal(7, name
="reg_a_step")
1174 self
.in2_step
= Signal(7, name
="reg_b_step")
1175 self
.in3_step
= Signal(7, name
="reg_c_step")
1176 self
.o_step
= Signal(7, name
="reg_o_step")
1177 self
.o2_step
= Signal(7, name
="reg_o2_step")
1178 self
.remap_active
= Signal(5, name
="remap_active") # per reg
1179 self
.no_in_vec
= Signal(1, name
="no_in_vec") # no inputs vector
1180 self
.no_out_vec
= Signal(1, name
="no_out_vec") # no outputs vector
1181 self
.loop_continue
= Signal(1, name
="loop_continue")
1183 self
.no_in_vec
= Const(1, 1)
1184 self
.no_out_vec
= Const(1, 1)
1185 self
.loop_continue
= Const(0, 1)
1187 def get_col_subset(self
, opkls
):
1188 subset
= super().get_col_subset(opkls
)
1189 subset
.add("asmcode")
1190 subset
.add("in1_sel")
1191 subset
.add("in2_sel")
1192 subset
.add("in3_sel")
1193 subset
.add("out_sel")
1195 subset
.add("sv_in1")
1196 subset
.add("sv_in2")
1197 subset
.add("sv_in3")
1198 subset
.add("sv_out")
1199 subset
.add("sv_out2")
1200 subset
.add("sv_cr_in")
1201 subset
.add("sv_cr_out")
1202 subset
.add("SV_Etype")
1203 subset
.add("SV_Ptype")
1204 subset
.add("SV_mode")
1205 # from SVP64RMModeDecode
1206 for (field
, _
) in sv_input_record_layout
:
1209 subset
.add("internal_op")
1213 def elaborate(self
, platform
):
1214 m
= super().elaborate(platform
)
1217 op
, e_out
, do_out
= self
.op
, self
.e
, self
.e
.do
1218 dec_spr
, msr
, cia
, ext_irq
= state
.dec
, state
.msr
, state
.pc
, state
.eint
1219 rc_out
= self
.dec_rc
.rc_out
.data
1223 # fill in for a normal instruction (not an exception)
1224 # copy over if non-exception, non-privileged etc. is detected
1226 # set up submodule decoders
1227 m
.submodules
.dec_a
= dec_a
= DecodeA(self
.dec
, op
, self
.regreduce_en
)
1228 m
.submodules
.dec_b
= dec_b
= DecodeB(self
.dec
, op
)
1229 m
.submodules
.dec_c
= dec_c
= DecodeC(self
.dec
, op
)
1230 m
.submodules
.dec_o
= dec_o
= DecodeOut(self
.dec
, op
, self
.regreduce_en
)
1231 m
.submodules
.dec_o2
= dec_o2
= DecodeOut2(self
.dec
, op
)
1232 m
.submodules
.dec_cr_in
= self
.dec_cr_in
= DecodeCRIn(self
.dec
, op
)
1233 m
.submodules
.dec_cr_out
= self
.dec_cr_out
= DecodeCROut(self
.dec
, op
)
1234 comb
+= dec_a
.sv_nz
.eq(self
.sv_a_nz
)
1235 comb
+= self
.crout_5bit
.eq(self
.dec_cr_out
.cr_5bit
)
1238 # and SVP64 Extra decoders
1239 m
.submodules
.crout_svdec
= crout_svdec
= SVP64CRExtra()
1240 m
.submodules
.crin_svdec
= crin_svdec
= SVP64CRExtra()
1241 m
.submodules
.crin_svdec_b
= crin_svdec_b
= SVP64CRExtra()
1242 m
.submodules
.crin_svdec_o
= crin_svdec_o
= SVP64CRExtra()
1243 m
.submodules
.in1_svdec
= in1_svdec
= SVP64RegExtra()
1244 m
.submodules
.in2_svdec
= in2_svdec
= SVP64RegExtra()
1245 m
.submodules
.in3_svdec
= in3_svdec
= SVP64RegExtra()
1246 m
.submodules
.o_svdec
= o_svdec
= SVP64RegExtra()
1247 m
.submodules
.o2_svdec
= o2_svdec
= SVP64RegExtra()
1249 # debug access to cr svdec (used in get_pdecode_cr_in/out)
1250 self
.crout_svdec
= crout_svdec
1251 self
.crin_svdec
= crin_svdec
1253 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
1254 reg
= Signal(5, reset_less
=True)
1256 # copy instruction through...
1257 for i
in [do
.insn
, dec_a
.insn_in
, dec_b
.insn_in
,
1258 self
.dec_cr_in
.insn_in
, self
.dec_cr_out
.insn_in
,
1259 dec_c
.insn_in
, dec_o
.insn_in
, dec_o2
.insn_in
]:
1260 comb
+= i
.eq(self
.dec
.opcode_in
)
1263 comb
+= self
.dec_cr_in
.sel_in
.eq(self
.op_get("cr_in"))
1264 comb
+= self
.dec_cr_out
.sel_in
.eq(self
.op_get("cr_out"))
1265 comb
+= self
.dec_cr_out
.rc_in
.eq(rc_out
)
1268 comb
+= self
.do_copy("read_cr_whole", self
.dec_cr_in
.whole_reg
)
1269 comb
+= self
.do_copy("write_cr_whole", self
.dec_cr_out
.whole_reg
)
1271 # ...and subdecoders' input fields
1272 comb
+= dec_a
.sel_in
.eq(self
.op_get("in1_sel"))
1273 comb
+= dec_b
.sel_in
.eq(self
.op_get("in2_sel"))
1274 comb
+= dec_c
.sel_in
.eq(self
.op_get("in3_sel"))
1275 comb
+= dec_o
.sel_in
.eq(self
.op_get("out_sel"))
1276 comb
+= dec_o2
.sel_in
.eq(self
.op_get("out_sel"))
1278 comb
+= dec_o2
.implicit_rs
.eq(self
.implicit_rs
)
1279 comb
+= dec_o2
.implicit_from_rc
.eq(self
.extend_rc_maxvl
)
1280 if hasattr(do
, "lk"):
1281 comb
+= dec_o2
.lk
.eq(do
.lk
)
1284 # now do the SVP64 munging. op.SV_Etype and op.sv_in1 comes from
1285 # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
1286 # which in turn were auto-generated by sv_analysis.py
1287 extra
= self
.sv_rm
.extra
# SVP64 extra bits 10:18
1292 comb
+= crout_svdec
.idx
.eq(self
.op_get("sv_cr_out"))
1293 comb
+= self
.cr_out_isvec
.eq(crout_svdec
.isvec
)
1296 # CR in - selection slightly different due to shared CR field sigh
1297 cr_a_idx
= Signal(SVEXTRA
)
1298 cr_b_idx
= Signal(SVEXTRA
)
1300 # these change slightly, when decoding BA/BB. really should have
1301 # their own separate CSV column: sv_cr_in1 and sv_cr_in2, but hey
1302 comb
+= cr_a_idx
.eq(self
.op_get("sv_cr_in"))
1303 comb
+= cr_b_idx
.eq(SVEXTRA
.NONE
)
1304 with m
.If(self
.op_get("sv_cr_in") == SVEXTRA
.Idx_1_2
.value
):
1305 comb
+= cr_a_idx
.eq(SVEXTRA
.Idx1
)
1306 comb
+= cr_b_idx
.eq(SVEXTRA
.Idx2
)
1308 comb
+= self
.cr_in_isvec
.eq(crin_svdec
.isvec
)
1309 comb
+= self
.cr_in_b_isvec
.eq(crin_svdec_b
.isvec
)
1310 comb
+= self
.cr_in_o_isvec
.eq(crin_svdec_o
.isvec
)
1312 # indices are slightly different, BA/BB mess sorted above
1313 comb
+= crin_svdec
.idx
.eq(cr_a_idx
) # SVP64 CR in A
1314 comb
+= crin_svdec_b
.idx
.eq(cr_b_idx
) # SVP64 CR in B
1316 comb
+= crin_svdec_o
.idx
.eq(self
.op_get("sv_cr_out"))
1318 # get SVSTATE srcstep (TODO: elwidth etc.) needed below
1319 vl
= Signal
.like(self
.state
.svstate
.vl
)
1320 maxvl
= Signal
.like(self
.state
.svstate
.maxvl
)
1321 subvl
= Signal
.like(self
.rm_dec
.rm_in
.subvl
)
1322 srcstep
= Signal
.like(self
.state
.svstate
.srcstep
)
1323 dststep
= Signal
.like(self
.state
.svstate
.dststep
)
1324 ssubstep
= Signal
.like(self
.state
.svstate
.ssubstep
)
1325 dsubstep
= Signal
.like(self
.state
.svstate
.ssubstep
)
1326 comb
+= vl
.eq(self
.state
.svstate
.vl
)
1327 comb
+= maxvl
.eq(self
.state
.svstate
.maxvl
)
1328 comb
+= subvl
.eq(self
.rm_dec
.rm_in
.subvl
)
1329 comb
+= srcstep
.eq(self
.state
.svstate
.srcstep
)
1330 comb
+= dststep
.eq(self
.state
.svstate
.dststep
)
1331 comb
+= ssubstep
.eq(self
.state
.svstate
.ssubstep
)
1332 comb
+= dsubstep
.eq(self
.state
.svstate
.dsubstep
)
1334 in1_step
, in2_step
= self
.in1_step
, self
.in2_step
1335 in3_step
= self
.in3_step
1336 o_step
, o2_step
= self
.o_step
, self
.o2_step
1338 # multiply vl by subvl - note that this is only 7 bit!
1339 # when elwidth overrides get involved this will have to go up
1341 comb
+= vmax
.eq(vl
*(subvl
+1))
1343 # registers a, b, c and out and out2 (LD/ST EA)
1344 sv_etype
= self
.op_get("SV_Etype")
1345 for i
, stuff
in enumerate((
1346 ("RA", e
.read_reg1
, dec_a
.reg_out
, in1_svdec
, in1_step
, False),
1347 ("RB", e
.read_reg2
, dec_b
.reg_out
, in2_svdec
, in2_step
, False),
1348 ("RC", e
.read_reg3
, dec_c
.reg_out
, in3_svdec
, in3_step
, False),
1349 ("RT", e
.write_reg
, dec_o
.reg_out
, o_svdec
, o_step
, True),
1350 ("EA", e
.write_ea
, dec_o2
.reg_out
, o2_svdec
, o2_step
, True))):
1351 rname
, to_reg
, fromreg
, svdec
, remapstep
, out
= stuff
1352 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1353 comb
+= svdec
.etype
.eq(sv_etype
) # EXTRA2/3 for this insn
1354 comb
+= svdec
.reg_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1355 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1356 # *screaam* FFT mode needs an extra offset for RB
1357 # similar to FRS/FRT (below). all of this needs cleanup
1358 offs
= Signal(7, name
="offs_"+rname
, reset_less
=True)
1361 # when FFT sv.ffmadd detected, and REMAP not in use,
1362 # automagically add on an extra offset to RB.
1363 # however when REMAP is active, the FFT REMAP
1364 # schedule takes care of this offset.
1365 with m
.If(dec_o2
.reg_out
.ok
& dec_o2
.rs_en
&
1366 self
.extend_rb_maxvl
):
1367 with m
.If(~self
.remap_active
[i
]):
1368 with m
.If(svdec
.isvec
):
1369 comb
+= offs
.eq(maxvl
) # MAXVL for Vectors
1370 # detect if Vectorised: add srcstep/dststep if yes.
1371 # to_reg is 7-bits, outs get dststep added, ins get srcstep
1372 with m
.If(svdec
.isvec
):
1373 selectstep
= dststep
if out
else srcstep
1374 subselect
= dsubstep
if out
else ssubstep
1375 step
= Signal(7, name
="step_%s" % rname
.lower())
1376 with m
.If(self
.remap_active
[i
]):
1377 comb
+= step
.eq((remapstep
*(subvl
+1))+subselect
)
1379 comb
+= step
.eq((selectstep
*(subvl
+1))+subselect
)
1380 # reverse gear goes the opposite way
1381 with m
.If(self
.rm_dec
.reverse_gear
):
1382 comb
+= to_reg
.offs
.eq(offs
+(vmax
-1-step
))
1384 comb
+= to_reg
.offs
.eq(offs
+step
)
1386 comb
+= to_reg
.offs
.eq(offs
)
1387 comb
+= to_reg
.base
.eq(svdec
.reg_out
)
1388 comb
+= to_reg
.data
.eq(to_reg
.base
+ to_reg
.offs
)
1390 # SVP64 in/out fields
1391 comb
+= in1_svdec
.idx
.eq(self
.op_get("sv_in1")) # reg #1 (in1_sel)
1392 comb
+= in2_svdec
.idx
.eq(self
.op_get("sv_in2")) # reg #2 (in2_sel)
1393 comb
+= in3_svdec
.idx
.eq(self
.op_get("sv_in3")) # reg #3 (in3_sel)
1394 comb
+= o_svdec
.idx
.eq(self
.op_get("sv_out")) # output (out_sel)
1396 comb
+= o2_svdec
.idx
.eq(self
.op_get("sv_out2"))
1397 # XXX TODO - work out where this should come from. the problem is
1398 # that LD-with-update is implied (computed from "is instruction in
1399 # "update mode" rather than specified cleanly as its own CSV column
1401 # output reg-is-vectorised (and when no in/out is vectorised)
1402 comb
+= self
.in1_isvec
.eq(in1_svdec
.isvec
)
1403 comb
+= self
.in2_isvec
.eq(in2_svdec
.isvec
)
1404 comb
+= self
.in3_isvec
.eq(in3_svdec
.isvec
)
1405 comb
+= self
.o_isvec
.eq(o_svdec
.isvec
)
1406 comb
+= self
.o2_isvec
.eq(o2_svdec
.isvec
)
1408 # urrr... don't ask... the implicit register FRS in FFT mode
1409 # "tracks" FRT exactly except it's offset by MAXVL. rather than
1410 # mess up the above with if-statements, override it here.
1411 # same trick is applied to FRB, above, but it's a lot cleaner there
1412 with m
.If(dec_o2
.reg_out
.ok
& dec_o2
.rs_en
):
1413 imp_reg_out
= Signal(7)
1414 imp_isvec
= Signal(1)
1415 with m
.If(self
.extend_rc_maxvl
): # maddedu etc. from RC
1416 comb
+= imp_isvec
.eq(in3_svdec
.isvec
)
1417 comb
+= imp_reg_out
.eq(in3_svdec
.reg_out
)
1419 comb
+= imp_isvec
.eq(o_svdec
.isvec
)
1420 comb
+= imp_reg_out
.eq(o_svdec
.reg_out
)
1422 with m
.If(~self
.remap_active
[4]):
1423 with m
.If(imp_isvec
):
1424 comb
+= offs
.eq(maxvl
) # MAXVL for Vectors
1425 with m
.Elif(self
.extend_rc_maxvl
): # maddedu etc. from RC
1426 comb
+= offs
.eq(0) # keep as RC
1428 comb
+= offs
.eq(1) # add 1 if scalar
1429 with m
.If(imp_isvec
):
1430 step
= Signal(7, name
="step_%s" % rname
.lower())
1431 with m
.If(self
.remap_active
[4]):
1432 with m
.If(self
.extend_rc_maxvl
): # maddedu etc. from RC
1433 comb
+= step
.eq(in3_step
)
1435 comb
+= step
.eq(o2_step
)
1437 comb
+= step
.eq(dststep
)
1438 # reverse gear goes the opposite way
1439 with m
.If(self
.rm_dec
.reverse_gear
):
1440 roffs
= offs
+(vl
-1-step
)
1441 comb
+= e
.write_ea
.data
.eq(roffs
)
1443 comb
+= e
.write_ea
.data
.eq(offs
+step
)
1445 comb
+= e
.write_ea
.offs
.eq(offs
)
1446 comb
+= e
.write_ea
.base
.eq(imp_reg_out
)
1447 comb
+= e
.write_ea
.data
.eq(e
.write_ea
.base
+ e
.write_ea
.offs
)
1448 # ... but write to *second* output
1449 comb
+= self
.o2_isvec
.eq(imp_isvec
)
1450 comb
+= o2_svdec
.idx
.eq(self
.op_get("sv_out"))
1452 # TODO add SPRs here. must be True when *all* are scalar
1453 l
= map(lambda svdec
: svdec
.isvec
, [in1_svdec
, in2_svdec
, in3_svdec
,
1454 crin_svdec
, crin_svdec_b
,
1456 comb
+= self
.no_in_vec
.eq(~
Cat(*l
).bool()) # all input scalar
1457 l
= map(lambda svdec
: svdec
.isvec
, [
1458 o2_svdec
, o_svdec
, crout_svdec
])
1459 # in mapreduce mode, scalar out is *allowed*
1460 with m
.If(self
.rm_dec
.mode
== SVP64RMMode
.MAPREDUCE
.value
):
1461 comb
+= self
.no_out_vec
.eq(0)
1464 comb
+= self
.no_out_vec
.eq(~
Cat(*l
).bool())
1465 # now create a general-purpose "test" as to whether looping
1466 # should continue. this doesn't include predication bit-tests
1467 loop
= self
.loop_continue
1468 with m
.Switch(self
.op_get("SV_Ptype")):
1469 with m
.Case(SVPtype
.P2
.value
):
1471 # TODO: *and cache-inhibited LD/ST!*
1472 comb
+= loop
.eq(~
(self
.no_in_vec | self
.no_out_vec
))
1473 with m
.Case(SVPtype
.P1
.value
):
1474 # single-predication, test relies on dest only
1475 comb
+= loop
.eq(~self
.no_out_vec
)
1477 # not an SV operation, no looping
1480 # condition registers (CR)
1481 for to_reg
, cr
, name
, svdec
, out
in (
1482 (e
.read_cr1
, self
.dec_cr_in
, "cr_bitfield", crin_svdec
, 0),
1483 (e
.read_cr2
, self
.dec_cr_in
, "cr_bitfield_b", crin_svdec_b
, 0),
1484 (e
.read_cr3
, self
.dec_cr_in
, "cr_bitfield_o", crin_svdec_o
, 0),
1485 (e
.write_cr
, self
.dec_cr_out
, "cr_bitfield", crout_svdec
, 1)):
1486 fromreg
= getattr(cr
, name
)
1487 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1488 comb
+= svdec
.etype
.eq(sv_etype
) # EXTRA2/3 for this insn
1489 comb
+= svdec
.cr_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1490 with m
.If(svdec
.isvec
):
1491 # check if this is CR0 or CR1: treated differently
1492 # (does not "listen" to EXTRA2/3 spec for a start)
1493 # also: the CRs start from completely different locations
1494 step
= dststep
if out
else srcstep
1495 with m
.If(cr
.sv_override
== 1): # CR0
1496 offs
= SVP64CROffs
.CR0
1497 comb
+= to_reg
.data
.eq(step
+offs
)
1498 with m
.Elif(cr
.sv_override
== 2): # CR1
1499 offs
= SVP64CROffs
.CR1
1500 comb
+= to_reg
.data
.eq(step
+1)
1502 comb
+= to_reg
.data
.eq(step
+svdec
.cr_out
) # 7-bit out
1504 comb
+= to_reg
.data
.eq(svdec
.cr_out
) # 7-bit output
1505 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1507 # sigh must determine if RA is nonzero (7 bit)
1508 comb
+= self
.sv_a_nz
.eq(e
.read_reg1
.data
!= Const(0, 7))
1510 # connect up to/from read/write GPRs
1511 for to_reg
, fromreg
in ((e
.read_reg1
, dec_a
.reg_out
),
1512 (e
.read_reg2
, dec_b
.reg_out
),
1513 (e
.read_reg3
, dec_c
.reg_out
),
1514 (e
.write_reg
, dec_o
.reg_out
),
1515 (e
.write_ea
, dec_o2
.reg_out
)):
1516 comb
+= to_reg
.data
.eq(fromreg
.data
)
1517 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1519 # connect up to/from read/write CRs
1520 for to_reg
, cr
, name
in (
1521 (e
.read_cr1
, self
.dec_cr_in
, "cr_bitfield", ),
1522 (e
.read_cr2
, self
.dec_cr_in
, "cr_bitfield_b", ),
1523 (e
.read_cr3
, self
.dec_cr_in
, "cr_bitfield_o", ),
1524 (e
.write_cr
, self
.dec_cr_out
, "cr_bitfield", )):
1525 fromreg
= getattr(cr
, name
)
1526 comb
+= to_reg
.data
.eq(fromreg
.data
)
1527 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1530 comb
+= self
.rm_dec
.ldst_ra_vec
.eq(self
.in1_isvec
) # RA is vector
1531 comb
+= self
.rm_dec
.cr_5bit_in
.eq(self
.crout_5bit
) # CR is 5-bit
1532 # take bottom 2 bits of CR out (CR field selector)
1533 with m
.If(self
.crout_5bit
):
1534 comb
+= self
.rm_dec
.cr_2bit_in
.eq(self
.dec_cr_out
.cr_2bit
)
1537 comb
+= e
.read_spr1
.eq(dec_a
.spr_out
)
1538 comb
+= e
.write_spr
.eq(dec_o
.spr_out
)
1540 # Fast regs out including SRR0/1/SVSRR0
1541 comb
+= e
.read_fast1
.eq(dec_a
.fast_out
)
1542 comb
+= e
.read_fast2
.eq(dec_b
.fast_out
)
1543 comb
+= e
.write_fast1
.eq(dec_o
.fast_out
) # SRR0 (OP_RFID)
1544 comb
+= e
.write_fast2
.eq(dec_o2
.fast_out
) # SRR1 (ditto)
1545 comb
+= e
.write_fast3
.eq(dec_o2
.fast_out3
) # SVSRR0 (ditto)
1546 # and State regs (DEC, TB)
1547 comb
+= e
.read_state1
.eq(dec_a
.state_out
) # DEC/TB
1548 comb
+= e
.write_state1
.eq(dec_o
.state_out
) # DEC/TB
1550 # sigh this is exactly the sort of thing for which the
1551 # decoder is designed to not need. MTSPR, MFSPR and others need
1552 # access to the XER bits. however setting e.oe is not appropriate
1553 internal_op
= self
.op_get("internal_op")
1554 with m
.If(internal_op
== MicrOp
.OP_MFSPR
):
1555 comb
+= e
.xer_in
.eq(0b111) # SO, CA, OV
1556 with m
.If(internal_op
== MicrOp
.OP_CMP
):
1557 comb
+= e
.xer_in
.eq(1 << XERRegsEnum
.SO
) # SO
1558 with m
.If(internal_op
== MicrOp
.OP_MTSPR
):
1559 comb
+= e
.xer_out
.eq(1)
1561 # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
1562 with m
.If(op
.internal_op
== MicrOp
.OP_TRAP
):
1563 # *DO NOT* call self.trap here. that would reset absolutely
1564 # everything including destroying read of RA and RB.
1565 comb
+= self
.do_copy("trapaddr", 0x70) # strip first nibble
1567 ####################
1568 # ok so the instruction's been decoded, blah blah, however
1569 # now we need to determine if it's actually going to go ahead...
1570 # *or* if in fact it's a privileged operation, whether there's
1571 # an external interrupt, etc. etc. this is a simple priority
1572 # if-elif-elif sequence. decrement takes highest priority,
1573 # EINT next highest, privileged operation third.
1575 # check if instruction is privileged
1576 is_priv_insn
= instr_is_priv(m
, op
.internal_op
, e
.do
.insn
)
1578 # different IRQ conditions
1579 ext_irq_ok
= Signal()
1580 dec_irq_ok
= Signal()
1583 ldst_exc
= self
.ldst_exc
1585 comb
+= ext_irq_ok
.eq(ext_irq
& msr
[MSR
.EE
]) # v3.0B p944 (MSR.EE)
1586 comb
+= dec_irq_ok
.eq(dec_spr
[63] & msr
[MSR
.EE
]) # 6.5.11 p1076
1587 comb
+= priv_ok
.eq(is_priv_insn
& msr
[MSR
.PR
])
1588 comb
+= illeg_ok
.eq(op
.internal_op
== MicrOp
.OP_ILLEGAL
)
1590 # absolute top priority: check for an instruction failed
1591 with m
.If(self
.instr_fault
):
1592 comb
+= self
.e
.eq(0) # reset eeeeeverything
1593 comb
+= self
.do_copy("insn", self
.dec
.opcode_in
, True)
1594 comb
+= self
.do_copy("insn_type", MicrOp
.OP_FETCH_FAILED
, True)
1595 comb
+= self
.do_copy("fn_unit", Function
.MMU
, True)
1596 comb
+= self
.do_copy("cia", self
.state
.pc
, True) # PC
1597 comb
+= self
.do_copy("msr", self
.state
.msr
, True) # MSR
1598 # special override on internal_op, due to being a "fake" op
1599 comb
+= self
.dec
.op
.internal_op
.eq(MicrOp
.OP_FETCH_FAILED
)
1601 # LD/ST exceptions. TestIssuer copies the exception info at us
1602 # after a failed LD/ST.
1603 with m
.Elif(ldst_exc
.happened
):
1604 with m
.If(ldst_exc
.alignment
):
1605 self
.trap(m
, TT
.MEMEXC
, 0x600)
1606 with m
.Elif(ldst_exc
.instr_fault
):
1607 with m
.If(ldst_exc
.segment_fault
):
1608 self
.trap(m
, TT
.MEMEXC
, 0x480)
1610 # pass exception info to trap to create SRR1
1611 self
.trap(m
, TT
.MEMEXC
, 0x400, ldst_exc
)
1613 with m
.If(ldst_exc
.segment_fault
):
1614 self
.trap(m
, TT
.MEMEXC
, 0x380)
1616 self
.trap(m
, TT
.MEMEXC
, 0x300)
1618 # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
1619 with m
.Elif(dec_irq_ok
):
1620 self
.trap(m
, TT
.DEC
, 0x900) # v3.0B 6.5 p1065
1622 # external interrupt? only if MSR.EE set
1623 with m
.Elif(ext_irq_ok
):
1624 self
.trap(m
, TT
.EINT
, 0x500)
1626 # privileged instruction trap
1627 with m
.Elif(priv_ok
):
1628 self
.trap(m
, TT
.PRIV
, 0x700)
1630 # illegal instruction must redirect to trap. this is done by
1631 # *overwriting* the decoded instruction and starting again.
1632 # (note: the same goes for interrupts and for privileged operations,
1633 # just with different trapaddr and traptype)
1634 with m
.Elif(illeg_ok
):
1635 # illegal instruction trap
1636 self
.trap(m
, TT
.ILLEG
, 0x700)
1638 # no exception, just copy things to the output
1642 ####################
1643 # follow-up after trap/irq to set up SRR0/1
1645 # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
1646 # Note: OP_SC could actually be modified to just be a trap
1647 with m
.If((do_out
.insn_type
== MicrOp
.OP_TRAP
) |
1648 (do_out
.insn_type
== MicrOp
.OP_SC
)):
1649 # TRAP write fast1 = SRR0
1650 comb
+= e_out
.write_fast1
.data
.eq(FastRegsEnum
.SRR0
) # SRR0
1651 comb
+= e_out
.write_fast1
.ok
.eq(1)
1652 # TRAP write fast2 = SRR1
1653 comb
+= e_out
.write_fast2
.data
.eq(FastRegsEnum
.SRR1
) # SRR1
1654 comb
+= e_out
.write_fast2
.ok
.eq(1)
1655 # TRAP write fast2 = SRR1
1656 comb
+= e_out
.write_fast3
.data
.eq(FastRegsEnum
.SVSRR0
) # SVSRR0
1657 comb
+= e_out
.write_fast3
.ok
.eq(1)
1659 # RFID: needs to read SRR0/1
1660 with m
.If(do_out
.insn_type
== MicrOp
.OP_RFID
):
1661 # TRAP read fast1 = SRR0
1662 comb
+= e_out
.read_fast1
.data
.eq(FastRegsEnum
.SRR0
) # SRR0
1663 comb
+= e_out
.read_fast1
.ok
.eq(1)
1664 # TRAP read fast2 = SRR1
1665 comb
+= e_out
.read_fast2
.data
.eq(FastRegsEnum
.SRR1
) # SRR1
1666 comb
+= e_out
.read_fast2
.ok
.eq(1)
1667 # TRAP read fast2 = SVSRR0
1668 comb
+= e_out
.read_fast3
.data
.eq(FastRegsEnum
.SVSRR0
) # SVSRR0
1669 comb
+= e_out
.read_fast3
.ok
.eq(1)
1671 # annoying simulator bug.
1672 # asmcode may end up getting used for perfcounters?
1673 asmcode
= self
.op_get("asmcode")
1674 if hasattr(e_out
, "asmcode") and asmcode
is not None:
1675 comb
+= e_out
.asmcode
.eq(asmcode
)
1679 def trap(self
, m
, traptype
, trapaddr
, ldst_exc
=None):
1680 """trap: this basically "rewrites" the decoded instruction as a trap
1684 comb
+= e
.eq(0) # reset eeeeeverything
1687 comb
+= self
.do_copy("insn", self
.dec
.opcode_in
, True)
1688 comb
+= self
.do_copy("insn_type", MicrOp
.OP_TRAP
, True)
1689 comb
+= self
.do_copy("fn_unit", Function
.TRAP
, True)
1690 comb
+= self
.do_copy("trapaddr", trapaddr
>> 4, True) # bottom 4 bits
1691 comb
+= self
.do_copy("traptype", traptype
, True) # request type
1692 comb
+= self
.do_copy("ldst_exc", ldst_exc
, True) # request type
1693 comb
+= self
.do_copy("msr", self
.state
.msr
,
1694 True) # copy of MSR "state"
1695 comb
+= self
.do_copy("cia", self
.state
.pc
, True) # copy of PC "state"
1696 comb
+= self
.do_copy("svstate", self
.state
.svstate
, True) # SVSTATE
1699 def get_rdflags(m
, e
, cu
):
1700 """returns a sequential list of the read "ok" flags for a given FU.
1701 this list is in order of the CompUnit input specs
1704 for idx
in range(cu
.n_src
):
1705 regfile
, regname
, _
= cu
.get_in_spec(idx
)
1706 decinfo
= regspec_decode_read(m
, e
, regfile
, regname
)
1707 rdl
.append(decinfo
.okflag
)
1712 if __name__
== '__main__':
1713 pdecode
= create_pdecode()
1714 dec2
= PowerDecode2(pdecode
, svp64_en
=True)
1715 vl
= rtlil
.convert(dec2
, ports
=dec2
.ports() + pdecode
.ports())
1716 with
open("dec2.il", "w") as f
: