1 """Power ISA Decoder second stage
3 based on Anton Blanchard microwatt decode2.vhdl
5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
6 over-riding the internal opcode when an exception is needed.
9 from nmigen
import Module
, Elaboratable
, Signal
, Mux
, Const
, Cat
, Repl
, Record
10 from nmigen
.cli
import rtlil
11 from nmutil
.util
import sel
13 from nmutil
.picker
import PriorityPicker
14 from nmutil
.iocontrol
import RecordObject
15 from nmutil
.extend
import exts
17 from openpower
.exceptions
import LDSTException
19 from openpower
.decoder
.power_svp64_prefix
import SVP64PrefixDecoder
20 from openpower
.decoder
.power_svp64_extra
import SVP64CRExtra
, SVP64RegExtra
21 from openpower
.decoder
.power_svp64_rm
import (SVP64RMModeDecode
,
22 sv_input_record_layout
,
24 from openpower
.sv
.svp64
import SVP64Rec
26 from openpower
.decoder
.power_regspec_map
import regspec_decode_read
27 from openpower
.decoder
.power_decoder
import (create_pdecode
,
28 create_pdecode_svp64_ldst
,
30 from openpower
.decoder
.power_enums
import (MicrOp
, CryIn
, Function
,
32 LdstLen
, In1Sel
, In2Sel
, In3Sel
,
33 OutSel
, SPRfull
, SPRreduced
,
34 RCOE
, SVP64LDSTmode
, LDSTMode
,
35 SVEXTRA
, SVEType
, SVPType
)
36 from openpower
.decoder
.decode2execute1
import (Decode2ToExecute1Type
, Data
,
39 from openpower
.consts
import (MSR
, SPEC
, EXTRA2
, EXTRA3
, SVP64P
, field
,
40 SPEC_SIZE
, SPECb
, SPEC_AUG_SIZE
, SVP64CROffs
,
41 FastRegsEnum
, XERRegsEnum
, TT
)
43 from openpower
.state
import CoreState
44 from openpower
.util
import (spr_to_fast
, spr_to_state
, log
)
47 def decode_spr_num(spr
):
48 return Cat(spr
[5:10], spr
[0:5])
51 def instr_is_priv(m
, op
, insn
):
52 """determines if the instruction is privileged or not
55 is_priv_insn
= Signal(reset_less
=True)
57 with m
.Case(MicrOp
.OP_ATTN
, MicrOp
.OP_MFMSR
, MicrOp
.OP_MTMSRD
,
58 MicrOp
.OP_MTMSR
, MicrOp
.OP_RFID
):
59 comb
+= is_priv_insn
.eq(1)
60 with m
.Case(MicrOp
.OP_TLBIE
):
61 comb
+= is_priv_insn
.eq(1)
62 with m
.Case(MicrOp
.OP_MFSPR
, MicrOp
.OP_MTSPR
):
63 with m
.If(insn
[20]): # field XFX.spr[-1] i think
64 comb
+= is_priv_insn
.eq(1)
68 class SPRMap(Elaboratable
):
69 """SPRMap: maps POWER9 SPR numbers to internal enum values, fast and slow
72 def __init__(self
, regreduce_en
):
73 self
.regreduce_en
= regreduce_en
79 self
.spr_i
= Signal(10, reset_less
=True)
80 self
.spr_o
= Data(SPR
, name
="spr_o")
81 self
.fast_o
= Data(4, name
="fast_o")
82 self
.state_o
= Data(3, name
="state_o")
84 def elaborate(self
, platform
):
90 with m
.Switch(self
.spr_i
):
91 for i
, x
in enumerate(SPR
):
93 m
.d
.comb
+= self
.spr_o
.data
.eq(i
)
94 m
.d
.comb
+= self
.spr_o
.ok
.eq(1)
95 for x
, v
in spr_to_fast
.items():
97 m
.d
.comb
+= self
.fast_o
.data
.eq(v
)
98 m
.d
.comb
+= self
.fast_o
.ok
.eq(1)
99 for x
, v
in spr_to_state
.items():
100 with m
.Case(x
.value
):
101 m
.d
.comb
+= self
.state_o
.data
.eq(v
)
102 m
.d
.comb
+= self
.state_o
.ok
.eq(1)
106 class DecodeA(Elaboratable
):
107 """DecodeA from instruction
109 decodes register RA, implicit and explicit CSRs
112 def __init__(self
, dec
, op
, regreduce_en
):
113 self
.regreduce_en
= regreduce_en
114 if self
.regreduce_en
:
120 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
121 self
.insn_in
= Signal(32, reset_less
=True)
122 self
.reg_out
= Data(5, name
="reg_a")
123 self
.spr_out
= Data(SPR
, "spr_a")
124 self
.fast_out
= Data(4, "fast_a")
125 self
.state_out
= Data(3, "state_a")
126 self
.sv_nz
= Signal(1)
128 def elaborate(self
, platform
):
133 m
.submodules
.sprmap
= sprmap
= SPRMap(self
.regreduce_en
)
135 # select Register A field, if *full 7 bits* are zero (2 more from SVP64)
136 ra
= Signal(5, reset_less
=True)
137 comb
+= ra
.eq(self
.dec
.RA
)
138 with m
.If((self
.sel_in
== In1Sel
.RA
) |
139 ((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
140 ((ra
!= Const(0, 5)) |
(self
.sv_nz
!= Const(0, 1))))):
141 comb
+= reg
.data
.eq(ra
)
144 # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
145 # moved it to 1st position (in1_sel)... because
146 rs
= Signal(5, reset_less
=True)
147 comb
+= rs
.eq(self
.dec
.RS
)
148 with m
.If(self
.sel_in
== In1Sel
.RS
):
149 comb
+= reg
.data
.eq(rs
)
152 # select Register FRA field,
153 fra
= Signal(5, reset_less
=True)
154 comb
+= fra
.eq(self
.dec
.FRA
)
155 with m
.If(self
.sel_in
== In1Sel
.FRA
):
156 comb
+= reg
.data
.eq(fra
)
159 # select Register FRS field,
160 frs
= Signal(5, reset_less
=True)
161 comb
+= frs
.eq(self
.dec
.FRS
)
162 with m
.If(self
.sel_in
== In1Sel
.FRS
):
163 comb
+= reg
.data
.eq(frs
)
166 # select Register FRT field,
167 frt
= Signal(5, reset_less
=True)
168 comb
+= frt
.eq(self
.dec
.FRT
)
169 with m
.If(self
.sel_in
== In1Sel
.FRT
):
170 comb
+= reg
.data
.eq(frt
)
173 # decode Fast-SPR based on instruction type
174 with m
.Switch(op
.internal_op
):
176 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
177 with m
.Case(MicrOp
.OP_BC
):
178 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
180 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.CTR
)
181 comb
+= self
.fast_out
.ok
.eq(1)
182 with m
.Case(MicrOp
.OP_BCREG
):
183 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
184 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
185 with m
.If(xo9
& ~xo5
):
187 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.CTR
)
188 comb
+= self
.fast_out
.ok
.eq(1)
190 # MFSPR move from SPRs
191 with m
.Case(MicrOp
.OP_MFSPR
):
192 spr
= Signal(10, reset_less
=True)
193 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
194 comb
+= sprmap
.spr_i
.eq(spr
)
195 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
196 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
197 comb
+= self
.state_out
.eq(sprmap
.state_o
)
202 class DecodeAImm(Elaboratable
):
203 """DecodeA immediate from instruction
205 decodes register RA, whether immediate-zero, implicit and
206 explicit CSRs. SVP64 mode requires 2 extra bits
209 def __init__(self
, dec
):
211 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
212 self
.immz_out
= Signal(reset_less
=True)
213 self
.sv_nz
= Signal(1) # EXTRA bits from SVP64
215 def elaborate(self
, platform
):
219 # zero immediate requested
220 ra
= Signal(5, reset_less
=True)
221 comb
+= ra
.eq(self
.dec
.RA
)
222 with m
.If((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
223 (ra
== Const(0, 5)) &
224 (self
.sv_nz
== Const(0, 1))):
225 comb
+= self
.immz_out
.eq(1)
230 class DecodeB(Elaboratable
):
231 """DecodeB from instruction
233 decodes register RB, different forms of immediate (signed, unsigned),
234 and implicit SPRs. register B is basically "lane 2" into the CompUnits.
235 by industry-standard convention, "lane 2" is where fully-decoded
236 immediates are muxed in.
239 def __init__(self
, dec
, op
):
242 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
243 self
.insn_in
= Signal(32, reset_less
=True)
244 self
.reg_out
= Data(7, "reg_b")
245 self
.reg_isvec
= Signal(1, name
="reg_b_isvec") # TODO: in reg_out
246 self
.fast_out
= Data(4, "fast_b")
248 def elaborate(self
, platform
):
254 # select Register B field
255 with m
.Switch(self
.sel_in
):
256 with m
.Case(In2Sel
.FRB
):
257 comb
+= reg
.data
.eq(self
.dec
.FRB
)
259 with m
.Case(In2Sel
.RB
):
260 comb
+= reg
.data
.eq(self
.dec
.RB
)
262 with m
.Case(In2Sel
.RS
):
263 # for M-Form shiftrot
264 comb
+= reg
.data
.eq(self
.dec
.RS
)
267 # decode SPR2 based on instruction type
268 # BCREG implicitly uses LR or TAR for 2nd reg
269 # CTR however is already in fast_spr1 *not* 2.
270 with m
.If(op
.internal_op
== MicrOp
.OP_BCREG
):
271 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
272 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
274 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.LR
)
275 comb
+= self
.fast_out
.ok
.eq(1)
277 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.TAR
)
278 comb
+= self
.fast_out
.ok
.eq(1)
283 class DecodeBImm(Elaboratable
):
284 """DecodeB immediate from instruction
287 def __init__(self
, dec
):
289 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
290 self
.imm_out
= Data(64, "imm_b")
292 def elaborate(self
, platform
):
296 # select Register B Immediate
297 with m
.Switch(self
.sel_in
):
298 with m
.Case(In2Sel
.CONST_UI
): # unsigned
299 comb
+= self
.imm_out
.data
.eq(self
.dec
.UI
)
300 comb
+= self
.imm_out
.ok
.eq(1)
301 with m
.Case(In2Sel
.CONST_SI
): # sign-extended 16-bit
302 si
= Signal(16, reset_less
=True)
303 comb
+= si
.eq(self
.dec
.SI
)
304 comb
+= self
.imm_out
.data
.eq(exts(si
, 16, 64))
305 comb
+= self
.imm_out
.ok
.eq(1)
306 with m
.Case(In2Sel
.CONST_SI_HI
): # sign-extended 16+16=32 bit
307 si_hi
= Signal(32, reset_less
=True)
308 comb
+= si_hi
.eq(self
.dec
.SI
<< 16)
309 comb
+= self
.imm_out
.data
.eq(exts(si_hi
, 32, 64))
310 comb
+= self
.imm_out
.ok
.eq(1)
311 with m
.Case(In2Sel
.CONST_UI_HI
): # unsigned
312 ui
= Signal(16, reset_less
=True)
313 comb
+= ui
.eq(self
.dec
.UI
)
314 comb
+= self
.imm_out
.data
.eq(ui
<< 16)
315 comb
+= self
.imm_out
.ok
.eq(1)
316 with m
.Case(In2Sel
.CONST_LI
): # sign-extend 24+2=26 bit
317 li
= Signal(26, reset_less
=True)
318 comb
+= li
.eq(self
.dec
.LI
<< 2)
319 comb
+= self
.imm_out
.data
.eq(exts(li
, 26, 64))
320 comb
+= self
.imm_out
.ok
.eq(1)
321 with m
.Case(In2Sel
.CONST_BD
): # sign-extend (14+2)=16 bit
322 bd
= Signal(16, reset_less
=True)
323 comb
+= bd
.eq(self
.dec
.BD
<< 2)
324 comb
+= self
.imm_out
.data
.eq(exts(bd
, 16, 64))
325 comb
+= self
.imm_out
.ok
.eq(1)
326 with m
.Case(In2Sel
.CONST_DS
): # sign-extended (14+2=16) bit
327 ds
= Signal(16, reset_less
=True)
328 comb
+= ds
.eq(self
.dec
.DS
<< 2)
329 comb
+= self
.imm_out
.data
.eq(exts(ds
, 16, 64))
330 comb
+= self
.imm_out
.ok
.eq(1)
331 with m
.Case(In2Sel
.CONST_M1
): # signed (-1)
332 comb
+= self
.imm_out
.data
.eq(~
Const(0, 64)) # all 1s
333 comb
+= self
.imm_out
.ok
.eq(1)
334 with m
.Case(In2Sel
.CONST_SH
): # unsigned - for shift
335 comb
+= self
.imm_out
.data
.eq(self
.dec
.sh
)
336 comb
+= self
.imm_out
.ok
.eq(1)
337 with m
.Case(In2Sel
.CONST_SH32
): # unsigned - for shift
338 comb
+= self
.imm_out
.data
.eq(self
.dec
.SH32
)
339 comb
+= self
.imm_out
.ok
.eq(1)
344 class DecodeC(Elaboratable
):
345 """DecodeC from instruction
347 decodes register RC. this is "lane 3" into some CompUnits (not many)
350 def __init__(self
, dec
, op
):
353 self
.sel_in
= Signal(In3Sel
, reset_less
=True)
354 self
.insn_in
= Signal(32, reset_less
=True)
355 self
.reg_out
= Data(5, "reg_c")
357 def elaborate(self
, platform
):
363 # select Register C field
364 with m
.Switch(self
.sel_in
):
365 with m
.Case(In3Sel
.RB
):
366 # for M-Form shiftrot
367 comb
+= reg
.data
.eq(self
.dec
.RB
)
369 with m
.Case(In3Sel
.FRS
):
370 comb
+= reg
.data
.eq(self
.dec
.FRS
)
372 with m
.Case(In3Sel
.FRA
):
373 comb
+= reg
.data
.eq(self
.dec
.FRA
)
375 with m
.Case(In3Sel
.FRC
):
376 comb
+= reg
.data
.eq(self
.dec
.FRC
)
378 with m
.Case(In3Sel
.RS
):
379 comb
+= reg
.data
.eq(self
.dec
.RS
)
381 with m
.Case(In3Sel
.RC
):
382 comb
+= reg
.data
.eq(self
.dec
.RC
)
384 with m
.Case(In3Sel
.RT
):
385 # for TLI-form ternlogi
386 comb
+= reg
.data
.eq(self
.dec
.RT
)
392 class DecodeOut(Elaboratable
):
393 """DecodeOut from instruction
395 decodes output register RA, RT, FRS, FRT, or SPR
398 def __init__(self
, dec
, op
, regreduce_en
):
399 self
.regreduce_en
= regreduce_en
400 if self
.regreduce_en
:
406 self
.sel_in
= Signal(OutSel
, reset_less
=True)
407 self
.insn_in
= Signal(32, reset_less
=True)
408 self
.reg_out
= Data(5, "reg_o")
409 self
.spr_out
= Data(SPR
, "spr_o")
410 self
.fast_out
= Data(4, "fast_o")
411 self
.state_out
= Data(3, "state_o")
413 def elaborate(self
, platform
):
416 m
.submodules
.sprmap
= sprmap
= SPRMap(self
.regreduce_en
)
420 # select Register out field
421 with m
.Switch(self
.sel_in
):
422 with m
.Case(OutSel
.FRS
):
423 comb
+= reg
.data
.eq(self
.dec
.FRS
)
425 with m
.Case(OutSel
.FRA
):
426 comb
+= reg
.data
.eq(self
.dec
.FRA
)
428 with m
.Case(OutSel
.FRT
):
429 comb
+= reg
.data
.eq(self
.dec
.FRT
)
431 with m
.Case(OutSel
.RT
):
432 comb
+= reg
.data
.eq(self
.dec
.RT
)
434 with m
.Case(OutSel
.RA
):
435 comb
+= reg
.data
.eq(self
.dec
.RA
)
437 with m
.Case(OutSel
.SPR
):
438 spr
= Signal(10, reset_less
=True)
439 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
440 # MFSPR move to SPRs - needs mapping
441 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
442 comb
+= sprmap
.spr_i
.eq(spr
)
443 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
444 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
445 comb
+= self
.state_out
.eq(sprmap
.state_o
)
448 with m
.Switch(op
.internal_op
):
450 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
451 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_BCREG
):
452 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
454 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.CTR
)
455 comb
+= self
.fast_out
.ok
.eq(1)
457 # RFID 1st spr (fast)
458 with m
.Case(MicrOp
.OP_RFID
):
459 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.SRR0
) # SRR0
460 comb
+= self
.fast_out
.ok
.eq(1)
465 class DecodeOut2(Elaboratable
):
466 """DecodeOut2 from instruction
468 decodes output registers (2nd one). note that RA is *implicit* below,
469 which now causes problems with SVP64
471 TODO: SVP64 is a little more complex, here. svp64 allows extending
472 by one more destination by having one more EXTRA field. RA-as-src
473 is not the same as RA-as-dest. limited in that it's the same first
474 5 bits (from the v3.0B opcode), but still kinda cool. mostly used
475 for operations that have src-as-dest: mostly this is LD/ST-with-update
476 but there are others.
479 def __init__(self
, dec
, op
):
482 self
.sel_in
= Signal(OutSel
, reset_less
=True)
483 self
.implicit_rs
= Signal(reset_less
=True) # SVP64 implicit RS/FRS
484 self
.implicit_from_rc
= Signal(reset_less
=True)# implicit RS from RC
485 self
.lk
= Signal(reset_less
=True)
486 self
.insn_in
= Signal(32, reset_less
=True)
487 self
.reg_out
= Data(5, "reg_o2")
488 self
.rs_en
= Signal(reset_less
=True) # FFT instruction detected
489 self
.fast_out
= Data(4, "fast_o2")
490 self
.fast_out3
= Data(4, "fast_o3")
492 def elaborate(self
, platform
):
496 #m.submodules.svdec = svdec = SVP64RegExtra()
498 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
499 #reg = Signal(5, reset_less=True)
501 if hasattr(op
, "upd"):
502 # update mode LD/ST uses read-reg A also as an output
503 with m
.If(op
.upd
== LDSTMode
.update
):
504 comb
+= self
.reg_out
.data
.eq(self
.dec
.RA
)
505 comb
+= self
.reg_out
.ok
.eq(1)
507 # B, BC or BCREG: potential implicit register (LR) output
508 # these give bl, bcl, bclrl, etc.
509 with m
.Switch(op
.internal_op
):
511 # BC* implicit register (LR)
512 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_B
, MicrOp
.OP_BCREG
):
513 with m
.If(self
.lk
): # "link" mode
514 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.LR
) # LR
515 comb
+= self
.fast_out
.ok
.eq(1)
517 # RFID 2nd and 3rd spr (fast)
518 with m
.Case(MicrOp
.OP_RFID
):
519 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.SRR1
) # SRR1
520 comb
+= self
.fast_out
.ok
.eq(1)
521 comb
+= self
.fast_out3
.data
.eq(FastRegsEnum
.SVSRR0
) # SVSRR0
522 comb
+= self
.fast_out3
.ok
.eq(1)
524 # SVP64 FFT mode, FP mul-add: 2nd output reg (FRS) same as FRT
525 # will be offset by VL in hardware
526 # with m.Case(MicrOp.OP_FP_MADD):
527 with m
.If(self
.implicit_rs
):
528 with m
.If(self
.implicit_from_rc
):
529 comb
+= self
.reg_out
.data
.eq(self
.dec
.FRC
) # same as RC
531 comb
+= self
.reg_out
.data
.eq(self
.dec
.FRT
) # same as RT
532 comb
+= self
.reg_out
.ok
.eq(1)
533 comb
+= self
.rs_en
.eq(1)
538 class DecodeRC(Elaboratable
):
539 """DecodeRc from instruction
541 decodes Record bit Rc
544 def __init__(self
, dec
):
546 self
.sel_in
= Signal(RCOE
, reset_less
=True)
547 self
.insn_in
= Signal(32, reset_less
=True)
548 self
.rc_out
= Data(1, "rc")
550 def elaborate(self
, platform
):
554 # select Record bit out field
555 with m
.Switch(self
.sel_in
):
556 with m
.Case(RCOE
.RC
, RCOE
.RC_ONLY
):
557 comb
+= self
.rc_out
.data
.eq(self
.dec
.Rc
)
558 comb
+= self
.rc_out
.ok
.eq(1)
559 with m
.Case(RCOE
.ONE
):
560 comb
+= self
.rc_out
.data
.eq(1)
561 comb
+= self
.rc_out
.ok
.eq(1)
562 with m
.Case(RCOE
.NONE
):
563 comb
+= self
.rc_out
.data
.eq(0)
564 comb
+= self
.rc_out
.ok
.eq(1)
569 class DecodeOE(Elaboratable
):
570 """DecodeOE from instruction
572 decodes OE field: uses RC decode detection which has now been
573 updated to separate out RC_ONLY. all cases RC_ONLY are *NOT*
574 listening to the OE field, here.
577 def __init__(self
, dec
, op
):
580 self
.sel_in
= Signal(RCOE
, reset_less
=True)
581 self
.insn_in
= Signal(32, reset_less
=True)
582 self
.oe_out
= Data(1, "oe")
584 def elaborate(self
, platform
):
588 with m
.Switch(self
.sel_in
):
589 with m
.Case(RCOE
.RC
):
590 comb
+= self
.oe_out
.data
.eq(self
.dec
.OE
)
591 comb
+= self
.oe_out
.ok
.eq(1)
594 comb
+= self
.oe_out
.data
.eq(0)
595 comb
+= self
.oe_out
.ok
.eq(0)
600 class DecodeCRIn(Elaboratable
):
601 """Decodes input CR from instruction
603 CR indices - insn fields - (not the data *in* the CR) require only 3
604 bits because they refer to CR0-CR7
607 def __init__(self
, dec
, op
):
610 self
.sel_in
= Signal(CRInSel
, reset_less
=True)
611 self
.insn_in
= Signal(32, reset_less
=True)
612 self
.cr_bitfield
= Data(3, "cr_bitfield")
613 self
.cr_bitfield_b
= Data(3, "cr_bitfield_b")
614 self
.cr_bitfield_o
= Data(3, "cr_bitfield_o")
615 self
.whole_reg
= Data(8, "cr_fxm")
616 self
.sv_override
= Signal(2, reset_less
=True) # do not do EXTRA spec
618 def elaborate(self
, platform
):
622 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
625 # zero-initialisation
626 comb
+= self
.cr_bitfield
.ok
.eq(0)
627 comb
+= self
.cr_bitfield_b
.ok
.eq(0)
628 comb
+= self
.cr_bitfield_o
.ok
.eq(0)
629 comb
+= self
.whole_reg
.ok
.eq(0)
630 comb
+= self
.sv_override
.eq(0)
632 # select the relevant CR bitfields
633 with m
.Switch(self
.sel_in
):
634 with m
.Case(CRInSel
.NONE
):
635 pass # No bitfield activated
636 with m
.Case(CRInSel
.CR0
):
637 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
638 comb
+= self
.cr_bitfield
.ok
.eq(1)
639 comb
+= self
.sv_override
.eq(1)
640 with m
.Case(CRInSel
.CR1
):
641 comb
+= self
.cr_bitfield
.data
.eq(1) # CR1 (MSB0 numbering)
642 comb
+= self
.cr_bitfield
.ok
.eq(1)
643 comb
+= self
.sv_override
.eq(2)
644 with m
.Case(CRInSel
.BI
):
645 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BI
[2:5])
646 comb
+= self
.cr_bitfield
.ok
.eq(1)
647 with m
.Case(CRInSel
.BFA
):
648 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BFA
)
649 comb
+= self
.cr_bitfield
.ok
.eq(1)
650 with m
.Case(CRInSel
.BA_BB
):
651 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BA
[2:5])
652 comb
+= self
.cr_bitfield
.ok
.eq(1)
653 comb
+= self
.cr_bitfield_b
.data
.eq(self
.dec
.BB
[2:5])
654 comb
+= self
.cr_bitfield_b
.ok
.eq(1)
655 comb
+= self
.cr_bitfield_o
.data
.eq(self
.dec
.BT
[2:5])
656 comb
+= self
.cr_bitfield_o
.ok
.eq(1)
657 with m
.Case(CRInSel
.BC
):
658 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BC
[2:5])
659 comb
+= self
.cr_bitfield
.ok
.eq(1)
660 with m
.Case(CRInSel
.WHOLE_REG
):
661 comb
+= self
.whole_reg
.ok
.eq(1)
662 move_one
= Signal(reset_less
=True)
663 comb
+= move_one
.eq(self
.insn_in
[20]) # MSB0 bit 11
664 with m
.If((op
.internal_op
== MicrOp
.OP_MFCR
) & move_one
):
665 # must one-hot the FXM field
666 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
667 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
669 # otherwise use all of it
670 comb
+= self
.whole_reg
.data
.eq(0xff)
675 class DecodeCROut(Elaboratable
):
676 """Decodes input CR from instruction
678 CR indices - insn fields - (not the data *in* the CR) require only 3
679 bits because they refer to CR0-CR7
682 def __init__(self
, dec
, op
):
685 self
.rc_in
= Signal(reset_less
=True)
686 self
.sel_in
= Signal(CROutSel
, reset_less
=True)
687 self
.insn_in
= Signal(32, reset_less
=True)
688 self
.cr_bitfield
= Data(3, "cr_bitfield")
689 self
.whole_reg
= Data(8, "cr_fxm")
690 self
.sv_override
= Signal(2, reset_less
=True) # do not do EXTRA spec
691 self
.cr_5bit
= Signal(reset_less
=True) # set True for 5-bit
692 self
.cr_2bit
= Signal(2, reset_less
=True) # get lowest 2 bits
694 def elaborate(self
, platform
):
698 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
701 comb
+= self
.cr_bitfield
.ok
.eq(0)
702 comb
+= self
.whole_reg
.ok
.eq(0)
703 comb
+= self
.sv_override
.eq(0)
704 comb
+= self
.cr_5bit
.eq(0)
706 # please note these MUST match (setting of cr_bitfield.ok) exactly
707 # with write_cr0 below in PowerDecoder2. the reason it's separated
708 # is to avoid having duplicate copies of DecodeCROut in multiple
709 # PowerDecoderSubsets. register decoding should be a one-off in
710 # PowerDecoder2. see https://bugs.libre-soc.org/show_bug.cgi?id=606
712 with m
.Switch(self
.sel_in
):
713 with m
.Case(CROutSel
.NONE
):
714 pass # No bitfield activated
715 with m
.Case(CROutSel
.CR0
):
716 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
717 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
718 comb
+= self
.sv_override
.eq(1)
719 with m
.Case(CROutSel
.CR1
):
720 comb
+= self
.cr_bitfield
.data
.eq(1) # CR1 (MSB0 numbering)
721 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
722 comb
+= self
.sv_override
.eq(2)
723 with m
.Case(CROutSel
.BF
):
724 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BF
)
725 comb
+= self
.cr_bitfield
.ok
.eq(1)
726 with m
.Case(CROutSel
.BT
):
727 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormXL
.BT
[2:5])
728 comb
+= self
.cr_bitfield
.ok
.eq(1)
729 comb
+= self
.cr_5bit
.eq(1)
730 comb
+= self
.cr_2bit
.eq(self
.dec
.FormXL
.BT
[0:2])
731 with m
.Case(CROutSel
.WHOLE_REG
):
732 comb
+= self
.whole_reg
.ok
.eq(1)
733 move_one
= Signal(reset_less
=True)
734 comb
+= move_one
.eq(self
.insn_in
[20])
735 with m
.If((op
.internal_op
== MicrOp
.OP_MTCRF
)):
737 # must one-hot the FXM field
738 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
739 with m
.If(ppick
.en_o
):
740 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
742 comb
+= self
.whole_reg
.data
.eq(0b00000001) # CR7
744 comb
+= self
.whole_reg
.data
.eq(self
.dec
.FXM
)
746 # otherwise use all of it
747 comb
+= self
.whole_reg
.data
.eq(0xff)
752 # dictionary of Input Record field names that, if they exist,
753 # will need a corresponding CSV Decoder file column (actually, PowerOp)
754 # to be decoded (this includes the single bit names)
755 record_names
= {'insn_type': 'internal_op',
756 'fn_unit': 'function_unit',
757 'SV_Ptype': 'SV_Ptype',
758 'SV_mode': 'SV_mode',
762 'imm_data': 'in2_sel',
763 'invert_in': 'inv_a',
764 'invert_out': 'inv_out',
767 'output_carry': 'cry_out',
768 'input_carry': 'cry_in',
769 'is_32bit': 'is_32b',
772 'data_len': 'ldst_len',
774 'byte_reverse': 'br',
775 'sign_extend': 'sgn_ext',
780 class PowerDecodeSubset(Elaboratable
):
781 """PowerDecodeSubset: dynamic subset decoder
783 only fields actually requested are copied over. hence, "subset" (duh).
786 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False, state
=None,
787 svp64_en
=True, regreduce_en
=False, fp_en
=False):
789 self
.svp64_en
= svp64_en
790 self
.regreduce_en
= regreduce_en
793 self
.is_svp64_mode
= Signal() # mark decoding as SVP64 Mode
794 self
.implicit_rs
= Signal() # implicit RS/FRS
795 self
.extend_rb_maxvl
= Signal() # jumps RB by an additional MAXVL
796 self
.extend_rc_maxvl
= Signal() # jumps RS by MAXVL from RC
797 self
.sv_rm
= SVP64Rec(name
="dec_svp64") # SVP64 RM field
798 self
.rm_dec
= SVP64RMModeDecode("svp64_rm_dec")
799 # set these to the predicate mask bits needed for the ALU
800 self
.pred_sm
= Signal() # TODO expand to SIMD mask width
801 self
.pred_dm
= Signal() # TODO expand to SIMD mask width
802 self
.sv_a_nz
= Signal(1)
805 self
.fn_name
= fn_name
807 opkls
= Decode2ToOperand
808 self
.do
= opkls(fn_name
)
810 col_subset
= self
.get_col_subset(self
.do
)
811 row_subset
= self
.rowsubsetfn
816 # "conditions" for Decoders, to enable some weird and wonderful
817 # alternatives. useful for PCR (Program Compatibility Register)
818 # amongst other things
821 # XXX NO 'SVP64FFT': self.use_svp64_fft,
826 # only needed for "main" PowerDecode2
828 self
.e
= Decode2ToExecute1Type(name
=self
.fn_name
, do
=self
.do
,
829 regreduce_en
=regreduce_en
)
831 # create decoder if one not already given
833 dec
= create_pdecode(name
=fn_name
, col_subset
=col_subset
,
834 row_subset
=row_subset
,
835 conditions
=conditions
, include_fp
=fp_en
)
838 # set up a copy of the PowerOp
839 self
.op
= PowerOp
.like(self
.dec
.op
)
841 # state information needed by the Decoder
843 state
= CoreState("dec2")
846 def get_col_subset(self
, do
):
847 subset
= {'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
848 for k
, v
in record_names
.items():
851 log("get_col_subset", self
.fn_name
, do
.fields
, subset
)
854 def rowsubsetfn(self
, opcode
, row
):
855 """select per-Function-Unit subset of opcodes to be processed
857 normally this just looks at the "unit" column. MMU is different
858 in that it processes specific SPR set/get operations that the SPR
861 return (row
['unit'] == self
.fn_name
or
862 # sigh a dreadful hack: MTSPR and MFSPR need to be processed
863 # by the MMU pipeline so we direct those opcodes to MMU **AND**
864 # SPR pipelines, then selectively weed out the SPRs that should
865 # or should not not go to each pipeline, further down.
866 # really this should be done by modifying the CSV syntax
867 # to support multiple tasks (unit column multiple entries)
868 # see https://bugs.libre-soc.org/show_bug.cgi?id=310
869 (self
.fn_name
== 'MMU' and row
['unit'] == 'SPR' and
870 row
['internal op'] in ['OP_MTSPR', 'OP_MFSPR']) or
871 # urrr... and the KAIVB SPR, which must also be redirected
872 # (to the TRAP pipeline)
873 # see https://bugs.libre-soc.org/show_bug.cgi?id=859
874 (self
.fn_name
== 'TRAP' and row
['unit'] == 'SPR' and
875 row
['internal op'] in ['OP_MTSPR', 'OP_MFSPR'])
879 ports
= self
.dec
.ports() + self
.e
.ports()
881 ports
+= self
.sv_rm
.ports()
882 ports
.append(self
.is_svp64_mode
)
883 ports
.append(self
.implicit_rs
)
886 def needs_field(self
, field
, op_field
):
891 return hasattr(do
, field
) and self
.op_get(op_field
) is not None
893 def do_get(self
, field
, final
=False):
894 if final
or self
.final
:
898 return getattr(do
, field
, None)
900 def do_copy(self
, field
, val
, final
=False):
901 df
= self
.do_get(field
, final
)
902 if df
is not None and val
is not None:
906 def op_get(self
, op_field
):
907 return getattr(self
.op
, op_field
, None)
909 def elaborate(self
, platform
):
910 if self
.regreduce_en
:
917 op
, do
= self
.dec
.op
, self
.do
918 msr
, cia
, svstate
= state
.msr
, state
.pc
, state
.svstate
919 # fill in for a normal instruction (not an exception)
920 # copy over if non-exception, non-privileged etc. is detected
922 if self
.fn_name
is None:
925 name
= self
.fn_name
+ "tmp"
926 self
.e_tmp
= Decode2ToExecute1Type(name
=name
, opkls
=self
.opkls
,
927 regreduce_en
=self
.regreduce_en
)
929 # set up submodule decoders
930 m
.submodules
.dec
= dec
= self
.dec
931 m
.submodules
.dec_rc
= self
.dec_rc
= dec_rc
= DecodeRC(self
.dec
)
932 m
.submodules
.dec_oe
= dec_oe
= DecodeOE(self
.dec
, op
)
935 # and SVP64 RM mode decoder
936 m
.submodules
.sv_rm_dec
= rm_dec
= self
.rm_dec
938 # copy op from decoder
939 comb
+= self
.op
.eq(self
.dec
.op
)
941 # copy instruction through...
942 for i
in [do
.insn
, dec_rc
.insn_in
, dec_oe
.insn_in
, ]:
943 comb
+= i
.eq(self
.dec
.opcode_in
)
945 # ...and subdecoders' input fields
946 comb
+= dec_rc
.sel_in
.eq(self
.op_get("rc_sel"))
947 comb
+= dec_oe
.sel_in
.eq(self
.op_get("rc_sel")) # XXX should be OE sel
950 comb
+= self
.do_copy("msr", msr
)
951 comb
+= self
.do_copy("cia", cia
)
952 comb
+= self
.do_copy("svstate", svstate
)
954 # set up instruction type
955 # no op: defaults to OP_ILLEGAL
956 internal_op
= self
.op_get("internal_op")
957 comb
+= self
.do_copy("insn_type", internal_op
)
959 # function unit for decoded instruction: requires minor redirect
961 fn
= self
.op_get("function_unit")
962 spr
= Signal(10, reset_less
=True)
963 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
965 # Microwatt doesn't implement the partition table
966 # instead has PRTBL register (SPR) to point to process table
967 # Kestrel has a KAIVB SPR to "rebase" exceptions. rebasing is normally
968 # done with Hypervisor Mode which is not implemented (yet)
970 is_mmu_spr
= Signal()
971 is_trap_spr
= Signal()
972 comb
+= is_spr_mv
.eq((internal_op
== MicrOp
.OP_MTSPR
) |
973 (internal_op
== MicrOp
.OP_MFSPR
))
974 comb
+= is_mmu_spr
.eq((spr
== SPR
.DSISR
.value
) |
975 (spr
== SPR
.DAR
.value
) |
976 (spr
== SPR
.PRTBL
.value
) |
977 (spr
== SPR
.PIDR
.value
))
978 comb
+= is_trap_spr
.eq((spr
== SPR
.KAIVB
.value
)
980 # MMU must receive MMU SPRs
981 with m
.If(is_spr_mv
& (fn
== Function
.SPR
) & is_mmu_spr
):
982 comb
+= self
.do_copy("fn_unit", Function
.MMU
)
983 comb
+= self
.do_copy("insn_type", internal_op
)
984 # TRAP must receive TRAP SPR KAIVB
985 with m
.If(is_spr_mv
& (fn
== Function
.SPR
) & is_trap_spr
):
986 comb
+= self
.do_copy("fn_unit", Function
.TRAP
)
987 comb
+= self
.do_copy("insn_type", internal_op
)
988 # SPR pipe must *not* receive MMU or TRAP SPRs
989 with m
.Elif(is_spr_mv
& ((fn
== Function
.MMU
) & ~is_mmu_spr
) &
990 ((fn
== Function
.TRAP
) & ~is_trap_spr
)):
991 comb
+= self
.do_copy("fn_unit", Function
.NONE
)
992 comb
+= self
.do_copy("insn_type", MicrOp
.OP_ILLEGAL
)
995 comb
+= self
.do_copy("fn_unit", fn
)
998 if self
.needs_field("zero_a", "in1_sel"):
999 m
.submodules
.dec_ai
= dec_ai
= DecodeAImm(self
.dec
)
1000 comb
+= dec_ai
.sv_nz
.eq(self
.sv_a_nz
)
1001 comb
+= dec_ai
.sel_in
.eq(self
.op_get("in1_sel"))
1002 comb
+= self
.do_copy("zero_a", dec_ai
.immz_out
) # RA==0 detected
1003 if self
.needs_field("imm_data", "in2_sel"):
1004 m
.submodules
.dec_bi
= dec_bi
= DecodeBImm(self
.dec
)
1005 comb
+= dec_bi
.sel_in
.eq(self
.op_get("in2_sel"))
1006 comb
+= self
.do_copy("imm_data", dec_bi
.imm_out
) # imm in RB
1008 # CR in/out - note: these MUST match with what happens in
1010 rc_out
= self
.dec_rc
.rc_out
.data
1011 with m
.Switch(self
.op_get("cr_out")):
1012 with m
.Case(CROutSel
.CR0
, CROutSel
.CR1
):
1013 comb
+= self
.do_copy("write_cr0", rc_out
) # only when RC=1
1014 with m
.Case(CROutSel
.BF
, CROutSel
.BT
):
1015 comb
+= self
.do_copy("write_cr0", 1)
1017 comb
+= self
.do_copy("input_cr", self
.op_get("cr_in")) # CR in
1018 comb
+= self
.do_copy("output_cr", self
.op_get("cr_out")) # CR out
1021 # connect up SVP64 RM Mode decoding. however... we need a shorter
1022 # path, for the LDST bit-reverse detection. so perform partial
1023 # decode when SVP64 is detected. then, bit-reverse mode can be
1024 # quickly determined, and the Decoder result MUXed over to
1025 # the alternative decoder, svdecldst. what a mess... *sigh*
1026 sv_ptype
= self
.op_get("SV_Ptype")
1027 sv_mode
= self
.op_get("SV_mode")
1028 fn
= self
.op_get("function_unit")
1029 comb
+= rm_dec
.sv_mode
.eq(sv_mode
) # BRANCH/CROP/LDST_IMM etc.
1030 comb
+= rm_dec
.fn_in
.eq(fn
) # decode needs to know Fn type
1031 comb
+= rm_dec
.ptype_in
.eq(sv_ptype
) # Single/Twin predicated
1032 comb
+= rm_dec
.rc_in
.eq(rc_out
) # Rc=1
1033 comb
+= rm_dec
.rm_in
.eq(self
.sv_rm
) # SVP64 RM mode
1034 if self
.needs_field("imm_data", "in2_sel"):
1035 bzero
= dec_bi
.imm_out
.ok
& ~dec_bi
.imm_out
.data
.bool()
1036 comb
+= rm_dec
.ldst_imz_in
.eq(bzero
) # B immediate is zero
1038 # main PowerDecoder2 determines if different SVP64 modes enabled
1039 # detect if SVP64 FFT mode enabled (really bad hack),
1040 # exclude fcfids and others
1041 # XXX this is a REALLY bad hack, REALLY has to be done better.
1042 # likely with a sub-decoder.
1043 # what this ultimately does is enable the 2nd implicit register
1044 # (FRS) for SVP64-decoding. all of these instructions are
1045 # 3-in 2-out but there is not enough room either in the
1046 # opcode *or* EXTRA2/3 to specify a 5th operand.
1048 comb
+= major
.eq(self
.dec
.opcode_in
[26:32])
1050 comb
+= xo
.eq(self
.dec
.opcode_in
[1:11])
1051 comb
+= self
.implicit_rs
.eq(0)
1052 comb
+= self
.extend_rb_maxvl
.eq(0)
1053 comb
+= self
.extend_rc_maxvl
.eq(0)
1054 # implicit RS for major 59
1055 with m
.If((major
== 59) & xo
.matches(
1056 '-----00100', # ffmsubs
1057 '-----00101', # ffmadds
1058 '-----00110', # ffnmsubs
1059 '-----00111', # ffnmadds
1060 '1111100000', # ffadds
1061 '-----11011', # fdmadds
1063 comb
+= self
.implicit_rs
.eq(1)
1064 comb
+= self
.extend_rb_maxvl
.eq(1) # extend RB
1066 comb
+= xo6
.eq(self
.dec
.opcode_in
[0:6])
1067 # implicit RS for major 4
1068 with m
.If((major
== 4) & xo6
.matches(
1071 '111001', # maddedus
1072 '111010', # divmod2du
1076 comb
+= self
.implicit_rs
.eq(1)
1077 comb
+= self
.extend_rc_maxvl
.eq(1) # RS=RT+MAXVL or RS=RC
1078 # implicit RS for major 22, integer maddsubrs
1079 with m
.If((major
== 22) & xo6
.matches(
1080 '-01000', # maddsubrs
1084 comb
+= self
.implicit_rs
.eq(1)
1085 comb
+= self
.extend_rb_maxvl
.eq(1) # extend RB
1088 comb
+= self
.do_copy("rc", dec_rc
.rc_out
)
1090 # OE only enabled when SVP64 not active
1091 with m
.If(~self
.is_svp64_mode
):
1092 comb
+= self
.do_copy("oe", dec_oe
.oe_out
)
1093 # RC1 overrides Rc if rc type is NONE or ONE or Rc=0, in svp64_mode
1094 # for instructions with a forced-Rc=1 (stbcx., pcdec.)
1095 # the RC1 RM bit *becomes* Rc=0/1, but for instructions
1096 # that have Rc=0/1 then when Rc=0 RC1 *becomes* (replaces) Rc.
1097 with m
.Elif((dec_rc
.sel_in
.matches(RCOE
.RC
, RCOE
.RC_ONLY
) &
1098 dec_rc
.rc_out
.data
== 0) |
1099 (dec_rc
.sel_in
== RCOE
.ONE
)):
1100 RC1
= Data(1, "RC1")
1101 comb
+= RC1
.ok
.eq(rm_dec
.RC1
)
1102 comb
+= RC1
.RC1
.eq(rm_dec
.RC1
)
1103 comb
+= self
.do_copy("rc", RC1
)
1105 comb
+= self
.do_copy("oe", dec_oe
.oe_out
)
1107 # decoded/selected instruction flags
1108 comb
+= self
.do_copy("data_len", self
.op_get("ldst_len"))
1109 comb
+= self
.do_copy("invert_in", self
.op_get("inv_a"))
1110 comb
+= self
.do_copy("invert_out", self
.op_get("inv_out"))
1111 comb
+= self
.do_copy("input_carry", self
.op_get("cry_in"))
1112 comb
+= self
.do_copy("output_carry", self
.op_get("cry_out"))
1113 comb
+= self
.do_copy("is_32bit", self
.op_get("is_32b"))
1114 comb
+= self
.do_copy("is_signed", self
.op_get("sgn"))
1115 lk
= self
.op_get("lk")
1118 comb
+= self
.do_copy("lk", self
.dec
.LK
) # XXX TODO: accessor
1120 comb
+= self
.do_copy("byte_reverse", self
.op_get("br"))
1121 comb
+= self
.do_copy("sign_extend", self
.op_get("sgn_ext"))
1122 comb
+= self
.do_copy("ldst_mode", self
.op_get("upd")) # LD/ST mode
1123 comb
+= self
.do_copy("reserve", self
.op_get("rsrv")) # atomic
1125 # copy over SVP64 input record fields (if they exist)
1127 # TODO, really do we have to do these explicitly?? sigh
1128 # for (field, _) in sv_input_record_layout:
1129 # comb += self.do_copy(field, self.rm_dec.op_get(field))
1130 comb
+= self
.do_copy("sv_saturate", self
.rm_dec
.saturate
)
1131 comb
+= self
.do_copy("sv_Ptype", self
.rm_dec
.ptype_in
)
1132 comb
+= self
.do_copy("sv_ldstmode", self
.rm_dec
.ldstmode
)
1133 # these get set up based on incoming mask bits. TODO:
1134 # pass in multiple bits (later, when SIMD backends are enabled)
1135 with m
.If(self
.rm_dec
.pred_sz
):
1136 comb
+= self
.do_copy("sv_pred_sz", ~self
.pred_sm
)
1137 with m
.If(self
.rm_dec
.pred_dz
):
1138 comb
+= self
.do_copy("sv_pred_dz", ~self
.pred_dm
)
1143 class PowerDecode2(PowerDecodeSubset
):
1144 """PowerDecode2: the main instruction decoder.
1146 whilst PowerDecode is responsible for decoding the actual opcode, this
1147 module encapsulates further specialist, sparse information and
1148 expansion of fields that is inconvenient to have in the CSV files.
1149 for example: the encoding of the immediates, which are detected
1150 and expanded out to their full value from an annotated (enum)
1153 implicit register usage is also set up, here. for example: OP_BC
1154 requires implicitly reading CTR, OP_RFID requires implicitly writing
1157 in addition, PowerDecoder2 is responsible for detecting whether
1158 instructions are illegal (or privileged) or not, and instead of
1159 just leaving at that, *replacing* the instruction to execute with
1160 a suitable alternative (trap).
1162 LDSTExceptions are done the cycle _after_ they're detected (after
1163 they come out of LDSTCompUnit). basically despite the instruction
1164 being decoded, the results of the decode are completely ignored
1165 and "exception.happened" used to set the "actual" instruction to
1166 "OP_TRAP". the LDSTException data structure gets filled in,
1167 in the CompTrapOpSubset and that's what it fills in SRR.
1169 to make this work, TestIssuer must notice "exception.happened"
1170 after the (failed) LD/ST and copies the LDSTException info from
1171 the output, into here (PowerDecoder2). without incrementing PC.
1173 also instr_fault works the same way: the instruction is "rewritten"
1174 so that the "fake" op that gets created is OP_FETCH_FAILED
1177 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False,
1178 state
=None, svp64_en
=True, regreduce_en
=False, fp_en
=False):
1179 super().__init
__(dec
, opkls
, fn_name
, final
, state
, svp64_en
,
1180 regreduce_en
=False, fp_en
=fp_en
)
1181 self
.ldst_exc
= LDSTException("dec2_exc") # rewrites as OP_TRAP
1182 self
.instr_fault
= Signal() # rewrites instruction as OP_FETCH_FAILED
1183 self
.crout_5bit
= Signal() # CR out is 5-bit
1186 self
.cr_out_isvec
= Signal(1, name
="cr_out_isvec")
1187 self
.cr_in_isvec
= Signal(1, name
="cr_in_isvec")
1188 self
.cr_in_b_isvec
= Signal(1, name
="cr_in_b_isvec")
1189 self
.cr_in_o_isvec
= Signal(1, name
="cr_in_o_isvec")
1190 self
.in1_isvec
= Signal(1, name
="reg_a_isvec")
1191 self
.in2_isvec
= Signal(1, name
="reg_b_isvec")
1192 self
.in3_isvec
= Signal(1, name
="reg_c_isvec")
1193 self
.o_isvec
= Signal(7, name
="reg_o_isvec")
1194 self
.o2_isvec
= Signal(7, name
="reg_o2_isvec")
1195 self
.in1_step
= Signal(7, name
="reg_a_step")
1196 self
.in2_step
= Signal(7, name
="reg_b_step")
1197 self
.in3_step
= Signal(7, name
="reg_c_step")
1198 self
.o_step
= Signal(7, name
="reg_o_step")
1199 self
.o2_step
= Signal(7, name
="reg_o2_step")
1200 self
.remap_active
= Signal(5, name
="remap_active") # per reg
1201 self
.no_in_vec
= Signal(1, name
="no_in_vec") # no inputs vector
1202 self
.no_out_vec
= Signal(1, name
="no_out_vec") # no outputs vector
1203 self
.loop_continue
= Signal(1, name
="loop_continue")
1205 self
.no_in_vec
= Const(1, 1)
1206 self
.no_out_vec
= Const(1, 1)
1207 self
.loop_continue
= Const(0, 1)
1209 def get_col_subset(self
, opkls
):
1210 subset
= super().get_col_subset(opkls
)
1211 subset
.add("asmcode")
1212 subset
.add("in1_sel")
1213 subset
.add("in2_sel")
1214 subset
.add("in3_sel")
1215 subset
.add("out_sel")
1217 subset
.add("sv_in1")
1218 subset
.add("sv_in2")
1219 subset
.add("sv_in3")
1220 subset
.add("sv_out")
1221 subset
.add("sv_out2")
1222 subset
.add("sv_cr_in")
1223 subset
.add("sv_cr_out")
1224 subset
.add("SV_Etype")
1225 subset
.add("SV_Ptype")
1226 subset
.add("SV_mode")
1227 # from SVP64RMModeDecode
1228 for (field
, _
) in sv_input_record_layout
:
1231 subset
.add("internal_op")
1235 def elaborate(self
, platform
):
1236 m
= super().elaborate(platform
)
1239 op
, e_out
, do_out
= self
.op
, self
.e
, self
.e
.do
1240 dec_spr
, msr
, cia
, ext_irq
= state
.dec
, state
.msr
, state
.pc
, state
.eint
1241 rc_out
= self
.dec_rc
.rc_out
.data
1245 # fill in for a normal instruction (not an exception)
1246 # copy over if non-exception, non-privileged etc. is detected
1248 # set up submodule decoders
1249 m
.submodules
.dec_a
= dec_a
= DecodeA(self
.dec
, op
, self
.regreduce_en
)
1250 m
.submodules
.dec_b
= dec_b
= DecodeB(self
.dec
, op
)
1251 m
.submodules
.dec_c
= dec_c
= DecodeC(self
.dec
, op
)
1252 m
.submodules
.dec_o
= dec_o
= DecodeOut(self
.dec
, op
, self
.regreduce_en
)
1253 m
.submodules
.dec_o2
= dec_o2
= DecodeOut2(self
.dec
, op
)
1254 m
.submodules
.dec_cr_in
= self
.dec_cr_in
= DecodeCRIn(self
.dec
, op
)
1255 m
.submodules
.dec_cr_out
= self
.dec_cr_out
= DecodeCROut(self
.dec
, op
)
1256 comb
+= dec_a
.sv_nz
.eq(self
.sv_a_nz
)
1257 comb
+= self
.crout_5bit
.eq(self
.dec_cr_out
.cr_5bit
)
1260 # and SVP64 Extra decoders
1261 m
.submodules
.crout_svdec
= crout_svdec
= SVP64CRExtra()
1262 m
.submodules
.crin_svdec
= crin_svdec
= SVP64CRExtra()
1263 m
.submodules
.crin_svdec_b
= crin_svdec_b
= SVP64CRExtra()
1264 m
.submodules
.crin_svdec_o
= crin_svdec_o
= SVP64CRExtra()
1265 m
.submodules
.in1_svdec
= in1_svdec
= SVP64RegExtra()
1266 m
.submodules
.in2_svdec
= in2_svdec
= SVP64RegExtra()
1267 m
.submodules
.in3_svdec
= in3_svdec
= SVP64RegExtra()
1268 m
.submodules
.o_svdec
= o_svdec
= SVP64RegExtra()
1269 m
.submodules
.o2_svdec
= o2_svdec
= SVP64RegExtra()
1271 # debug access to cr svdec (used in get_pdecode_cr_in/out)
1272 self
.crout_svdec
= crout_svdec
1273 self
.crin_svdec
= crin_svdec
1275 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
1276 reg
= Signal(5, reset_less
=True)
1278 # copy instruction through...
1279 for i
in [do
.insn
, dec_a
.insn_in
, dec_b
.insn_in
,
1280 self
.dec_cr_in
.insn_in
, self
.dec_cr_out
.insn_in
,
1281 dec_c
.insn_in
, dec_o
.insn_in
, dec_o2
.insn_in
]:
1282 comb
+= i
.eq(self
.dec
.opcode_in
)
1285 comb
+= self
.dec_cr_in
.sel_in
.eq(self
.op_get("cr_in"))
1286 comb
+= self
.dec_cr_out
.sel_in
.eq(self
.op_get("cr_out"))
1287 comb
+= self
.dec_cr_out
.rc_in
.eq(rc_out
)
1290 comb
+= self
.do_copy("read_cr_whole", self
.dec_cr_in
.whole_reg
)
1291 comb
+= self
.do_copy("write_cr_whole", self
.dec_cr_out
.whole_reg
)
1293 # ...and subdecoders' input fields
1294 comb
+= dec_a
.sel_in
.eq(self
.op_get("in1_sel"))
1295 comb
+= dec_b
.sel_in
.eq(self
.op_get("in2_sel"))
1296 comb
+= dec_c
.sel_in
.eq(self
.op_get("in3_sel"))
1297 comb
+= dec_o
.sel_in
.eq(self
.op_get("out_sel"))
1298 comb
+= dec_o2
.sel_in
.eq(self
.op_get("out_sel"))
1300 comb
+= dec_o2
.implicit_rs
.eq(self
.implicit_rs
)
1301 comb
+= dec_o2
.implicit_from_rc
.eq(self
.extend_rc_maxvl
)
1302 if hasattr(do
, "lk"):
1303 comb
+= dec_o2
.lk
.eq(do
.lk
)
1306 # now do the SVP64 munging. op.SV_Etype and op.sv_in1 comes from
1307 # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
1308 # which in turn were auto-generated by sv_analysis.py
1309 extra
= self
.sv_rm
.extra
# SVP64 extra bits 10:18
1314 comb
+= crout_svdec
.idx
.eq(self
.op_get("sv_cr_out"))
1315 comb
+= self
.cr_out_isvec
.eq(crout_svdec
.isvec
)
1318 # CR in - selection slightly different due to shared CR field sigh
1319 cr_a_idx
= Signal(SVEXTRA
)
1320 cr_b_idx
= Signal(SVEXTRA
)
1322 # these change slightly, when decoding BA/BB. really should have
1323 # their own separate CSV column: sv_cr_in1 and sv_cr_in2, but hey
1324 comb
+= cr_a_idx
.eq(self
.op_get("sv_cr_in"))
1325 comb
+= cr_b_idx
.eq(SVEXTRA
.NONE
)
1326 with m
.If(self
.op_get("sv_cr_in") == SVEXTRA
.Idx_1_2
.value
):
1327 comb
+= cr_a_idx
.eq(SVEXTRA
.Idx1
)
1328 comb
+= cr_b_idx
.eq(SVEXTRA
.Idx2
)
1330 comb
+= self
.cr_in_isvec
.eq(crin_svdec
.isvec
)
1331 comb
+= self
.cr_in_b_isvec
.eq(crin_svdec_b
.isvec
)
1332 comb
+= self
.cr_in_o_isvec
.eq(crin_svdec_o
.isvec
)
1334 # indices are slightly different, BA/BB mess sorted above
1335 comb
+= crin_svdec
.idx
.eq(cr_a_idx
) # SVP64 CR in A
1336 comb
+= crin_svdec_b
.idx
.eq(cr_b_idx
) # SVP64 CR in B
1338 comb
+= crin_svdec_o
.idx
.eq(self
.op_get("sv_cr_out"))
1340 # get SVSTATE srcstep (TODO: elwidth etc.) needed below
1341 vl
= Signal
.like(self
.state
.svstate
.vl
)
1342 maxvl
= Signal
.like(self
.state
.svstate
.maxvl
)
1343 subvl
= Signal
.like(self
.rm_dec
.rm_in
.subvl
)
1344 srcstep
= Signal
.like(self
.state
.svstate
.srcstep
)
1345 dststep
= Signal
.like(self
.state
.svstate
.dststep
)
1346 ssubstep
= Signal
.like(self
.state
.svstate
.ssubstep
)
1347 dsubstep
= Signal
.like(self
.state
.svstate
.ssubstep
)
1348 comb
+= vl
.eq(self
.state
.svstate
.vl
)
1349 comb
+= maxvl
.eq(self
.state
.svstate
.maxvl
)
1350 comb
+= subvl
.eq(self
.rm_dec
.rm_in
.subvl
)
1351 comb
+= srcstep
.eq(self
.state
.svstate
.srcstep
)
1352 comb
+= dststep
.eq(self
.state
.svstate
.dststep
)
1353 comb
+= ssubstep
.eq(self
.state
.svstate
.ssubstep
)
1354 comb
+= dsubstep
.eq(self
.state
.svstate
.dsubstep
)
1356 in1_step
, in2_step
= self
.in1_step
, self
.in2_step
1357 in3_step
= self
.in3_step
1358 o_step
, o2_step
= self
.o_step
, self
.o2_step
1360 # multiply vl by subvl - note that this is only 7 bit!
1361 # when elwidth overrides get involved this will have to go up
1363 comb
+= vmax
.eq(vl
*(subvl
+1))
1365 # registers a, b, c and out and out2 (LD/ST EA)
1366 sv_etype
= self
.op_get("SV_Etype")
1367 for i
, stuff
in enumerate((
1368 ("RA", e
.read_reg1
, dec_a
.reg_out
, in1_svdec
, in1_step
, False),
1369 ("RB", e
.read_reg2
, dec_b
.reg_out
, in2_svdec
, in2_step
, False),
1370 ("RC", e
.read_reg3
, dec_c
.reg_out
, in3_svdec
, in3_step
, False),
1371 ("RT", e
.write_reg
, dec_o
.reg_out
, o_svdec
, o_step
, True),
1372 ("EA", e
.write_ea
, dec_o2
.reg_out
, o2_svdec
, o2_step
, True))):
1373 rname
, to_reg
, fromreg
, svdec
, remapstep
, out
= stuff
1374 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1375 comb
+= svdec
.etype
.eq(sv_etype
) # EXTRA2/3 for this insn
1376 comb
+= svdec
.reg_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1377 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1378 # *screaam* FFT mode needs an extra offset for RB
1379 # similar to FRS/FRT (below). all of this needs cleanup
1380 offs
= Signal(7, name
="offs_"+rname
, reset_less
=True)
1383 # when FFT sv.ffmadd detected, and REMAP not in use,
1384 # automagically add on an extra offset to RB.
1385 # however when REMAP is active, the FFT REMAP
1386 # schedule takes care of this offset.
1387 with m
.If(dec_o2
.reg_out
.ok
& dec_o2
.rs_en
&
1388 self
.extend_rb_maxvl
):
1389 with m
.If(~self
.remap_active
[i
]):
1390 with m
.If(svdec
.isvec
):
1391 comb
+= offs
.eq(maxvl
) # MAXVL for Vectors
1392 # detect if Vectorised: add srcstep/dststep if yes.
1393 # to_reg is 7-bits, outs get dststep added, ins get srcstep
1394 with m
.If(svdec
.isvec
):
1395 selectstep
= dststep
if out
else srcstep
1396 subselect
= dsubstep
if out
else ssubstep
1397 step
= Signal(7, name
="step_%s" % rname
.lower())
1398 with m
.If(self
.remap_active
[i
]):
1399 comb
+= step
.eq((remapstep
*(subvl
+1))+subselect
)
1401 comb
+= step
.eq((selectstep
*(subvl
+1))+subselect
)
1402 # reverse gear goes the opposite way
1403 with m
.If(self
.rm_dec
.reverse_gear
):
1404 comb
+= to_reg
.offs
.eq(offs
+(vmax
-1-step
))
1406 comb
+= to_reg
.offs
.eq(offs
+step
)
1408 comb
+= to_reg
.offs
.eq(offs
)
1409 comb
+= to_reg
.base
.eq(svdec
.reg_out
)
1410 comb
+= to_reg
.data
.eq(to_reg
.base
+ to_reg
.offs
)
1412 # SVP64 in/out fields
1413 comb
+= in1_svdec
.idx
.eq(self
.op_get("sv_in1")) # reg #1 (in1_sel)
1414 comb
+= in2_svdec
.idx
.eq(self
.op_get("sv_in2")) # reg #2 (in2_sel)
1415 comb
+= in3_svdec
.idx
.eq(self
.op_get("sv_in3")) # reg #3 (in3_sel)
1416 comb
+= o_svdec
.idx
.eq(self
.op_get("sv_out")) # output (out_sel)
1418 comb
+= o2_svdec
.idx
.eq(self
.op_get("sv_out2"))
1419 # XXX TODO - work out where this should come from. the problem is
1420 # that LD-with-update is implied (computed from "is instruction in
1421 # "update mode" rather than specified cleanly as its own CSV column
1423 # output reg-is-vectorised (and when no in/out is vectorised)
1424 comb
+= self
.in1_isvec
.eq(in1_svdec
.isvec
)
1425 comb
+= self
.in2_isvec
.eq(in2_svdec
.isvec
)
1426 comb
+= self
.in3_isvec
.eq(in3_svdec
.isvec
)
1427 comb
+= self
.o_isvec
.eq(o_svdec
.isvec
)
1428 comb
+= self
.o2_isvec
.eq(o2_svdec
.isvec
)
1430 # urrr... don't ask... the implicit register FRS in FFT mode
1431 # "tracks" FRT exactly except it's offset by MAXVL. rather than
1432 # mess up the above with if-statements, override it here.
1433 # same trick is applied to FRB, above, but it's a lot cleaner there
1434 with m
.If(dec_o2
.reg_out
.ok
& dec_o2
.rs_en
):
1435 imp_reg_out
= Signal(7)
1436 imp_isvec
= Signal(1)
1437 with m
.If(self
.extend_rc_maxvl
): # maddedu etc. from RC
1438 comb
+= imp_isvec
.eq(in3_svdec
.isvec
)
1439 comb
+= imp_reg_out
.eq(in3_svdec
.reg_out
)
1441 comb
+= imp_isvec
.eq(o_svdec
.isvec
)
1442 comb
+= imp_reg_out
.eq(o_svdec
.reg_out
)
1444 with m
.If(~self
.remap_active
[4]):
1445 with m
.If(imp_isvec
):
1446 comb
+= offs
.eq(maxvl
) # MAXVL for Vectors
1447 with m
.Elif(self
.extend_rc_maxvl
): # maddedu etc. from RC
1448 comb
+= offs
.eq(0) # keep as RC
1450 comb
+= offs
.eq(1) # add 1 if scalar
1451 with m
.If(imp_isvec
):
1452 step
= Signal(7, name
="step_%s" % rname
.lower())
1453 with m
.If(self
.remap_active
[4]):
1454 with m
.If(self
.extend_rc_maxvl
): # maddedu etc. from RC
1455 comb
+= step
.eq(in3_step
)
1457 comb
+= step
.eq(o2_step
)
1459 comb
+= step
.eq(dststep
)
1460 # reverse gear goes the opposite way
1461 with m
.If(self
.rm_dec
.reverse_gear
):
1462 roffs
= offs
+(vl
-1-step
)
1463 comb
+= e
.write_ea
.data
.eq(roffs
)
1465 comb
+= e
.write_ea
.data
.eq(offs
+step
)
1467 comb
+= e
.write_ea
.offs
.eq(offs
)
1468 comb
+= e
.write_ea
.base
.eq(imp_reg_out
)
1469 comb
+= e
.write_ea
.data
.eq(e
.write_ea
.base
+ e
.write_ea
.offs
)
1470 # ... but write to *second* output
1471 comb
+= self
.o2_isvec
.eq(imp_isvec
)
1472 comb
+= o2_svdec
.idx
.eq(self
.op_get("sv_out"))
1474 # TODO add SPRs here. must be True when *all* are scalar
1475 l
= map(lambda svdec
: svdec
.isvec
, [in1_svdec
, in2_svdec
, in3_svdec
,
1476 crin_svdec
, crin_svdec_b
,
1478 comb
+= self
.no_in_vec
.eq(~
Cat(*l
).bool()) # all input scalar
1479 l
= map(lambda svdec
: svdec
.isvec
, [
1480 o2_svdec
, o_svdec
, crout_svdec
])
1481 # in mapreduce mode, scalar out is *allowed*
1482 with m
.If(self
.rm_dec
.mode
== SVP64RMMode
.MAPREDUCE
.value
):
1483 comb
+= self
.no_out_vec
.eq(0)
1486 comb
+= self
.no_out_vec
.eq(~
Cat(*l
).bool())
1487 # now create a general-purpose "test" as to whether looping
1488 # should continue. this doesn't include predication bit-tests
1489 loop
= self
.loop_continue
1490 with m
.Switch(self
.op_get("SV_Ptype")):
1491 with m
.Case(SVPType
.P2
.value
):
1493 # TODO: *and cache-inhibited LD/ST!*
1494 comb
+= loop
.eq(~
(self
.no_in_vec | self
.no_out_vec
))
1495 with m
.Case(SVPType
.P1
.value
):
1496 # single-predication, test relies on dest only
1497 comb
+= loop
.eq(~self
.no_out_vec
)
1499 # not an SV operation, no looping
1502 # condition registers (CR)
1503 for to_reg
, cr
, name
, svdec
, out
in (
1504 (e
.read_cr1
, self
.dec_cr_in
, "cr_bitfield", crin_svdec
, 0),
1505 (e
.read_cr2
, self
.dec_cr_in
, "cr_bitfield_b", crin_svdec_b
, 0),
1506 (e
.read_cr3
, self
.dec_cr_in
, "cr_bitfield_o", crin_svdec_o
, 0),
1507 (e
.write_cr
, self
.dec_cr_out
, "cr_bitfield", crout_svdec
, 1)):
1508 fromreg
= getattr(cr
, name
)
1509 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1510 comb
+= svdec
.etype
.eq(sv_etype
) # EXTRA2/3 for this insn
1511 comb
+= svdec
.cr_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1512 with m
.If(svdec
.isvec
):
1513 # check if this is CR0 or CR1: treated differently
1514 # (does not "listen" to EXTRA2/3 spec for a start)
1515 # also: the CRs start from completely different locations
1516 step
= dststep
if out
else srcstep
1517 with m
.If(cr
.sv_override
== 1): # CR0
1518 offs
= SVP64CROffs
.CR0
1519 comb
+= to_reg
.data
.eq(step
+offs
)
1520 with m
.Elif(cr
.sv_override
== 2): # CR1
1521 offs
= SVP64CROffs
.CR1
1522 comb
+= to_reg
.data
.eq(step
+1)
1524 comb
+= to_reg
.data
.eq(step
+svdec
.cr_out
) # 7-bit out
1526 comb
+= to_reg
.data
.eq(svdec
.cr_out
) # 7-bit output
1527 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1529 # sigh must determine if RA is nonzero (7 bit)
1530 comb
+= self
.sv_a_nz
.eq(e
.read_reg1
.data
!= Const(0, 7))
1532 # connect up to/from read/write GPRs
1533 for to_reg
, fromreg
in ((e
.read_reg1
, dec_a
.reg_out
),
1534 (e
.read_reg2
, dec_b
.reg_out
),
1535 (e
.read_reg3
, dec_c
.reg_out
),
1536 (e
.write_reg
, dec_o
.reg_out
),
1537 (e
.write_ea
, dec_o2
.reg_out
)):
1538 comb
+= to_reg
.data
.eq(fromreg
.data
)
1539 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1541 # connect up to/from read/write CRs
1542 for to_reg
, cr
, name
in (
1543 (e
.read_cr1
, self
.dec_cr_in
, "cr_bitfield", ),
1544 (e
.read_cr2
, self
.dec_cr_in
, "cr_bitfield_b", ),
1545 (e
.read_cr3
, self
.dec_cr_in
, "cr_bitfield_o", ),
1546 (e
.write_cr
, self
.dec_cr_out
, "cr_bitfield", )):
1547 fromreg
= getattr(cr
, name
)
1548 comb
+= to_reg
.data
.eq(fromreg
.data
)
1549 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1552 comb
+= self
.rm_dec
.ldst_ra_vec
.eq(self
.in1_isvec
) # RA is vector
1553 comb
+= self
.rm_dec
.cr_5bit_in
.eq(self
.crout_5bit
) # CR is 5-bit
1554 # take bottom 2 bits of CR out (CR field selector)
1555 with m
.If(self
.crout_5bit
):
1556 comb
+= self
.rm_dec
.cr_2bit_in
.eq(self
.dec_cr_out
.cr_2bit
)
1559 comb
+= e
.read_spr1
.eq(dec_a
.spr_out
)
1560 comb
+= e
.write_spr
.eq(dec_o
.spr_out
)
1562 # Fast regs out including SRR0/1/SVSRR0
1563 comb
+= e
.read_fast1
.eq(dec_a
.fast_out
)
1564 comb
+= e
.read_fast2
.eq(dec_b
.fast_out
)
1565 comb
+= e
.write_fast1
.eq(dec_o
.fast_out
) # SRR0 (OP_RFID)
1566 comb
+= e
.write_fast2
.eq(dec_o2
.fast_out
) # SRR1 (ditto)
1567 comb
+= e
.write_fast3
.eq(dec_o2
.fast_out3
) # SVSRR0 (ditto)
1568 # and State regs (DEC, TB)
1569 comb
+= e
.read_state1
.eq(dec_a
.state_out
) # DEC/TB
1570 comb
+= e
.write_state1
.eq(dec_o
.state_out
) # DEC/TB
1572 # sigh this is exactly the sort of thing for which the
1573 # decoder is designed to not need. MTSPR, MFSPR and others need
1574 # access to the XER bits. however setting e.oe is not appropriate
1575 internal_op
= self
.op_get("internal_op")
1576 with m
.If(internal_op
== MicrOp
.OP_MFSPR
):
1577 comb
+= e
.xer_in
.eq(0b111) # SO, CA, OV
1578 with m
.If(internal_op
== MicrOp
.OP_CMP
):
1579 comb
+= e
.xer_in
.eq(1 << XERRegsEnum
.SO
) # SO
1580 with m
.If(internal_op
== MicrOp
.OP_MTSPR
):
1581 comb
+= e
.xer_out
.eq(1)
1583 # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
1584 with m
.If(op
.internal_op
== MicrOp
.OP_TRAP
):
1585 # *DO NOT* call self.trap here. that would reset absolutely
1586 # everything including destroying read of RA and RB.
1587 comb
+= self
.do_copy("trapaddr", 0x70) # strip first nibble
1589 ####################
1590 # ok so the instruction's been decoded, blah blah, however
1591 # now we need to determine if it's actually going to go ahead...
1592 # *or* if in fact it's a privileged operation, whether there's
1593 # an external interrupt, etc. etc. this is a simple priority
1594 # if-elif-elif sequence. decrement takes highest priority,
1595 # EINT next highest, privileged operation third.
1597 # check if instruction is privileged
1598 is_priv_insn
= instr_is_priv(m
, op
.internal_op
, e
.do
.insn
)
1600 # different IRQ conditions
1601 ext_irq_ok
= Signal()
1602 dec_irq_ok
= Signal()
1605 ldst_exc
= self
.ldst_exc
1607 comb
+= ext_irq_ok
.eq(ext_irq
& msr
[MSR
.EE
]) # v3.0B p944 (MSR.EE)
1608 comb
+= dec_irq_ok
.eq(dec_spr
[63] & msr
[MSR
.EE
]) # 6.5.11 p1076
1609 comb
+= priv_ok
.eq(is_priv_insn
& msr
[MSR
.PR
])
1610 comb
+= illeg_ok
.eq(op
.internal_op
== MicrOp
.OP_ILLEGAL
)
1612 # absolute top priority: check for an instruction failed
1613 with m
.If(self
.instr_fault
):
1614 comb
+= self
.e
.eq(0) # reset eeeeeverything
1615 comb
+= self
.do_copy("insn", self
.dec
.opcode_in
, True)
1616 comb
+= self
.do_copy("insn_type", MicrOp
.OP_FETCH_FAILED
, True)
1617 comb
+= self
.do_copy("fn_unit", Function
.MMU
, True)
1618 comb
+= self
.do_copy("cia", self
.state
.pc
, True) # PC
1619 comb
+= self
.do_copy("msr", self
.state
.msr
, True) # MSR
1620 # special override on internal_op, due to being a "fake" op
1621 comb
+= self
.dec
.op
.internal_op
.eq(MicrOp
.OP_FETCH_FAILED
)
1623 # LD/ST exceptions. TestIssuer copies the exception info at us
1624 # after a failed LD/ST.
1625 with m
.Elif(ldst_exc
.happened
):
1626 with m
.If(ldst_exc
.alignment
):
1627 self
.trap(m
, TT
.MEMEXC
, 0x600)
1628 with m
.Elif(ldst_exc
.instr_fault
):
1629 with m
.If(ldst_exc
.segment_fault
):
1630 self
.trap(m
, TT
.MEMEXC
, 0x480)
1632 # pass exception info to trap to create SRR1
1633 self
.trap(m
, TT
.MEMEXC
, 0x400, ldst_exc
)
1635 with m
.If(ldst_exc
.segment_fault
):
1636 self
.trap(m
, TT
.MEMEXC
, 0x380)
1638 self
.trap(m
, TT
.MEMEXC
, 0x300)
1640 # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
1641 with m
.Elif(dec_irq_ok
):
1642 self
.trap(m
, TT
.DEC
, 0x900) # v3.0B 6.5 p1065
1644 # external interrupt? only if MSR.EE set
1645 with m
.Elif(ext_irq_ok
):
1646 self
.trap(m
, TT
.EINT
, 0x500)
1648 # privileged instruction trap
1649 with m
.Elif(priv_ok
):
1650 self
.trap(m
, TT
.PRIV
, 0x700)
1652 # illegal instruction must redirect to trap. this is done by
1653 # *overwriting* the decoded instruction and starting again.
1654 # (note: the same goes for interrupts and for privileged operations,
1655 # just with different trapaddr and traptype)
1656 with m
.Elif(illeg_ok
):
1657 # illegal instruction trap
1658 self
.trap(m
, TT
.ILLEG
, 0x700)
1660 # no exception, just copy things to the output
1664 ####################
1665 # follow-up after trap/irq to set up SRR0/1
1667 # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
1668 # Note: OP_SC could actually be modified to just be a trap
1669 with m
.If((do_out
.insn_type
== MicrOp
.OP_TRAP
) |
1670 (do_out
.insn_type
== MicrOp
.OP_SC
)):
1671 # TRAP write fast1 = SRR0
1672 comb
+= e_out
.write_fast1
.data
.eq(FastRegsEnum
.SRR0
) # SRR0
1673 comb
+= e_out
.write_fast1
.ok
.eq(1)
1674 # TRAP write fast2 = SRR1
1675 comb
+= e_out
.write_fast2
.data
.eq(FastRegsEnum
.SRR1
) # SRR1
1676 comb
+= e_out
.write_fast2
.ok
.eq(1)
1677 # TRAP write fast2 = SRR1
1678 comb
+= e_out
.write_fast3
.data
.eq(FastRegsEnum
.SVSRR0
) # SVSRR0
1679 comb
+= e_out
.write_fast3
.ok
.eq(1)
1681 # RFID: needs to read SRR0/1
1682 with m
.If(do_out
.insn_type
== MicrOp
.OP_RFID
):
1683 # TRAP read fast1 = SRR0
1684 comb
+= e_out
.read_fast1
.data
.eq(FastRegsEnum
.SRR0
) # SRR0
1685 comb
+= e_out
.read_fast1
.ok
.eq(1)
1686 # TRAP read fast2 = SRR1
1687 comb
+= e_out
.read_fast2
.data
.eq(FastRegsEnum
.SRR1
) # SRR1
1688 comb
+= e_out
.read_fast2
.ok
.eq(1)
1689 # TRAP read fast2 = SVSRR0
1690 comb
+= e_out
.read_fast3
.data
.eq(FastRegsEnum
.SVSRR0
) # SVSRR0
1691 comb
+= e_out
.read_fast3
.ok
.eq(1)
1693 # annoying simulator bug.
1694 # asmcode may end up getting used for perfcounters?
1695 asmcode
= self
.op_get("asmcode")
1696 if hasattr(e_out
, "asmcode") and asmcode
is not None:
1697 comb
+= e_out
.asmcode
.eq(asmcode
)
1701 def trap(self
, m
, traptype
, trapaddr
, ldst_exc
=None):
1702 """trap: this basically "rewrites" the decoded instruction as a trap
1706 comb
+= e
.eq(0) # reset eeeeeverything
1709 comb
+= self
.do_copy("insn", self
.dec
.opcode_in
, True)
1710 comb
+= self
.do_copy("insn_type", MicrOp
.OP_TRAP
, True)
1711 comb
+= self
.do_copy("fn_unit", Function
.TRAP
, True)
1712 comb
+= self
.do_copy("trapaddr", trapaddr
>> 4, True) # bottom 4 bits
1713 comb
+= self
.do_copy("traptype", traptype
, True) # request type
1714 comb
+= self
.do_copy("ldst_exc", ldst_exc
, True) # request type
1715 comb
+= self
.do_copy("msr", self
.state
.msr
,
1716 True) # copy of MSR "state"
1717 comb
+= self
.do_copy("cia", self
.state
.pc
, True) # copy of PC "state"
1718 comb
+= self
.do_copy("svstate", self
.state
.svstate
, True) # SVSTATE
1721 def get_rdflags(m
, e
, cu
):
1722 """returns a sequential list of the read "ok" flags for a given FU.
1723 this list is in order of the CompUnit input specs
1726 for idx
in range(cu
.n_src
):
1727 regfile
, regname
, _
= cu
.get_in_spec(idx
)
1728 decinfo
= regspec_decode_read(m
, e
, regfile
, regname
)
1729 rdl
.append(decinfo
.okflag
)
1734 if __name__
== '__main__':
1735 pdecode
= create_pdecode()
1736 dec2
= PowerDecode2(pdecode
, svp64_en
=True)
1737 vl
= rtlil
.convert(dec2
, ports
=dec2
.ports() + pdecode
.ports())
1738 with
open("dec2.il", "w") as f
: