src/openpower/decoder/power_decoder2.py

   1 """Power ISA Decoder second stage
   2
   3 based on Anton Blanchard microwatt decode2.vhdl
   4
   5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
   6 over-riding the internal opcode when an exception is needed.
   7 """
   8
   9 from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl, Record
  10 from nmigen.cli import rtlil
  11 from nmutil.util import sel
  12
  13 from nmutil.picker import PriorityPicker
  14 from nmutil.iocontrol import RecordObject
  15 from nmutil.extend import exts
  16
  17 from openpower.exceptions import LDSTException
  18
  19 from openpower.decoder.power_svp64_prefix import SVP64PrefixDecoder
  20 from openpower.decoder.power_svp64_extra import SVP64CRExtra, SVP64RegExtra
  21 from openpower.decoder.power_svp64_rm import (SVP64RMModeDecode,
  22                                               sv_input_record_layout)
  23 from openpower.sv.svp64 import SVP64Rec
  24
  25 from openpower.decoder.power_regspec_map import regspec_decode_read
  26 from openpower.decoder.power_decoder import create_pdecode
  27 from openpower.decoder.power_enums import (MicrOp, CryIn, Function,
  28                                      CRInSel, CROutSel,
  29                                      LdstLen, In1Sel, In2Sel, In3Sel,
  30                                      OutSel, SPRfull, SPRreduced,
  31                                      RC, LDSTMode,
  32                                      SVEXTRA, SVEtype, SVPtype)
  33 from openpower.decoder.decode2execute1 import (Decode2ToExecute1Type, Data,
  34                                                Decode2ToOperand)
  35
  36 from openpower.consts import (MSR, SPEC, EXTRA2, EXTRA3, SVP64P, field,
  37                               SPEC_SIZE, SPECb, SPEC_AUG_SIZE, SVP64CROffs,
  38                               FastRegsEnum, XERRegsEnum, TT)
  39
  40 from openpower.state import CoreState
  41 from openpower.util import spr_to_fast
  42
  43
  44 def decode_spr_num(spr):
  45     return Cat(spr[5:10], spr[0:5])
  46
  47
  48 def instr_is_priv(m, op, insn):
  49     """determines if the instruction is privileged or not
  50     """
  51     comb = m.d.comb
  52     is_priv_insn = Signal(reset_less=True)
  53     with m.Switch(op):
  54         with m.Case(MicrOp.OP_ATTN, MicrOp.OP_MFMSR, MicrOp.OP_MTMSRD,
  55                     MicrOp.OP_MTMSR, MicrOp.OP_RFID):
  56             comb += is_priv_insn.eq(1)
  57         with m.Case(MicrOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
  58         with m.Case(MicrOp.OP_MFSPR, MicrOp.OP_MTSPR):
  59             with m.If(insn[20]):  # field XFX.spr[-1] i think
  60                 comb += is_priv_insn.eq(1)
  61     return is_priv_insn
  62
  63
  64 class SPRMap(Elaboratable):
  65     """SPRMap: maps POWER9 SPR numbers to internal enum values, fast and slow
  66     """
  67
  68     def __init__(self, regreduce_en):
  69         self.regreduce_en = regreduce_en
  70         if regreduce_en:
  71             SPR = SPRreduced
  72         else:
  73             SPR = SPRfull
  74
  75         self.spr_i = Signal(10, reset_less=True)
  76         self.spr_o = Data(SPR, name="spr_o")
  77         self.fast_o = Data(3, name="fast_o")
  78
  79     def elaborate(self, platform):
  80         m = Module()
  81         if self.regreduce_en:
  82             SPR = SPRreduced
  83         else:
  84             SPR = SPRfull
  85         with m.Switch(self.spr_i):
  86             for i, x in enumerate(SPR):
  87                 with m.Case(x.value):
  88                     m.d.comb += self.spr_o.data.eq(i)
  89                     m.d.comb += self.spr_o.ok.eq(1)
  90             for x, v in spr_to_fast.items():
  91                 with m.Case(x.value):
  92                     m.d.comb += self.fast_o.data.eq(v)
  93                     m.d.comb += self.fast_o.ok.eq(1)
  94         return m
  95
  96
  97 class DecodeA(Elaboratable):
  98     """DecodeA from instruction
  99
 100     decodes register RA, implicit and explicit CSRs
 101     """
 102
 103     def __init__(self, dec, regreduce_en):
 104         self.regreduce_en = regreduce_en
 105         if self.regreduce_en:
 106             SPR = SPRreduced
 107         else:
 108             SPR = SPRfull
 109         self.dec = dec
 110         self.sel_in = Signal(In1Sel, reset_less=True)
 111         self.insn_in = Signal(32, reset_less=True)
 112         self.reg_out = Data(5, name="reg_a")
 113         self.spr_out = Data(SPR, "spr_a")
 114         self.fast_out = Data(3, "fast_a")
 115         self.sv_nz = Signal(1)
 116
 117     def elaborate(self, platform):
 118         m = Module()
 119         comb = m.d.comb
 120         op = self.dec.op
 121         reg = self.reg_out
 122         m.submodules.sprmap = sprmap = SPRMap(self.regreduce_en)
 123
 124         # select Register A field, if *full 7 bits* are zero (2 more from SVP64)
 125         ra = Signal(5, reset_less=True)
 126         comb += ra.eq(self.dec.RA)
 127         with m.If((self.sel_in == In1Sel.RA) |
 128                   ((self.sel_in == In1Sel.RA_OR_ZERO) &
 129                    ((ra != Const(0, 5)) | (self.sv_nz != Const(0, 1))))):
 130             comb += reg.data.eq(ra)
 131             comb += reg.ok.eq(1)
 132
 133         # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
 134         # moved it to 1st position (in1_sel)... because
 135         rs = Signal(5, reset_less=True)
 136         comb += rs.eq(self.dec.RS)
 137         with m.If(self.sel_in == In1Sel.RS):
 138             comb += reg.data.eq(rs)
 139             comb += reg.ok.eq(1)
 140
 141         # select Register FRA field,
 142         fra = Signal(5, reset_less=True)
 143         comb += fra.eq(self.dec.FRA)
 144         with m.If(self.sel_in == In1Sel.FRA):
 145             comb += reg.data.eq(fra)
 146             comb += reg.ok.eq(1)
 147
 148         # select Register FRS field,
 149         frs = Signal(5, reset_less=True)
 150         comb += frs.eq(self.dec.FRS)
 151         with m.If(self.sel_in == In1Sel.FRS):
 152             comb += reg.data.eq(frs)
 153             comb += reg.ok.eq(1)
 154
 155         # decode Fast-SPR based on instruction type
 156         with m.Switch(op.internal_op):
 157
 158             # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
 159             with m.Case(MicrOp.OP_BC):
 160                 with m.If(~self.dec.BO[2]):  # 3.0B p38 BO2=0, use CTR reg
 161                     # constant: CTR
 162                     comb += self.fast_out.data.eq(FastRegsEnum.CTR)
 163                     comb += self.fast_out.ok.eq(1)
 164             with m.Case(MicrOp.OP_BCREG):
 165                 xo9 = self.dec.FormXL.XO[9]  # 3.0B p38 top bit of XO
 166                 xo5 = self.dec.FormXL.XO[5]  # 3.0B p38
 167                 with m.If(xo9 & ~xo5):
 168                     # constant: CTR
 169                     comb += self.fast_out.data.eq(FastRegsEnum.CTR)
 170                     comb += self.fast_out.ok.eq(1)
 171
 172             # MFSPR move from SPRs
 173             with m.Case(MicrOp.OP_MFSPR):
 174                 spr = Signal(10, reset_less=True)
 175                 comb += spr.eq(decode_spr_num(self.dec.SPR))  # from XFX
 176                 comb += sprmap.spr_i.eq(spr)
 177                 comb += self.spr_out.eq(sprmap.spr_o)
 178                 comb += self.fast_out.eq(sprmap.fast_o)
 179
 180         return m
 181
 182
 183 class DecodeAImm(Elaboratable):
 184     """DecodeA immediate from instruction
 185
 186     decodes register RA, whether immediate-zero, implicit and
 187     explicit CSRs.  SVP64 mode requires 2 extra bits
 188     """
 189
 190     def __init__(self, dec):
 191         self.dec = dec
 192         self.sel_in = Signal(In1Sel, reset_less=True)
 193         self.immz_out = Signal(reset_less=True)
 194         self.sv_nz = Signal(1) # EXTRA bits from SVP64
 195
 196     def elaborate(self, platform):
 197         m = Module()
 198         comb = m.d.comb
 199
 200         # zero immediate requested
 201         ra = Signal(5, reset_less=True)
 202         comb += ra.eq(self.dec.RA)
 203         with m.If((self.sel_in == In1Sel.RA_OR_ZERO) &
 204                     (ra == Const(0, 5)) &
 205                     (self.sv_nz == Const(0, 1))):
 206             comb += self.immz_out.eq(1)
 207
 208         return m
 209
 210
 211 class DecodeB(Elaboratable):
 212     """DecodeB from instruction
 213
 214     decodes register RB, different forms of immediate (signed, unsigned),
 215     and implicit SPRs.  register B is basically "lane 2" into the CompUnits.
 216     by industry-standard convention, "lane 2" is where fully-decoded
 217     immediates are muxed in.
 218     """
 219
 220     def __init__(self, dec):
 221         self.dec = dec
 222         self.sel_in = Signal(In2Sel, reset_less=True)
 223         self.insn_in = Signal(32, reset_less=True)
 224         self.reg_out = Data(7, "reg_b")
 225         self.reg_isvec = Signal(1, name="reg_b_isvec") # TODO: in reg_out
 226         self.fast_out = Data(3, "fast_b")
 227
 228     def elaborate(self, platform):
 229         m = Module()
 230         comb = m.d.comb
 231         op = self.dec.op
 232         reg = self.reg_out
 233
 234         # select Register B field
 235         with m.Switch(self.sel_in):
 236             with m.Case(In2Sel.FRB):
 237                 comb += reg.data.eq(self.dec.FRB)
 238                 comb += reg.ok.eq(1)
 239             with m.Case(In2Sel.RB):
 240                 comb += reg.data.eq(self.dec.RB)
 241                 comb += reg.ok.eq(1)
 242             with m.Case(In2Sel.RS):
 243                 # for M-Form shiftrot
 244                 comb += reg.data.eq(self.dec.RS)
 245                 comb += reg.ok.eq(1)
 246
 247         # decode SPR2 based on instruction type
 248         # BCREG implicitly uses LR or TAR for 2nd reg
 249         # CTR however is already in fast_spr1 *not* 2.
 250         with m.If(op.internal_op == MicrOp.OP_BCREG):
 251             xo9 = self.dec.FormXL.XO[9]  # 3.0B p38 top bit of XO
 252             xo5 = self.dec.FormXL.XO[5]  # 3.0B p38
 253             with m.If(~xo9):
 254                 comb += self.fast_out.data.eq(FastRegsEnum.LR)
 255                 comb += self.fast_out.ok.eq(1)
 256             with m.Elif(xo5):
 257                 comb += self.fast_out.data.eq(FastRegsEnum.TAR)
 258                 comb += self.fast_out.ok.eq(1)
 259
 260         return m
 261
 262
 263 class DecodeBImm(Elaboratable):
 264     """DecodeB immediate from instruction
 265     """
 266     def __init__(self, dec):
 267         self.dec = dec
 268         self.sel_in = Signal(In2Sel, reset_less=True)
 269         self.imm_out = Data(64, "imm_b")
 270
 271     def elaborate(self, platform):
 272         m = Module()
 273         comb = m.d.comb
 274
 275         # select Register B Immediate
 276         with m.Switch(self.sel_in):
 277             with m.Case(In2Sel.CONST_UI): # unsigned
 278                 comb += self.imm_out.data.eq(self.dec.UI)
 279                 comb += self.imm_out.ok.eq(1)
 280             with m.Case(In2Sel.CONST_SI):  # sign-extended 16-bit
 281                 si = Signal(16, reset_less=True)
 282                 comb += si.eq(self.dec.SI)
 283                 comb += self.imm_out.data.eq(exts(si, 16, 64))
 284                 comb += self.imm_out.ok.eq(1)
 285             with m.Case(In2Sel.CONST_SI_HI):  # sign-extended 16+16=32 bit
 286                 si_hi = Signal(32, reset_less=True)
 287                 comb += si_hi.eq(self.dec.SI << 16)
 288                 comb += self.imm_out.data.eq(exts(si_hi, 32, 64))
 289                 comb += self.imm_out.ok.eq(1)
 290             with m.Case(In2Sel.CONST_UI_HI): # unsigned
 291                 ui = Signal(16, reset_less=True)
 292                 comb += ui.eq(self.dec.UI)
 293                 comb += self.imm_out.data.eq(ui << 16)
 294                 comb += self.imm_out.ok.eq(1)
 295             with m.Case(In2Sel.CONST_LI): # sign-extend 24+2=26 bit
 296                 li = Signal(26, reset_less=True)
 297                 comb += li.eq(self.dec.LI << 2)
 298                 comb += self.imm_out.data.eq(exts(li, 26, 64))
 299                 comb += self.imm_out.ok.eq(1)
 300             with m.Case(In2Sel.CONST_BD): # sign-extend (14+2)=16 bit
 301                 bd = Signal(16, reset_less=True)
 302                 comb += bd.eq(self.dec.BD << 2)
 303                 comb += self.imm_out.data.eq(exts(bd, 16, 64))
 304                 comb += self.imm_out.ok.eq(1)
 305             with m.Case(In2Sel.CONST_DS): # sign-extended (14+2=16) bit
 306                 ds = Signal(16, reset_less=True)
 307                 comb += ds.eq(self.dec.DS << 2)
 308                 comb += self.imm_out.data.eq(exts(ds, 16, 64))
 309                 comb += self.imm_out.ok.eq(1)
 310             with m.Case(In2Sel.CONST_M1): # signed (-1)
 311                 comb += self.imm_out.data.eq(~Const(0, 64))  # all 1s
 312                 comb += self.imm_out.ok.eq(1)
 313             with m.Case(In2Sel.CONST_SH): # unsigned - for shift
 314                 comb += self.imm_out.data.eq(self.dec.sh)
 315                 comb += self.imm_out.ok.eq(1)
 316             with m.Case(In2Sel.CONST_SH32): # unsigned - for shift
 317                 comb += self.imm_out.data.eq(self.dec.SH32)
 318                 comb += self.imm_out.ok.eq(1)
 319
 320         return m
 321
 322
 323 class DecodeC(Elaboratable):
 324     """DecodeC from instruction
 325
 326     decodes register RC.  this is "lane 3" into some CompUnits (not many)
 327     """
 328
 329     def __init__(self, dec):
 330         self.dec = dec
 331         self.sel_in = Signal(In3Sel, reset_less=True)
 332         self.insn_in = Signal(32, reset_less=True)
 333         self.reg_out = Data(5, "reg_c")
 334
 335     def elaborate(self, platform):
 336         m = Module()
 337         comb = m.d.comb
 338         op = self.dec.op
 339         reg = self.reg_out
 340
 341         # select Register C field
 342         with m.Switch(self.sel_in):
 343             with m.Case(In3Sel.RB):
 344                 # for M-Form shiftrot
 345                 comb += reg.data.eq(self.dec.RB)
 346                 comb += reg.ok.eq(1)
 347             with m.Case(In3Sel.FRS):
 348                 comb += reg.data.eq(self.dec.FRS)
 349                 comb += reg.ok.eq(1)
 350             with m.Case(In3Sel.FRC):
 351                 comb += reg.data.eq(self.dec.FRC)
 352                 comb += reg.ok.eq(1)
 353             with m.Case(In3Sel.RS):
 354                 comb += reg.data.eq(self.dec.RS)
 355                 comb += reg.ok.eq(1)
 356
 357         return m
 358
 359
 360 class DecodeOut(Elaboratable):
 361     """DecodeOut from instruction
 362
 363     decodes output register RA, RT or SPR
 364     """
 365
 366     def __init__(self, dec, regreduce_en):
 367         self.regreduce_en = regreduce_en
 368         if self.regreduce_en:
 369             SPR = SPRreduced
 370         else:
 371             SPR = SPRfull
 372         self.dec = dec
 373         self.sel_in = Signal(OutSel, reset_less=True)
 374         self.insn_in = Signal(32, reset_less=True)
 375         self.reg_out = Data(5, "reg_o")
 376         self.spr_out = Data(SPR, "spr_o")
 377         self.fast_out = Data(3, "fast_o")
 378
 379     def elaborate(self, platform):
 380         m = Module()
 381         comb = m.d.comb
 382         m.submodules.sprmap = sprmap = SPRMap(self.regreduce_en)
 383         op = self.dec.op
 384         reg = self.reg_out
 385
 386         # select Register out field
 387         with m.Switch(self.sel_in):
 388             with m.Case(OutSel.FRT):
 389                 comb += reg.data.eq(self.dec.FRT)
 390                 comb += reg.ok.eq(1)
 391             with m.Case(OutSel.RT):
 392                 comb += reg.data.eq(self.dec.RT)
 393                 comb += reg.ok.eq(1)
 394             with m.Case(OutSel.RA):
 395                 comb += reg.data.eq(self.dec.RA)
 396                 comb += reg.ok.eq(1)
 397             with m.Case(OutSel.SPR):
 398                 spr = Signal(10, reset_less=True)
 399                 comb += spr.eq(decode_spr_num(self.dec.SPR))  # from XFX
 400                 # MFSPR move to SPRs - needs mapping
 401                 with m.If(op.internal_op == MicrOp.OP_MTSPR):
 402                     comb += sprmap.spr_i.eq(spr)
 403                     comb += self.spr_out.eq(sprmap.spr_o)
 404                     comb += self.fast_out.eq(sprmap.fast_o)
 405
 406         # determine Fast Reg
 407         with m.Switch(op.internal_op):
 408
 409             # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
 410             with m.Case(MicrOp.OP_BC, MicrOp.OP_BCREG):
 411                 with m.If(~self.dec.BO[2]):  # 3.0B p38 BO2=0, use CTR reg
 412                     # constant: CTR
 413                     comb += self.fast_out.data.eq(FastRegsEnum.CTR)
 414                     comb += self.fast_out.ok.eq(1)
 415
 416             # RFID 1st spr (fast)
 417             with m.Case(MicrOp.OP_RFID):
 418                 comb += self.fast_out.data.eq(FastRegsEnum.SRR0)  # SRR0
 419                 comb += self.fast_out.ok.eq(1)
 420
 421         return m
 422
 423
 424 class DecodeOut2(Elaboratable):
 425     """DecodeOut2 from instruction
 426
 427     decodes output registers (2nd one).  note that RA is *implicit* below,
 428     which now causes problems with SVP64
 429
 430     TODO: SVP64 is a little more complex, here.  svp64 allows extending
 431     by one more destination by having one more EXTRA field.  RA-as-src
 432     is not the same as RA-as-dest.  limited in that it's the same first
 433     5 bits (from the v3.0B opcode), but still kinda cool.  mostly used
 434     for operations that have src-as-dest: mostly this is LD/ST-with-update
 435     but there are others.
 436     """
 437
 438     def __init__(self, dec):
 439         self.dec = dec
 440         self.sel_in = Signal(OutSel, reset_less=True)
 441         self.lk = Signal(reset_less=True)
 442         self.insn_in = Signal(32, reset_less=True)
 443         self.reg_out = Data(5, "reg_o2")
 444         self.fast_out = Data(3, "fast_o2")
 445         self.fast_out3 = Data(3, "fast_o3")
 446
 447     def elaborate(self, platform):
 448         m = Module()
 449         comb = m.d.comb
 450         op = self.dec.op
 451         #m.submodules.svdec = svdec = SVP64RegExtra()
 452
 453         # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
 454         #reg = Signal(5, reset_less=True)
 455
 456         if hasattr(self.dec.op, "upd"):
 457             # update mode LD/ST uses read-reg A also as an output
 458             with m.If(self.dec.op.upd == LDSTMode.update):
 459                 comb += self.reg_out.data.eq(self.dec.RA)
 460                 comb += self.reg_out.ok.eq(1)
 461
 462         # B, BC or BCREG: potential implicit register (LR) output
 463         # these give bl, bcl, bclrl, etc.
 464         with m.Switch(op.internal_op):
 465
 466             # BC* implicit register (LR)
 467             with m.Case(MicrOp.OP_BC, MicrOp.OP_B, MicrOp.OP_BCREG):
 468                 with m.If(self.lk):  # "link" mode
 469                     comb += self.fast_out.data.eq(FastRegsEnum.LR)  # LR
 470                     comb += self.fast_out.ok.eq(1)
 471
 472             # RFID 2nd and 3rd spr (fast)
 473             with m.Case(MicrOp.OP_RFID):
 474                 comb += self.fast_out.data.eq(FastRegsEnum.SRR1)  # SRR1
 475                 comb += self.fast_out.ok.eq(1)
 476                 comb += self.fast_out3.data.eq(FastRegsEnum.SVSRR0) # SVSRR0
 477                 comb += self.fast_out3.ok.eq(1)
 478
 479         return m
 480
 481
 482 class DecodeRC(Elaboratable):
 483     """DecodeRc from instruction
 484
 485     decodes Record bit Rc
 486     """
 487
 488     def __init__(self, dec):
 489         self.dec = dec
 490         self.sel_in = Signal(RC, reset_less=True)
 491         self.insn_in = Signal(32, reset_less=True)
 492         self.rc_out = Data(1, "rc")
 493
 494     def elaborate(self, platform):
 495         m = Module()
 496         comb = m.d.comb
 497
 498         # select Record bit out field
 499         with m.Switch(self.sel_in):
 500             with m.Case(RC.RC):
 501                 comb += self.rc_out.data.eq(self.dec.Rc)
 502                 comb += self.rc_out.ok.eq(1)
 503             with m.Case(RC.ONE):
 504                 comb += self.rc_out.data.eq(1)
 505                 comb += self.rc_out.ok.eq(1)
 506             with m.Case(RC.NONE):
 507                 comb += self.rc_out.data.eq(0)
 508                 comb += self.rc_out.ok.eq(1)
 509
 510         return m
 511
 512
 513 class DecodeOE(Elaboratable):
 514     """DecodeOE from instruction
 515
 516     decodes OE field: uses RC decode detection which might not be good
 517
 518     -- For now, use "rc" in the decode table to decide whether oe exists.
 519     -- This is not entirely correct architecturally: For mulhd and
 520     -- mulhdu, the OE field is reserved. It remains to be seen what an
 521     -- actual POWER9 does if we set it on those instructions, for now we
 522     -- test that further down when assigning to the multiplier oe input.
 523     """
 524
 525     def __init__(self, dec):
 526         self.dec = dec
 527         self.sel_in = Signal(RC, reset_less=True)
 528         self.insn_in = Signal(32, reset_less=True)
 529         self.oe_out = Data(1, "oe")
 530
 531     def elaborate(self, platform):
 532         m = Module()
 533         comb = m.d.comb
 534         op = self.dec.op
 535
 536         with m.Switch(op.internal_op):
 537
 538             # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE
 539             # also rotate
 540             # XXX ARGH! ignoring OE causes incompatibility with microwatt
 541             # http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-August/000302.html
 542             with m.Case(MicrOp.OP_MUL_H64, MicrOp.OP_MUL_H32,
 543                         MicrOp.OP_EXTS, MicrOp.OP_CNTZ,
 544                         MicrOp.OP_SHL, MicrOp.OP_SHR, MicrOp.OP_RLC,
 545                         MicrOp.OP_LOAD, MicrOp.OP_STORE,
 546                         MicrOp.OP_RLCL, MicrOp.OP_RLCR,
 547                         MicrOp.OP_EXTSWSLI):
 548                 pass
 549
 550             # all other ops decode OE field
 551             with m.Default():
 552                 # select OE bit out field
 553                 with m.Switch(self.sel_in):
 554                     with m.Case(RC.RC):
 555                         comb += self.oe_out.data.eq(self.dec.OE)
 556                         comb += self.oe_out.ok.eq(1)
 557
 558         return m
 559
 560
 561 class DecodeCRIn(Elaboratable):
 562     """Decodes input CR from instruction
 563
 564     CR indices - insn fields - (not the data *in* the CR) require only 3
 565     bits because they refer to CR0-CR7
 566     """
 567
 568     def __init__(self, dec):
 569         self.dec = dec
 570         self.sel_in = Signal(CRInSel, reset_less=True)
 571         self.insn_in = Signal(32, reset_less=True)
 572         self.cr_bitfield = Data(3, "cr_bitfield")
 573         self.cr_bitfield_b = Data(3, "cr_bitfield_b")
 574         self.cr_bitfield_o = Data(3, "cr_bitfield_o")
 575         self.whole_reg = Data(8,  "cr_fxm")
 576         self.sv_override = Signal(2, reset_less=True) # do not do EXTRA spec
 577
 578     def elaborate(self, platform):
 579         m = Module()
 580         comb = m.d.comb
 581         op = self.dec.op
 582         m.submodules.ppick = ppick = PriorityPicker(8, reverse_i=True,
 583                                                        reverse_o=True)
 584
 585         # zero-initialisation
 586         comb += self.cr_bitfield.ok.eq(0)
 587         comb += self.cr_bitfield_b.ok.eq(0)
 588         comb += self.cr_bitfield_o.ok.eq(0)
 589         comb += self.whole_reg.ok.eq(0)
 590         comb += self.sv_override.eq(0)
 591
 592         # select the relevant CR bitfields
 593         with m.Switch(self.sel_in):
 594             with m.Case(CRInSel.NONE):
 595                 pass  # No bitfield activated
 596             with m.Case(CRInSel.CR0):
 597                 comb += self.cr_bitfield.data.eq(0) # CR0 (MSB0 numbering)
 598                 comb += self.cr_bitfield.ok.eq(1)
 599                 comb += self.sv_override.eq(1)
 600             with m.Case(CRInSel.CR1):
 601                 comb += self.cr_bitfield.data.eq(1) # CR1 (MSB0 numbering)
 602                 comb += self.cr_bitfield.ok.eq(1)
 603                 comb += self.sv_override.eq(2)
 604             with m.Case(CRInSel.BI):
 605                 comb += self.cr_bitfield.data.eq(self.dec.BI[2:5])
 606                 comb += self.cr_bitfield.ok.eq(1)
 607             with m.Case(CRInSel.BFA):
 608                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BFA)
 609                 comb += self.cr_bitfield.ok.eq(1)
 610             with m.Case(CRInSel.BA_BB):
 611                 comb += self.cr_bitfield.data.eq(self.dec.BA[2:5])
 612                 comb += self.cr_bitfield.ok.eq(1)
 613                 comb += self.cr_bitfield_b.data.eq(self.dec.BB[2:5])
 614                 comb += self.cr_bitfield_b.ok.eq(1)
 615                 comb += self.cr_bitfield_o.data.eq(self.dec.BT[2:5])
 616                 comb += self.cr_bitfield_o.ok.eq(1)
 617             with m.Case(CRInSel.BC):
 618                 comb += self.cr_bitfield.data.eq(self.dec.BC[2:5])
 619                 comb += self.cr_bitfield.ok.eq(1)
 620             with m.Case(CRInSel.WHOLE_REG):
 621                 comb += self.whole_reg.ok.eq(1)
 622                 move_one = Signal(reset_less=True)
 623                 comb += move_one.eq(self.insn_in[20]) # MSB0 bit 11
 624                 with m.If((op.internal_op == MicrOp.OP_MFCR) & move_one):
 625                     # must one-hot the FXM field
 626                     comb += ppick.i.eq(self.dec.FXM)
 627                     comb += self.whole_reg.data.eq(ppick.o)
 628                 with m.Else():
 629                     # otherwise use all of it
 630                     comb += self.whole_reg.data.eq(0xff)
 631
 632         return m
 633
 634
 635 class DecodeCROut(Elaboratable):
 636     """Decodes input CR from instruction
 637
 638     CR indices - insn fields - (not the data *in* the CR) require only 3
 639     bits because they refer to CR0-CR7
 640     """
 641
 642     def __init__(self, dec):
 643         self.dec = dec
 644         self.rc_in = Signal(reset_less=True)
 645         self.sel_in = Signal(CROutSel, reset_less=True)
 646         self.insn_in = Signal(32, reset_less=True)
 647         self.cr_bitfield = Data(3, "cr_bitfield")
 648         self.whole_reg = Data(8,  "cr_fxm")
 649         self.sv_override = Signal(2, reset_less=True) # do not do EXTRA spec
 650
 651     def elaborate(self, platform):
 652         m = Module()
 653         comb = m.d.comb
 654         op = self.dec.op
 655         m.submodules.ppick = ppick = PriorityPicker(8, reverse_i=True,
 656                                                        reverse_o=True)
 657
 658         comb += self.cr_bitfield.ok.eq(0)
 659         comb += self.whole_reg.ok.eq(0)
 660         comb += self.sv_override.eq(0)
 661
 662         # please note these MUST match (setting of cr_bitfield.ok) exactly
 663         # with write_cr0 below in PowerDecoder2.  the reason it's separated
 664         # is to avoid having duplicate copies of DecodeCROut in multiple
 665         # PowerDecoderSubsets.  register decoding should be a one-off in
 666         # PowerDecoder2.  see https://bugs.libre-soc.org/show_bug.cgi?id=606
 667
 668         with m.Switch(self.sel_in):
 669             with m.Case(CROutSel.NONE):
 670                 pass  # No bitfield activated
 671             with m.Case(CROutSel.CR0):
 672                 comb += self.cr_bitfield.data.eq(0) # CR0 (MSB0 numbering)
 673                 comb += self.cr_bitfield.ok.eq(self.rc_in)  # only when RC=1
 674                 comb += self.sv_override.eq(1)
 675             with m.Case(CROutSel.CR1):
 676                 comb += self.cr_bitfield.data.eq(1) # CR1 (MSB0 numbering)
 677                 comb += self.cr_bitfield.ok.eq(self.rc_in)  # only when RC=1
 678                 comb += self.sv_override.eq(2)
 679             with m.Case(CROutSel.BF):
 680                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BF)
 681                 comb += self.cr_bitfield.ok.eq(1)
 682             with m.Case(CROutSel.BT):
 683                 comb += self.cr_bitfield.data.eq(self.dec.FormXL.BT[2:5])
 684                 comb += self.cr_bitfield.ok.eq(1)
 685             with m.Case(CROutSel.WHOLE_REG):
 686                 comb += self.whole_reg.ok.eq(1)
 687                 move_one = Signal(reset_less=True)
 688                 comb += move_one.eq(self.insn_in[20])
 689                 with m.If((op.internal_op == MicrOp.OP_MTCRF)):
 690                     with m.If(move_one):
 691                         # must one-hot the FXM field
 692                         comb += ppick.i.eq(self.dec.FXM)
 693                         with m.If(ppick.en_o):
 694                             comb += self.whole_reg.data.eq(ppick.o)
 695                         with m.Else():
 696                             comb += self.whole_reg.data.eq(0b00000001) # CR7
 697                     with m.Else():
 698                         comb += self.whole_reg.data.eq(self.dec.FXM)
 699                 with m.Else():
 700                     # otherwise use all of it
 701                     comb += self.whole_reg.data.eq(0xff)
 702
 703         return m
 704
 705 # dictionary of Input Record field names that, if they exist,
 706 # will need a corresponding CSV Decoder file column (actually, PowerOp)
 707 # to be decoded (this includes the single bit names)
 708 record_names = {'insn_type': 'internal_op',
 709                 'fn_unit': 'function_unit',
 710                 'SV_Ptype': 'SV_Ptype',
 711                 'rc': 'rc_sel',
 712                 'oe': 'rc_sel',
 713                 'zero_a': 'in1_sel',
 714                 'imm_data': 'in2_sel',
 715                 'invert_in': 'inv_a',
 716                 'invert_out': 'inv_out',
 717                 'rc': 'cr_out',
 718                 'oe': 'cr_in',
 719                 'output_carry': 'cry_out',
 720                 'input_carry': 'cry_in',
 721                 'is_32bit': 'is_32b',
 722                 'is_signed': 'sgn',
 723                 'lk': 'lk',
 724                 'data_len': 'ldst_len',
 725                 'byte_reverse': 'br',
 726                 'sign_extend': 'sgn_ext',
 727                 'ldst_mode': 'upd',
 728                 }
 729
 730
 731 class PowerDecodeSubset(Elaboratable):
 732     """PowerDecodeSubset: dynamic subset decoder
 733
 734     only fields actually requested are copied over. hence, "subset" (duh).
 735     """
 736     def __init__(self, dec, opkls=None, fn_name=None, final=False, state=None,
 737                             svp64_en=True, regreduce_en=False):
 738
 739         self.svp64_en = svp64_en
 740         self.regreduce_en = regreduce_en
 741         if svp64_en:
 742             self.sv_rm = SVP64Rec(name="dec_svp64") # SVP64 RM field
 743             self.rm_dec = SVP64RMModeDecode("svp64_rm_dec")
 744             # set these to the predicate mask bits needed for the ALU
 745             self.pred_sm = Signal() # TODO expand to SIMD mask width
 746             self.pred_dm = Signal() # TODO expand to SIMD mask width
 747         self.sv_a_nz = Signal(1)
 748         self.final = final
 749         self.opkls = opkls
 750         self.fn_name = fn_name
 751         if opkls is None:
 752             opkls = Decode2ToOperand
 753         self.do = opkls(fn_name)
 754         col_subset = self.get_col_subset(self.do)
 755
 756         # only needed for "main" PowerDecode2
 757         if not self.final:
 758             self.e = Decode2ToExecute1Type(name=self.fn_name, do=self.do,
 759                                            regreduce_en=regreduce_en)
 760
 761         # create decoder if one not already given
 762         if dec is None:
 763             dec = create_pdecode(name=fn_name, col_subset=col_subset,
 764                                       row_subset=self.rowsubsetfn)
 765         self.dec = dec
 766
 767         # state information needed by the Decoder
 768         if state is None:
 769             state = CoreState("dec2")
 770         self.state = state
 771
 772     def get_col_subset(self, do):
 773         subset = { 'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
 774         for k, v in record_names.items():
 775             if hasattr(do, k):
 776                 subset.add(v)
 777         print ("get_col_subset", self.fn_name, do.fields, subset)
 778         return subset
 779
 780     def rowsubsetfn(self, opcode, row):
 781         """select per-Function-Unit subset of opcodes to be processed
 782
 783         normally this just looks at the "unit" column.  MMU is different
 784         in that it processes specific SPR set/get operations that the SPR
 785         pipeline should not.
 786         """
 787         return (row['unit'] == self.fn_name or
 788                 # sigh a dreadful hack: MTSPR and MFSPR need to be processed
 789                 # by the MMU pipeline so we direct those opcodes to MMU **AND**
 790                 # SPR pipelines, then selectively weed out the SPRs that should
 791                 # or should not not go to each pipeline, further down.
 792                 # really this should be done by modifying the CSV syntax
 793                 # to support multiple tasks (unit column multiple entries)
 794                 # see https://bugs.libre-soc.org/show_bug.cgi?id=310
 795                (self.fn_name == 'MMU' and row['unit'] == 'SPR' and
 796                 row['internal op'] in ['OP_MTSPR', 'OP_MFSPR'])
 797                 )
 798
 799     def ports(self):
 800         ports = self.dec.ports() + self.e.ports()
 801         if self.svp64_en:
 802             ports += self.sv_rm.ports()
 803         return ports
 804
 805     def needs_field(self, field, op_field):
 806         if self.final:
 807             do = self.do
 808         else:
 809             do = self.e_tmp.do
 810         return hasattr(do, field) and self.op_get(op_field) is not None
 811
 812     def do_get(self, field, final=False):
 813         if final or self.final:
 814             do = self.do
 815         else:
 816             do = self.e_tmp.do
 817         return getattr(do, field, None)
 818
 819     def do_copy(self, field, val, final=False):
 820         df = self.do_get(field, final)
 821         if df is not None and val is not None:
 822             return df.eq(val)
 823         return []
 824
 825     def op_get(self, op_field):
 826         return getattr(self.dec.op, op_field, None)
 827
 828     def elaborate(self, platform):
 829         if self.regreduce_en:
 830             SPR = SPRreduced
 831         else:
 832             SPR = SPRfull
 833         m = Module()
 834         comb = m.d.comb
 835         state = self.state
 836         op, do = self.dec.op, self.do
 837         msr, cia, svstate = state.msr, state.pc, state.svstate
 838         # fill in for a normal instruction (not an exception)
 839         # copy over if non-exception, non-privileged etc. is detected
 840         if not self.final:
 841             if self.fn_name is None:
 842                 name = "tmp"
 843             else:
 844                 name = self.fn_name + "tmp"
 845             self.e_tmp = Decode2ToExecute1Type(name=name, opkls=self.opkls,
 846                                            regreduce_en=self.regreduce_en)
 847
 848         # set up submodule decoders
 849         m.submodules.dec = self.dec
 850         m.submodules.dec_rc = self.dec_rc = dec_rc = DecodeRC(self.dec)
 851         m.submodules.dec_oe = dec_oe = DecodeOE(self.dec)
 852
 853         if self.svp64_en:
 854             # and SVP64 RM mode decoder
 855             m.submodules.sv_rm_dec = rm_dec = self.rm_dec
 856
 857         # copy instruction through...
 858         for i in [do.insn, dec_rc.insn_in, dec_oe.insn_in, ]:
 859             comb += i.eq(self.dec.opcode_in)
 860
 861         # ...and subdecoders' input fields
 862         comb += dec_rc.sel_in.eq(op.rc_sel)
 863         comb += dec_oe.sel_in.eq(op.rc_sel)  # XXX should be OE sel
 864
 865         # copy "state" over
 866         comb += self.do_copy("msr", msr)
 867         comb += self.do_copy("cia", cia)
 868         comb += self.do_copy("svstate", svstate)
 869
 870         # set up instruction type
 871         # no op: defaults to OP_ILLEGAL
 872         internal_op = self.op_get("internal_op")
 873         comb += self.do_copy("insn_type", internal_op)
 874
 875         # function unit for decoded instruction: requires minor redirect
 876         # for SPR set/get
 877         fn = self.op_get("function_unit")
 878         spr = Signal(10, reset_less=True)
 879         comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
 880
 881         # Microwatt doesn't implement the partition table
 882         # instead has PRTBL register (SPR) to point to process table
 883         is_spr_mv = Signal()
 884         is_mmu_spr = Signal()
 885         comb += is_spr_mv.eq((internal_op == MicrOp.OP_MTSPR) |
 886                              (internal_op == MicrOp.OP_MFSPR))
 887         comb += is_mmu_spr.eq((spr == SPR.DSISR.value) |
 888                               (spr == SPR.DAR.value) |
 889                               (spr == SPR.PRTBL.value) |
 890                               (spr == SPR.PIDR.value))
 891         # MMU must receive MMU SPRs
 892         with m.If(is_spr_mv & (fn == Function.SPR) & is_mmu_spr):
 893             comb += self.do_copy("fn_unit", Function.NONE)
 894             comb += self.do_copy("insn_type", MicrOp.OP_ILLEGAL)
 895         # SPR pipe must *not* receive MMU SPRs
 896         with m.Elif(is_spr_mv & (fn == Function.MMU) & ~is_mmu_spr):
 897             comb += self.do_copy("fn_unit", Function.NONE)
 898             comb += self.do_copy("insn_type", MicrOp.OP_ILLEGAL)
 899         # all others ok
 900         with m.Else():
 901             comb += self.do_copy("fn_unit", fn)
 902
 903         # immediates
 904         if self.needs_field("zero_a", "in1_sel"):
 905             m.submodules.dec_ai = dec_ai = DecodeAImm(self.dec)
 906             comb += dec_ai.sv_nz.eq(self.sv_a_nz)
 907             comb += dec_ai.sel_in.eq(op.in1_sel)
 908             comb += self.do_copy("zero_a", dec_ai.immz_out)  # RA==0 detected
 909         if self.needs_field("imm_data", "in2_sel"):
 910             m.submodules.dec_bi = dec_bi = DecodeBImm(self.dec)
 911             comb += dec_bi.sel_in.eq(op.in2_sel)
 912             comb += self.do_copy("imm_data", dec_bi.imm_out) # imm in RB
 913
 914         # rc and oe out
 915         comb += self.do_copy("rc", dec_rc.rc_out)
 916         comb += self.do_copy("oe", dec_oe.oe_out)
 917
 918         # CR in/out - note: these MUST match with what happens in
 919         # DecodeCROut!
 920         rc_out = self.dec_rc.rc_out.data
 921         with m.Switch(op.cr_out):
 922             with m.Case(CROutSel.CR0, CROutSel.CR1):
 923                 comb += self.do_copy("write_cr0", rc_out) # only when RC=1
 924             with m.Case(CROutSel.BF, CROutSel.BT):
 925                 comb += self.do_copy("write_cr0", 1)
 926
 927         comb += self.do_copy("input_cr", self.op_get("cr_in"))   # CR in
 928         comb += self.do_copy("output_cr", self.op_get("cr_out"))  # CR out
 929
 930         if self.svp64_en:
 931             # connect up SVP64 RM Mode decoding
 932             fn = self.op_get("function_unit")
 933             comb += rm_dec.fn_in.eq(fn) # decode needs to know if LD/ST type
 934             comb += rm_dec.ptype_in.eq(op.SV_Ptype) # Single/Twin predicated
 935             comb += rm_dec.rc_in.eq(rc_out) # Rc=1
 936             comb += rm_dec.rm_in.eq(self.sv_rm) # SVP64 RM mode
 937
 938         # decoded/selected instruction flags
 939         comb += self.do_copy("data_len", self.op_get("ldst_len"))
 940         comb += self.do_copy("invert_in", self.op_get("inv_a"))
 941         comb += self.do_copy("invert_out", self.op_get("inv_out"))
 942         comb += self.do_copy("input_carry", self.op_get("cry_in"))
 943         comb += self.do_copy("output_carry", self.op_get("cry_out"))
 944         comb += self.do_copy("is_32bit", self.op_get("is_32b"))
 945         comb += self.do_copy("is_signed", self.op_get("sgn"))
 946         lk = self.op_get("lk")
 947         if lk is not None:
 948             with m.If(lk):
 949                 comb += self.do_copy("lk", self.dec.LK)  # XXX TODO: accessor
 950
 951         comb += self.do_copy("byte_reverse", self.op_get("br"))
 952         comb += self.do_copy("sign_extend", self.op_get("sgn_ext"))
 953         comb += self.do_copy("ldst_mode", self.op_get("upd"))  # LD/ST mode
 954
 955         # copy over SVP64 input record fields (if they exist)
 956         if self.svp64_en:
 957             # TODO, really do we have to do these explicitly?? sigh
 958             #for (field, _) in sv_input_record_layout:
 959             #    comb += self.do_copy(field, self.rm_dec.op_get(field))
 960             comb += self.do_copy("sv_saturate", self.rm_dec.saturate)
 961             comb += self.do_copy("sv_Ptype", self.rm_dec.ptype_in)
 962             # these get set up based on incoming mask bits.  TODO:
 963             # pass in multiple bits (later, when SIMD backends are enabled)
 964             with m.If(self.rm_dec.pred_sz):
 965                 comb += self.do_copy("sv_pred_sz", ~self.pred_sm)
 966             with m.If(self.rm_dec.pred_dz):
 967                 comb += self.do_copy("sv_pred_dz", ~self.pred_dm)
 968
 969         return m
 970
 971
 972 class PowerDecode2(PowerDecodeSubset):
 973     """PowerDecode2: the main instruction decoder.
 974
 975     whilst PowerDecode is responsible for decoding the actual opcode, this
 976     module encapsulates further specialist, sparse information and
 977     expansion of fields that is inconvenient to have in the CSV files.
 978     for example: the encoding of the immediates, which are detected
 979     and expanded out to their full value from an annotated (enum)
 980     representation.
 981
 982     implicit register usage is also set up, here.  for example: OP_BC
 983     requires implicitly reading CTR, OP_RFID requires implicitly writing
 984     to SRR1 and so on.
 985
 986     in addition, PowerDecoder2 is responsible for detecting whether
 987     instructions are illegal (or privileged) or not, and instead of
 988     just leaving at that, *replacing* the instruction to execute with
 989     a suitable alternative (trap).
 990
 991     LDSTExceptions are done the cycle _after_ they're detected (after
 992     they come out of LDSTCompUnit).  basically despite the instruction
 993     being decoded, the results of the decode are completely ignored
 994     and "exception.happened" used to set the "actual" instruction to
 995     "OP_TRAP".  the LDSTException data structure gets filled in,
 996     in the CompTrapOpSubset and that's what it fills in SRR.
 997
 998     to make this work, TestIssuer must notice "exception.happened"
 999     after the (failed) LD/ST and copies the LDSTException info from
1000     the output, into here (PowerDecoder2).  without incrementing PC.
1001     """
1002
1003     def __init__(self, dec, opkls=None, fn_name=None, final=False,
1004                             state=None, svp64_en=True, regreduce_en=False):
1005         super().__init__(dec, opkls, fn_name, final, state, svp64_en,
1006                          regreduce_en=False)
1007         self.ldst_exc = LDSTException("dec2_exc")
1008
1009         if self.svp64_en:
1010             self.cr_out_isvec = Signal(1, name="cr_out_isvec")
1011             self.cr_in_isvec = Signal(1, name="cr_in_isvec")
1012             self.cr_in_b_isvec = Signal(1, name="cr_in_b_isvec")
1013             self.cr_in_o_isvec = Signal(1, name="cr_in_o_isvec")
1014             self.in1_isvec = Signal(1, name="reg_a_isvec")
1015             self.in2_isvec = Signal(1, name="reg_b_isvec")
1016             self.in3_isvec = Signal(1, name="reg_c_isvec")
1017             self.o_isvec = Signal(1, name="reg_o_isvec")
1018             self.o2_isvec = Signal(1, name="reg_o2_isvec")
1019             self.no_in_vec = Signal(1, name="no_in_vec") # no inputs vector
1020             self.no_out_vec = Signal(1, name="no_out_vec") # no outputs vector
1021             self.loop_continue = Signal(1, name="loop_continue")
1022         else:
1023             self.no_in_vec = Const(1, 1)
1024             self.no_out_vec = Const(1, 1)
1025             self.loop_continue = Const(0, 1)
1026
1027     def get_col_subset(self, opkls):
1028         subset = super().get_col_subset(opkls)
1029         subset.add("asmcode")
1030         subset.add("in1_sel")
1031         subset.add("in2_sel")
1032         subset.add("in3_sel")
1033         subset.add("out_sel")
1034         if self.svp64_en:
1035             subset.add("sv_in1")
1036             subset.add("sv_in2")
1037             subset.add("sv_in3")
1038             subset.add("sv_out")
1039             subset.add("sv_out2")
1040             subset.add("sv_cr_in")
1041             subset.add("sv_cr_out")
1042             subset.add("SV_Etype")
1043             subset.add("SV_Ptype")
1044             # from SVP64RMModeDecode
1045             for (field, _) in sv_input_record_layout:
1046                 subset.add(field)
1047         subset.add("lk")
1048         subset.add("internal_op")
1049         subset.add("form")
1050         return subset
1051
1052     def elaborate(self, platform):
1053         m = super().elaborate(platform)
1054         comb = m.d.comb
1055         state = self.state
1056         e_out, op, do_out = self.e, self.dec.op, self.e.do
1057         dec_spr, msr, cia, ext_irq = state.dec, state.msr, state.pc, state.eint
1058         rc_out = self.dec_rc.rc_out.data
1059         e = self.e_tmp
1060         do = e.do
1061
1062         # fill in for a normal instruction (not an exception)
1063         # copy over if non-exception, non-privileged etc. is detected
1064
1065         # set up submodule decoders
1066         m.submodules.dec_a = dec_a = DecodeA(self.dec, self.regreduce_en)
1067         m.submodules.dec_b = dec_b = DecodeB(self.dec)
1068         m.submodules.dec_c = dec_c = DecodeC(self.dec)
1069         m.submodules.dec_o = dec_o = DecodeOut(self.dec, self.regreduce_en)
1070         m.submodules.dec_o2 = dec_o2 = DecodeOut2(self.dec)
1071         m.submodules.dec_cr_in = self.dec_cr_in = DecodeCRIn(self.dec)
1072         m.submodules.dec_cr_out = self.dec_cr_out = DecodeCROut(self.dec)
1073         comb += dec_a.sv_nz.eq(self.sv_a_nz)
1074
1075         if self.svp64_en:
1076             # and SVP64 Extra decoders
1077             m.submodules.crout_svdec = crout_svdec = SVP64CRExtra()
1078             m.submodules.crin_svdec = crin_svdec = SVP64CRExtra()
1079             m.submodules.crin_svdec_b = crin_svdec_b = SVP64CRExtra()
1080             m.submodules.crin_svdec_o = crin_svdec_o = SVP64CRExtra()
1081             m.submodules.in1_svdec = in1_svdec = SVP64RegExtra()
1082             m.submodules.in2_svdec = in2_svdec = SVP64RegExtra()
1083             m.submodules.in3_svdec = in3_svdec = SVP64RegExtra()
1084             m.submodules.o_svdec = o_svdec = SVP64RegExtra()
1085             m.submodules.o2_svdec = o2_svdec = SVP64RegExtra()
1086
1087             # debug access to crout_svdec (used in get_pdecode_cr_out)
1088             self.crout_svdec = crout_svdec
1089
1090         # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
1091         reg = Signal(5, reset_less=True)
1092
1093         # copy instruction through...
1094         for i in [do.insn, dec_a.insn_in, dec_b.insn_in,
1095                   self.dec_cr_in.insn_in, self.dec_cr_out.insn_in,
1096                   dec_c.insn_in, dec_o.insn_in, dec_o2.insn_in]:
1097             comb += i.eq(self.dec.opcode_in)
1098
1099         # CR setup
1100         comb += self.dec_cr_in.sel_in.eq(op.cr_in)
1101         comb += self.dec_cr_out.sel_in.eq(op.cr_out)
1102         comb += self.dec_cr_out.rc_in.eq(rc_out)
1103
1104         # CR register info
1105         comb += self.do_copy("read_cr_whole", self.dec_cr_in.whole_reg)
1106         comb += self.do_copy("write_cr_whole", self.dec_cr_out.whole_reg)
1107
1108         # ...and subdecoders' input fields
1109         comb += dec_a.sel_in.eq(op.in1_sel)
1110         comb += dec_b.sel_in.eq(op.in2_sel)
1111         comb += dec_c.sel_in.eq(op.in3_sel)
1112         comb += dec_o.sel_in.eq(op.out_sel)
1113         comb += dec_o2.sel_in.eq(op.out_sel)
1114         if hasattr(do, "lk"):
1115             comb += dec_o2.lk.eq(do.lk)
1116
1117         if self.svp64_en:
1118             # now do the SVP64 munging.  op.SV_Etype and op.sv_in1 comes from
1119             # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
1120             # which in turn were auto-generated by sv_analysis.py
1121             extra = self.sv_rm.extra            # SVP64 extra bits 10:18
1122
1123             #######
1124             # CR out
1125             comb += crout_svdec.idx.eq(op.sv_cr_out)  # SVP64 CR out
1126             comb += self.cr_out_isvec.eq(crout_svdec.isvec)
1127
1128             #######
1129             # CR in - selection slightly different due to shared CR field sigh
1130             cr_a_idx = Signal(SVEXTRA)
1131             cr_b_idx = Signal(SVEXTRA)
1132
1133             # these change slightly, when decoding BA/BB.  really should have
1134             # their own separate CSV column: sv_cr_in1 and sv_cr_in2, but hey
1135             comb += cr_a_idx.eq(op.sv_cr_in)
1136             comb += cr_b_idx.eq(SVEXTRA.NONE)
1137             with m.If(op.sv_cr_in == SVEXTRA.Idx_1_2.value):
1138                 comb += cr_a_idx.eq(SVEXTRA.Idx1)
1139                 comb += cr_b_idx.eq(SVEXTRA.Idx2)
1140
1141             comb += self.cr_in_isvec.eq(crin_svdec.isvec)
1142             comb += self.cr_in_b_isvec.eq(crin_svdec_b.isvec)
1143             comb += self.cr_in_o_isvec.eq(crin_svdec_o.isvec)
1144
1145             # indices are slightly different, BA/BB mess sorted above
1146             comb += crin_svdec.idx.eq(cr_a_idx)       # SVP64 CR in A
1147             comb += crin_svdec_b.idx.eq(cr_b_idx)     # SVP64 CR in B
1148             comb += crin_svdec_o.idx.eq(op.sv_cr_out) # SVP64 CR out
1149
1150             # get SVSTATE srcstep (TODO: elwidth etc.) needed below
1151             srcstep = Signal.like(self.state.svstate.srcstep)
1152             dststep = Signal.like(self.state.svstate.dststep)
1153             comb += srcstep.eq(self.state.svstate.srcstep)
1154             comb += dststep.eq(self.state.svstate.dststep)
1155
1156             # registers a, b, c and out and out2 (LD/ST EA)
1157             for to_reg, fromreg, svdec, out in (
1158                 (e.read_reg1, dec_a.reg_out, in1_svdec, False),
1159                 (e.read_reg2, dec_b.reg_out, in2_svdec, False),
1160                 (e.read_reg3, dec_c.reg_out, in3_svdec, False),
1161                 (e.write_reg, dec_o.reg_out, o_svdec, True),
1162                 (e.write_ea, dec_o2.reg_out, o2_svdec, True)):
1163                 comb += svdec.extra.eq(extra)        # EXTRA field of SVP64 RM
1164                 comb += svdec.etype.eq(op.SV_Etype)  # EXTRA2/3 for this insn
1165                 comb += svdec.reg_in.eq(fromreg.data) # 3-bit (CR0/BC/BFA)
1166                 comb += to_reg.ok.eq(fromreg.ok)
1167                 # detect if Vectorised: add srcstep/dststep if yes.
1168                 # to_reg is 7-bits, outs get dststep added, ins get srcstep
1169                 with m.If(svdec.isvec):
1170                     step = dststep if out else srcstep
1171                     comb += to_reg.data.eq(step+svdec.reg_out)
1172                 with m.Else():
1173                     comb += to_reg.data.eq(svdec.reg_out)
1174
1175             comb += in1_svdec.idx.eq(op.sv_in1)  # SVP64 reg #1 (in1_sel)
1176             comb += in2_svdec.idx.eq(op.sv_in2)  # SVP64 reg #2 (in2_sel)
1177             comb += in3_svdec.idx.eq(op.sv_in3)  # SVP64 reg #3 (in3_sel)
1178             comb += o_svdec.idx.eq(op.sv_out)    # SVP64 output (out_sel)
1179             comb += o2_svdec.idx.eq(op.sv_out2)  # SVP64 output (implicit)
1180             # XXX TODO - work out where this should come from.  the problem is
1181             # that LD-with-update is implied (computed from "is instruction in
1182             # "update mode" rather than specified cleanly as its own CSV column
1183
1184             # output reg-is-vectorised (and when no in/out is vectorised)
1185             comb += self.in1_isvec.eq(in1_svdec.isvec)
1186             comb += self.in2_isvec.eq(in2_svdec.isvec)
1187             comb += self.in3_isvec.eq(in3_svdec.isvec)
1188             comb += self.o_isvec.eq(o_svdec.isvec)
1189             comb += self.o2_isvec.eq(o2_svdec.isvec)
1190             # TODO add SPRs here.  must be True when *all* are scalar
1191             l = map(lambda svdec: svdec.isvec, [in1_svdec, in2_svdec, in3_svdec,
1192                                         crin_svdec, crin_svdec_b, crin_svdec_o])
1193             comb += self.no_in_vec.eq(~Cat(*l).bool()) # all input scalar
1194             l = map(lambda svdec: svdec.isvec, [o2_svdec, o_svdec, crout_svdec])
1195             comb += self.no_out_vec.eq(~Cat(*l).bool()) # all output scalar
1196             # now create a general-purpose "test" as to whether looping
1197             # should continue.  this doesn't include predication bit-tests
1198             loop = self.loop_continue
1199             with m.Switch(op.SV_Ptype):
1200                 with m.Case(SVPtype.P2.value):
1201                     # twin-predication
1202                     # TODO: *and cache-inhibited LD/ST!*
1203                     comb += loop.eq(~(self.no_in_vec | self.no_out_vec))
1204                 with m.Case(SVPtype.P1.value):
1205                     # single-predication, test relies on dest only
1206                     comb += loop.eq(~self.no_out_vec)
1207                 with m.Default():
1208                     # not an SV operation, no looping
1209                     comb += loop.eq(0)
1210
1211             # condition registers (CR)
1212             for to_reg, cr, name, svdec, out in (
1213                 (e.read_cr1, self.dec_cr_in, "cr_bitfield", crin_svdec, 0),
1214                 (e.read_cr2, self.dec_cr_in, "cr_bitfield_b", crin_svdec_b, 0),
1215                 (e.read_cr3, self.dec_cr_in, "cr_bitfield_o", crin_svdec_o, 0),
1216                 (e.write_cr, self.dec_cr_out, "cr_bitfield", crout_svdec, 1)):
1217                 fromreg = getattr(cr, name)
1218                 comb += svdec.extra.eq(extra)        # EXTRA field of SVP64 RM
1219                 comb += svdec.etype.eq(op.SV_Etype)  # EXTRA2/3 for this insn
1220                 comb += svdec.cr_in.eq(fromreg.data) # 3-bit (CR0/BC/BFA)
1221                 with m.If(svdec.isvec):
1222                     # check if this is CR0 or CR1: treated differently
1223                     # (does not "listen" to EXTRA2/3 spec for a start)
1224                     # also: the CRs start from completely different locations
1225                     step = dststep if out else srcstep
1226                     with m.If(cr.sv_override == 1): # CR0
1227                         offs = SVP64CROffs.CR0
1228                         comb += to_reg.data.eq(step+offs)
1229                     with m.Elif(cr.sv_override == 2): # CR1
1230                         offs = SVP64CROffs.CR1
1231                         comb += to_reg.data.eq(step+1)
1232                     with m.Else():
1233                         comb += to_reg.data.eq(step+svdec.cr_out) # 7-bit out
1234                 with m.Else():
1235                     comb += to_reg.data.eq(svdec.cr_out) # 7-bit output
1236                 comb += to_reg.ok.eq(fromreg.ok)
1237
1238             # sigh must determine if RA is nonzero (7 bit)
1239             comb += self.sv_a_nz.eq(e.read_reg1.data != Const(0, 7))
1240         else:
1241             # connect up to/from read/write GPRs
1242             for to_reg, fromreg in ((e.read_reg1, dec_a.reg_out),
1243                                     (e.read_reg2, dec_b.reg_out),
1244                                     (e.read_reg3, dec_c.reg_out),
1245                                     (e.write_reg, dec_o.reg_out),
1246                                     (e.write_ea, dec_o2.reg_out)):
1247                 comb += to_reg.data.eq(fromreg.data)
1248                 comb += to_reg.ok.eq(fromreg.ok)
1249
1250             # connect up to/from read/write CRs
1251             for to_reg, cr, name in (
1252                         (e.read_cr1, self.dec_cr_in, "cr_bitfield", ),
1253                         (e.read_cr2, self.dec_cr_in, "cr_bitfield_b", ),
1254                         (e.read_cr3, self.dec_cr_in, "cr_bitfield_o", ),
1255                         (e.write_cr, self.dec_cr_out, "cr_bitfield", )):
1256                 fromreg = getattr(cr, name)
1257                 comb += to_reg.data.eq(fromreg.data)
1258                 comb += to_reg.ok.eq(fromreg.ok)
1259
1260         # SPRs out
1261         comb += e.read_spr1.eq(dec_a.spr_out)
1262         comb += e.write_spr.eq(dec_o.spr_out)
1263
1264         # Fast regs out including SRR0/1/SVSRR0
1265         comb += e.read_fast1.eq(dec_a.fast_out)
1266         comb += e.read_fast2.eq(dec_b.fast_out)
1267         comb += e.write_fast1.eq(dec_o.fast_out)   # SRR0 (OP_RFID)
1268         comb += e.write_fast2.eq(dec_o2.fast_out)  # SRR1 (ditto)
1269         comb += e.write_fast3.eq(dec_o2.fast_out3) # SVSRR0 (ditto)
1270
1271         # sigh this is exactly the sort of thing for which the
1272         # decoder is designed to not need.  MTSPR, MFSPR and others need
1273         # access to the XER bits.  however setting e.oe is not appropriate
1274         with m.If(op.internal_op == MicrOp.OP_MFSPR):
1275             comb += e.xer_in.eq(0b111) # SO, CA, OV
1276         with m.If(op.internal_op == MicrOp.OP_CMP):
1277             comb += e.xer_in.eq(1<<XERRegsEnum.SO) # SO
1278         with m.If(op.internal_op == MicrOp.OP_MTSPR):
1279             comb += e.xer_out.eq(1)
1280
1281         # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
1282         with m.If(op.internal_op == MicrOp.OP_TRAP):
1283             # *DO NOT* call self.trap here.  that would reset absolutely
1284             # everything including destroying read of RA and RB.
1285             comb += self.do_copy("trapaddr", 0x70) # strip first nibble
1286
1287         ####################
1288         # ok so the instruction's been decoded, blah blah, however
1289         # now we need to determine if it's actually going to go ahead...
1290         # *or* if in fact it's a privileged operation, whether there's
1291         # an external interrupt, etc. etc.  this is a simple priority
1292         # if-elif-elif sequence.  decrement takes highest priority,
1293         # EINT next highest, privileged operation third.
1294
1295         # check if instruction is privileged
1296         is_priv_insn = instr_is_priv(m, op.internal_op, e.do.insn)
1297
1298         # different IRQ conditions
1299         ext_irq_ok = Signal()
1300         dec_irq_ok = Signal()
1301         priv_ok = Signal()
1302         illeg_ok = Signal()
1303         ldst_exc = self.ldst_exc
1304
1305         comb += ext_irq_ok.eq(ext_irq & msr[MSR.EE]) # v3.0B p944 (MSR.EE)
1306         comb += dec_irq_ok.eq(dec_spr[63] & msr[MSR.EE]) # 6.5.11 p1076
1307         comb += priv_ok.eq(is_priv_insn & msr[MSR.PR])
1308         comb += illeg_ok.eq(op.internal_op == MicrOp.OP_ILLEGAL)
1309
1310         # LD/ST exceptions.  TestIssuer copies the exception info at us
1311         # after a failed LD/ST.
1312         with m.If(ldst_exc.happened):
1313             with m.If(ldst_exc.alignment):
1314                 self.trap(m, TT.PRIV, 0x600)
1315             with m.Elif(ldst_exc.instr_fault):
1316                 with m.If(ldst_exc.segment_fault):
1317                     self.trap(m, TT.PRIV, 0x480)
1318                 with m.Else():
1319                     # pass exception info to trap to create SRR1
1320                     self.trap(m, TT.MEMEXC, 0x400, ldst_exc)
1321             with m.Else():
1322                 with m.If(ldst_exc.segment_fault):
1323                     self.trap(m, TT.PRIV, 0x380)
1324                 with m.Else():
1325                     self.trap(m, TT.PRIV, 0x300)
1326
1327         # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
1328         with m.Elif(dec_irq_ok):
1329             self.trap(m, TT.DEC, 0x900)   # v3.0B 6.5 p1065
1330
1331         # external interrupt? only if MSR.EE set
1332         with m.Elif(ext_irq_ok):
1333             self.trap(m, TT.EINT, 0x500)
1334
1335         # privileged instruction trap
1336         with m.Elif(priv_ok):
1337             self.trap(m, TT.PRIV, 0x700)
1338
1339         # illegal instruction must redirect to trap. this is done by
1340         # *overwriting* the decoded instruction and starting again.
1341         # (note: the same goes for interrupts and for privileged operations,
1342         # just with different trapaddr and traptype)
1343         with m.Elif(illeg_ok):
1344             # illegal instruction trap
1345             self.trap(m, TT.ILLEG, 0x700)
1346
1347         # no exception, just copy things to the output
1348         with m.Else():
1349             comb += e_out.eq(e)
1350
1351         ####################
1352         # follow-up after trap/irq to set up SRR0/1
1353
1354         # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
1355         # Note: OP_SC could actually be modified to just be a trap
1356         with m.If((do_out.insn_type == MicrOp.OP_TRAP) |
1357                   (do_out.insn_type == MicrOp.OP_SC)):
1358             # TRAP write fast1 = SRR0
1359             comb += e_out.write_fast1.data.eq(FastRegsEnum.SRR0)  # SRR0
1360             comb += e_out.write_fast1.ok.eq(1)
1361             # TRAP write fast2 = SRR1
1362             comb += e_out.write_fast2.data.eq(FastRegsEnum.SRR1)  # SRR1
1363             comb += e_out.write_fast2.ok.eq(1)
1364             # TRAP write fast2 = SRR1
1365             comb += e_out.write_fast3.data.eq(FastRegsEnum.SVSRR0)  # SVSRR0
1366             comb += e_out.write_fast3.ok.eq(1)
1367
1368         # RFID: needs to read SRR0/1
1369         with m.If(do_out.insn_type == MicrOp.OP_RFID):
1370             # TRAP read fast1 = SRR0
1371             comb += e_out.read_fast1.data.eq(FastRegsEnum.SRR0)  # SRR0
1372             comb += e_out.read_fast1.ok.eq(1)
1373             # TRAP read fast2 = SRR1
1374             comb += e_out.read_fast2.data.eq(FastRegsEnum.SRR1)  # SRR1
1375             comb += e_out.read_fast2.ok.eq(1)
1376             # TRAP read fast2 = SVSRR0
1377             comb += e_out.read_fast3.data.eq(FastRegsEnum.SVSRR0)  # SVSRR0
1378             comb += e_out.read_fast3.ok.eq(1)
1379
1380         # annoying simulator bug
1381         if hasattr(e_out, "asmcode") and hasattr(self.dec.op, "asmcode"):
1382             comb += e_out.asmcode.eq(self.dec.op.asmcode)
1383
1384         return m
1385
1386     def trap(self, m, traptype, trapaddr, ldst_exc=None):
1387         """trap: this basically "rewrites" the decoded instruction as a trap
1388         """
1389         comb = m.d.comb
1390         op, e = self.dec.op, self.e
1391         comb += e.eq(0)  # reset eeeeeverything
1392
1393         # start again
1394         comb += self.do_copy("insn", self.dec.opcode_in, True)
1395         comb += self.do_copy("insn_type", MicrOp.OP_TRAP, True)
1396         comb += self.do_copy("fn_unit", Function.TRAP, True)
1397         comb += self.do_copy("trapaddr", trapaddr >> 4, True) # bottom 4 bits
1398         comb += self.do_copy("traptype", traptype, True)  # request type
1399         comb += self.do_copy("ldst_exc", ldst_exc, True)  # request type
1400         comb += self.do_copy("msr", self.state.msr, True) # copy of MSR "state"
1401         comb += self.do_copy("cia", self.state.pc, True)  # copy of PC "state"
1402         comb += self.do_copy("svstate", self.state.svstate, True)  # SVSTATE
1403
1404
1405
1406 def get_rdflags(e, cu):
1407     rdl = []
1408     for idx in range(cu.n_src):
1409         regfile, regname, _ = cu.get_in_spec(idx)
1410         rdflag, read = regspec_decode_read(e, regfile, regname)
1411         rdl.append(rdflag)
1412     print("rdflags", rdl)
1413     return Cat(*rdl)
1414
1415
1416 if __name__ == '__main__':
1417     pdecode = create_pdecode()
1418     dec2 = PowerDecode2(pdecode)
1419     vl = rtlil.convert(dec2, ports=dec2.ports() + pdecode.ports())
1420     with open("dec2.il", "w") as f:
1421         f.write(vl)