1 """Power ISA Decoder second stage
3 based on Anton Blanchard microwatt decode2.vhdl
5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
6 over-riding the internal opcode when an exception is needed.
9 from nmigen
import Module
, Elaboratable
, Signal
, Mux
, Const
, Cat
, Repl
, Record
10 from nmigen
.cli
import rtlil
11 from nmutil
.util
import sel
13 from nmutil
.picker
import PriorityPicker
14 from nmutil
.iocontrol
import RecordObject
15 from nmutil
.extend
import exts
17 from openpower
.exceptions
import LDSTException
19 from openpower
.decoder
.power_svp64_prefix
import SVP64PrefixDecoder
20 from openpower
.decoder
.power_svp64_extra
import SVP64CRExtra
, SVP64RegExtra
21 from openpower
.decoder
.power_svp64_rm
import (SVP64RMModeDecode
,
22 sv_input_record_layout
,
24 from openpower
.sv
.svp64
import SVP64Rec
26 from openpower
.decoder
.power_regspec_map
import regspec_decode_read
27 from openpower
.decoder
.power_decoder
import (create_pdecode
,
28 create_pdecode_svp64_ldst
,
30 from openpower
.decoder
.power_enums
import (MicrOp
, CryIn
, Function
,
32 LdstLen
, In1Sel
, In2Sel
, In3Sel
,
33 OutSel
, SPRfull
, SPRreduced
,
34 RCOE
, SVP64LDSTmode
, LDSTMode
,
35 SVEXTRA
, SVEtype
, SVPtype
)
36 from openpower
.decoder
.decode2execute1
import (Decode2ToExecute1Type
, Data
,
39 from openpower
.consts
import (MSR
, SPEC
, EXTRA2
, EXTRA3
, SVP64P
, field
,
40 SPEC_SIZE
, SPECb
, SPEC_AUG_SIZE
, SVP64CROffs
,
41 FastRegsEnum
, XERRegsEnum
, TT
)
43 from openpower
.state
import CoreState
44 from openpower
.util
import (spr_to_fast
, spr_to_state
, log
)
47 def decode_spr_num(spr
):
48 return Cat(spr
[5:10], spr
[0:5])
51 def instr_is_priv(m
, op
, insn
):
52 """determines if the instruction is privileged or not
55 is_priv_insn
= Signal(reset_less
=True)
57 with m
.Case(MicrOp
.OP_ATTN
, MicrOp
.OP_MFMSR
, MicrOp
.OP_MTMSRD
,
58 MicrOp
.OP_MTMSR
, MicrOp
.OP_RFID
):
59 comb
+= is_priv_insn
.eq(1)
60 with m
.Case(MicrOp
.OP_TLBIE
):
61 comb
+= is_priv_insn
.eq(1)
62 with m
.Case(MicrOp
.OP_MFSPR
, MicrOp
.OP_MTSPR
):
63 with m
.If(insn
[20]): # field XFX.spr[-1] i think
64 comb
+= is_priv_insn
.eq(1)
68 class SPRMap(Elaboratable
):
69 """SPRMap: maps POWER9 SPR numbers to internal enum values, fast and slow
72 def __init__(self
, regreduce_en
):
73 self
.regreduce_en
= regreduce_en
79 self
.spr_i
= Signal(10, reset_less
=True)
80 self
.spr_o
= Data(SPR
, name
="spr_o")
81 self
.fast_o
= Data(4, name
="fast_o")
82 self
.state_o
= Data(3, name
="state_o")
84 def elaborate(self
, platform
):
90 with m
.Switch(self
.spr_i
):
91 for i
, x
in enumerate(SPR
):
93 m
.d
.comb
+= self
.spr_o
.data
.eq(i
)
94 m
.d
.comb
+= self
.spr_o
.ok
.eq(1)
95 for x
, v
in spr_to_fast
.items():
97 m
.d
.comb
+= self
.fast_o
.data
.eq(v
)
98 m
.d
.comb
+= self
.fast_o
.ok
.eq(1)
99 for x
, v
in spr_to_state
.items():
100 with m
.Case(x
.value
):
101 m
.d
.comb
+= self
.state_o
.data
.eq(v
)
102 m
.d
.comb
+= self
.state_o
.ok
.eq(1)
106 class DecodeA(Elaboratable
):
107 """DecodeA from instruction
109 decodes register RA, implicit and explicit CSRs
112 def __init__(self
, dec
, op
, regreduce_en
):
113 self
.regreduce_en
= regreduce_en
114 if self
.regreduce_en
:
120 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
121 self
.insn_in
= Signal(32, reset_less
=True)
122 self
.reg_out
= Data(5, name
="reg_a")
123 self
.spr_out
= Data(SPR
, "spr_a")
124 self
.fast_out
= Data(4, "fast_a")
125 self
.state_out
= Data(3, "state_a")
126 self
.sv_nz
= Signal(1)
128 def elaborate(self
, platform
):
133 m
.submodules
.sprmap
= sprmap
= SPRMap(self
.regreduce_en
)
135 # select Register A field, if *full 7 bits* are zero (2 more from SVP64)
136 ra
= Signal(5, reset_less
=True)
137 comb
+= ra
.eq(self
.dec
.RA
)
138 with m
.If((self
.sel_in
== In1Sel
.RA
) |
139 ((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
140 ((ra
!= Const(0, 5)) |
(self
.sv_nz
!= Const(0, 1))))):
141 comb
+= reg
.data
.eq(ra
)
144 # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
145 # moved it to 1st position (in1_sel)... because
146 rs
= Signal(5, reset_less
=True)
147 comb
+= rs
.eq(self
.dec
.RS
)
148 with m
.If(self
.sel_in
== In1Sel
.RS
):
149 comb
+= reg
.data
.eq(rs
)
152 # select Register FRA field,
153 fra
= Signal(5, reset_less
=True)
154 comb
+= fra
.eq(self
.dec
.FRA
)
155 with m
.If(self
.sel_in
== In1Sel
.FRA
):
156 comb
+= reg
.data
.eq(fra
)
159 # select Register FRS field,
160 frs
= Signal(5, reset_less
=True)
161 comb
+= frs
.eq(self
.dec
.FRS
)
162 with m
.If(self
.sel_in
== In1Sel
.FRS
):
163 comb
+= reg
.data
.eq(frs
)
166 # decode Fast-SPR based on instruction type
167 with m
.Switch(op
.internal_op
):
169 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
170 with m
.Case(MicrOp
.OP_BC
):
171 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
173 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.CTR
)
174 comb
+= self
.fast_out
.ok
.eq(1)
175 with m
.Case(MicrOp
.OP_BCREG
):
176 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
177 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
178 with m
.If(xo9
& ~xo5
):
180 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.CTR
)
181 comb
+= self
.fast_out
.ok
.eq(1)
183 # MFSPR move from SPRs
184 with m
.Case(MicrOp
.OP_MFSPR
):
185 spr
= Signal(10, reset_less
=True)
186 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
187 comb
+= sprmap
.spr_i
.eq(spr
)
188 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
189 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
190 comb
+= self
.state_out
.eq(sprmap
.state_o
)
195 class DecodeAImm(Elaboratable
):
196 """DecodeA immediate from instruction
198 decodes register RA, whether immediate-zero, implicit and
199 explicit CSRs. SVP64 mode requires 2 extra bits
202 def __init__(self
, dec
):
204 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
205 self
.immz_out
= Signal(reset_less
=True)
206 self
.sv_nz
= Signal(1) # EXTRA bits from SVP64
208 def elaborate(self
, platform
):
212 # zero immediate requested
213 ra
= Signal(5, reset_less
=True)
214 comb
+= ra
.eq(self
.dec
.RA
)
215 with m
.If((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
216 (ra
== Const(0, 5)) &
217 (self
.sv_nz
== Const(0, 1))):
218 comb
+= self
.immz_out
.eq(1)
223 class DecodeB(Elaboratable
):
224 """DecodeB from instruction
226 decodes register RB, different forms of immediate (signed, unsigned),
227 and implicit SPRs. register B is basically "lane 2" into the CompUnits.
228 by industry-standard convention, "lane 2" is where fully-decoded
229 immediates are muxed in.
232 def __init__(self
, dec
, op
):
235 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
236 self
.insn_in
= Signal(32, reset_less
=True)
237 self
.reg_out
= Data(7, "reg_b")
238 self
.reg_isvec
= Signal(1, name
="reg_b_isvec") # TODO: in reg_out
239 self
.fast_out
= Data(4, "fast_b")
241 def elaborate(self
, platform
):
247 # select Register B field
248 with m
.Switch(self
.sel_in
):
249 with m
.Case(In2Sel
.FRB
):
250 comb
+= reg
.data
.eq(self
.dec
.FRB
)
252 with m
.Case(In2Sel
.RB
):
253 comb
+= reg
.data
.eq(self
.dec
.RB
)
255 with m
.Case(In2Sel
.RS
):
256 # for M-Form shiftrot
257 comb
+= reg
.data
.eq(self
.dec
.RS
)
260 # decode SPR2 based on instruction type
261 # BCREG implicitly uses LR or TAR for 2nd reg
262 # CTR however is already in fast_spr1 *not* 2.
263 with m
.If(op
.internal_op
== MicrOp
.OP_BCREG
):
264 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
265 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
267 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.LR
)
268 comb
+= self
.fast_out
.ok
.eq(1)
270 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.TAR
)
271 comb
+= self
.fast_out
.ok
.eq(1)
276 class DecodeBImm(Elaboratable
):
277 """DecodeB immediate from instruction
280 def __init__(self
, dec
):
282 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
283 self
.imm_out
= Data(64, "imm_b")
285 def elaborate(self
, platform
):
289 # select Register B Immediate
290 with m
.Switch(self
.sel_in
):
291 with m
.Case(In2Sel
.CONST_UI
): # unsigned
292 comb
+= self
.imm_out
.data
.eq(self
.dec
.UI
)
293 comb
+= self
.imm_out
.ok
.eq(1)
294 with m
.Case(In2Sel
.CONST_SI
): # sign-extended 16-bit
295 si
= Signal(16, reset_less
=True)
296 comb
+= si
.eq(self
.dec
.SI
)
297 comb
+= self
.imm_out
.data
.eq(exts(si
, 16, 64))
298 comb
+= self
.imm_out
.ok
.eq(1)
299 with m
.Case(In2Sel
.CONST_SI_HI
): # sign-extended 16+16=32 bit
300 si_hi
= Signal(32, reset_less
=True)
301 comb
+= si_hi
.eq(self
.dec
.SI
<< 16)
302 comb
+= self
.imm_out
.data
.eq(exts(si_hi
, 32, 64))
303 comb
+= self
.imm_out
.ok
.eq(1)
304 with m
.Case(In2Sel
.CONST_UI_HI
): # unsigned
305 ui
= Signal(16, reset_less
=True)
306 comb
+= ui
.eq(self
.dec
.UI
)
307 comb
+= self
.imm_out
.data
.eq(ui
<< 16)
308 comb
+= self
.imm_out
.ok
.eq(1)
309 with m
.Case(In2Sel
.CONST_LI
): # sign-extend 24+2=26 bit
310 li
= Signal(26, reset_less
=True)
311 comb
+= li
.eq(self
.dec
.LI
<< 2)
312 comb
+= self
.imm_out
.data
.eq(exts(li
, 26, 64))
313 comb
+= self
.imm_out
.ok
.eq(1)
314 with m
.Case(In2Sel
.CONST_BD
): # sign-extend (14+2)=16 bit
315 bd
= Signal(16, reset_less
=True)
316 comb
+= bd
.eq(self
.dec
.BD
<< 2)
317 comb
+= self
.imm_out
.data
.eq(exts(bd
, 16, 64))
318 comb
+= self
.imm_out
.ok
.eq(1)
319 with m
.Case(In2Sel
.CONST_DS
): # sign-extended (14+2=16) bit
320 ds
= Signal(16, reset_less
=True)
321 comb
+= ds
.eq(self
.dec
.DS
<< 2)
322 comb
+= self
.imm_out
.data
.eq(exts(ds
, 16, 64))
323 comb
+= self
.imm_out
.ok
.eq(1)
324 with m
.Case(In2Sel
.CONST_M1
): # signed (-1)
325 comb
+= self
.imm_out
.data
.eq(~
Const(0, 64)) # all 1s
326 comb
+= self
.imm_out
.ok
.eq(1)
327 with m
.Case(In2Sel
.CONST_SH
): # unsigned - for shift
328 comb
+= self
.imm_out
.data
.eq(self
.dec
.sh
)
329 comb
+= self
.imm_out
.ok
.eq(1)
330 with m
.Case(In2Sel
.CONST_SH32
): # unsigned - for shift
331 comb
+= self
.imm_out
.data
.eq(self
.dec
.SH32
)
332 comb
+= self
.imm_out
.ok
.eq(1)
333 with m
.Case(In2Sel
.CONST_XBI
): # unsigned - for grevi
334 comb
+= self
.imm_out
.data
.eq(self
.dec
.FormXB
.XBI
)
335 comb
+= self
.imm_out
.ok
.eq(1)
340 class DecodeC(Elaboratable
):
341 """DecodeC from instruction
343 decodes register RC. this is "lane 3" into some CompUnits (not many)
346 def __init__(self
, dec
, op
):
349 self
.sel_in
= Signal(In3Sel
, reset_less
=True)
350 self
.insn_in
= Signal(32, reset_less
=True)
351 self
.reg_out
= Data(5, "reg_c")
353 def elaborate(self
, platform
):
359 # select Register C field
360 with m
.Switch(self
.sel_in
):
361 with m
.Case(In3Sel
.RB
):
362 # for M-Form shiftrot
363 comb
+= reg
.data
.eq(self
.dec
.RB
)
365 with m
.Case(In3Sel
.FRS
):
366 comb
+= reg
.data
.eq(self
.dec
.FRS
)
368 with m
.Case(In3Sel
.FRC
):
369 comb
+= reg
.data
.eq(self
.dec
.FRC
)
371 with m
.Case(In3Sel
.RS
):
372 comb
+= reg
.data
.eq(self
.dec
.RS
)
374 with m
.Case(In3Sel
.RC
):
375 comb
+= reg
.data
.eq(self
.dec
.RC
)
377 with m
.Case(In3Sel
.RT
):
378 # for TLI-form ternlogi
379 comb
+= reg
.data
.eq(self
.dec
.RT
)
385 class DecodeOut(Elaboratable
):
386 """DecodeOut from instruction
388 decodes output register RA, RT, FRS, FRT, or SPR
391 def __init__(self
, dec
, op
, regreduce_en
):
392 self
.regreduce_en
= regreduce_en
393 if self
.regreduce_en
:
399 self
.sel_in
= Signal(OutSel
, reset_less
=True)
400 self
.insn_in
= Signal(32, reset_less
=True)
401 self
.reg_out
= Data(5, "reg_o")
402 self
.spr_out
= Data(SPR
, "spr_o")
403 self
.fast_out
= Data(4, "fast_o")
404 self
.state_out
= Data(3, "state_o")
406 def elaborate(self
, platform
):
409 m
.submodules
.sprmap
= sprmap
= SPRMap(self
.regreduce_en
)
413 # select Register out field
414 with m
.Switch(self
.sel_in
):
415 with m
.Case(OutSel
.FRS
):
416 comb
+= reg
.data
.eq(self
.dec
.FRS
)
418 with m
.Case(OutSel
.FRT
):
419 comb
+= reg
.data
.eq(self
.dec
.FRT
)
421 with m
.Case(OutSel
.RT
):
422 comb
+= reg
.data
.eq(self
.dec
.RT
)
424 with m
.Case(OutSel
.RA
):
425 comb
+= reg
.data
.eq(self
.dec
.RA
)
427 with m
.Case(OutSel
.SPR
):
428 spr
= Signal(10, reset_less
=True)
429 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
430 # MFSPR move to SPRs - needs mapping
431 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
432 comb
+= sprmap
.spr_i
.eq(spr
)
433 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
434 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
435 comb
+= self
.state_out
.eq(sprmap
.state_o
)
438 with m
.Switch(op
.internal_op
):
440 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
441 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_BCREG
):
442 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
444 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.CTR
)
445 comb
+= self
.fast_out
.ok
.eq(1)
447 # RFID 1st spr (fast)
448 with m
.Case(MicrOp
.OP_RFID
):
449 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.SRR0
) # SRR0
450 comb
+= self
.fast_out
.ok
.eq(1)
455 class DecodeOut2(Elaboratable
):
456 """DecodeOut2 from instruction
458 decodes output registers (2nd one). note that RA is *implicit* below,
459 which now causes problems with SVP64
461 TODO: SVP64 is a little more complex, here. svp64 allows extending
462 by one more destination by having one more EXTRA field. RA-as-src
463 is not the same as RA-as-dest. limited in that it's the same first
464 5 bits (from the v3.0B opcode), but still kinda cool. mostly used
465 for operations that have src-as-dest: mostly this is LD/ST-with-update
466 but there are others.
469 def __init__(self
, dec
, op
):
472 self
.sel_in
= Signal(OutSel
, reset_less
=True)
473 self
.svp64_fft_mode
= Signal(reset_less
=True) # SVP64 FFT mode
474 self
.lk
= Signal(reset_less
=True)
475 self
.insn_in
= Signal(32, reset_less
=True)
476 self
.reg_out
= Data(5, "reg_o2")
477 self
.fp_madd_en
= Signal(reset_less
=True) # FFT instruction detected
478 self
.fast_out
= Data(4, "fast_o2")
479 self
.fast_out3
= Data(4, "fast_o3")
481 def elaborate(self
, platform
):
485 #m.submodules.svdec = svdec = SVP64RegExtra()
487 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
488 #reg = Signal(5, reset_less=True)
490 if hasattr(op
, "upd"):
491 # update mode LD/ST uses read-reg A also as an output
492 with m
.If(op
.upd
== LDSTMode
.update
):
493 comb
+= self
.reg_out
.data
.eq(self
.dec
.RA
)
494 comb
+= self
.reg_out
.ok
.eq(1)
496 # B, BC or BCREG: potential implicit register (LR) output
497 # these give bl, bcl, bclrl, etc.
498 with m
.Switch(op
.internal_op
):
500 # BC* implicit register (LR)
501 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_B
, MicrOp
.OP_BCREG
):
502 with m
.If(self
.lk
): # "link" mode
503 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.LR
) # LR
504 comb
+= self
.fast_out
.ok
.eq(1)
506 # RFID 2nd and 3rd spr (fast)
507 with m
.Case(MicrOp
.OP_RFID
):
508 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.SRR1
) # SRR1
509 comb
+= self
.fast_out
.ok
.eq(1)
510 comb
+= self
.fast_out3
.data
.eq(FastRegsEnum
.SVSRR0
) # SVSRR0
511 comb
+= self
.fast_out3
.ok
.eq(1)
513 # SVP64 FFT mode, FP mul-add: 2nd output reg (FRS) same as FRT
514 # will be offset by VL in hardware
515 # with m.Case(MicrOp.OP_FP_MADD):
516 with m
.If(self
.svp64_fft_mode
):
517 comb
+= self
.reg_out
.data
.eq(self
.dec
.FRT
)
518 comb
+= self
.reg_out
.ok
.eq(1)
519 comb
+= self
.fp_madd_en
.eq(1)
524 class DecodeRC(Elaboratable
):
525 """DecodeRc from instruction
527 decodes Record bit Rc
530 def __init__(self
, dec
):
532 self
.sel_in
= Signal(RCOE
, reset_less
=True)
533 self
.insn_in
= Signal(32, reset_less
=True)
534 self
.rc_out
= Data(1, "rc")
536 def elaborate(self
, platform
):
540 # select Record bit out field
541 with m
.Switch(self
.sel_in
):
542 with m
.Case(RCOE
.RC
, RCOE
.RC_ONLY
):
543 comb
+= self
.rc_out
.data
.eq(self
.dec
.Rc
)
544 comb
+= self
.rc_out
.ok
.eq(1)
545 with m
.Case(RCOE
.ONE
):
546 comb
+= self
.rc_out
.data
.eq(1)
547 comb
+= self
.rc_out
.ok
.eq(1)
548 with m
.Case(RCOE
.NONE
):
549 comb
+= self
.rc_out
.data
.eq(0)
550 comb
+= self
.rc_out
.ok
.eq(1)
555 class DecodeOE(Elaboratable
):
556 """DecodeOE from instruction
558 decodes OE field: uses RC decode detection which has now been
559 updated to separate out RC_ONLY. all cases RC_ONLY are *NOT*
560 listening to the OE field, here.
563 def __init__(self
, dec
, op
):
566 self
.sel_in
= Signal(RCOE
, reset_less
=True)
567 self
.insn_in
= Signal(32, reset_less
=True)
568 self
.oe_out
= Data(1, "oe")
570 def elaborate(self
, platform
):
574 with m
.Switch(self
.sel_in
):
575 with m
.Case(RCOE
.RC
):
576 comb
+= self
.oe_out
.data
.eq(self
.dec
.OE
)
577 comb
+= self
.oe_out
.ok
.eq(1)
580 comb
+= self
.oe_out
.data
.eq(0)
581 comb
+= self
.oe_out
.ok
.eq(0)
586 class DecodeCRIn(Elaboratable
):
587 """Decodes input CR from instruction
589 CR indices - insn fields - (not the data *in* the CR) require only 3
590 bits because they refer to CR0-CR7
593 def __init__(self
, dec
, op
):
596 self
.sel_in
= Signal(CRInSel
, reset_less
=True)
597 self
.insn_in
= Signal(32, reset_less
=True)
598 self
.cr_bitfield
= Data(3, "cr_bitfield")
599 self
.cr_bitfield_b
= Data(3, "cr_bitfield_b")
600 self
.cr_bitfield_o
= Data(3, "cr_bitfield_o")
601 self
.whole_reg
= Data(8, "cr_fxm")
602 self
.sv_override
= Signal(2, reset_less
=True) # do not do EXTRA spec
604 def elaborate(self
, platform
):
608 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
611 # zero-initialisation
612 comb
+= self
.cr_bitfield
.ok
.eq(0)
613 comb
+= self
.cr_bitfield_b
.ok
.eq(0)
614 comb
+= self
.cr_bitfield_o
.ok
.eq(0)
615 comb
+= self
.whole_reg
.ok
.eq(0)
616 comb
+= self
.sv_override
.eq(0)
618 # select the relevant CR bitfields
619 with m
.Switch(self
.sel_in
):
620 with m
.Case(CRInSel
.NONE
):
621 pass # No bitfield activated
622 with m
.Case(CRInSel
.CR0
):
623 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
624 comb
+= self
.cr_bitfield
.ok
.eq(1)
625 comb
+= self
.sv_override
.eq(1)
626 with m
.Case(CRInSel
.CR1
):
627 comb
+= self
.cr_bitfield
.data
.eq(1) # CR1 (MSB0 numbering)
628 comb
+= self
.cr_bitfield
.ok
.eq(1)
629 comb
+= self
.sv_override
.eq(2)
630 with m
.Case(CRInSel
.BI
):
631 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BI
[2:5])
632 comb
+= self
.cr_bitfield
.ok
.eq(1)
633 with m
.Case(CRInSel
.BFA
):
634 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BFA
)
635 comb
+= self
.cr_bitfield
.ok
.eq(1)
636 with m
.Case(CRInSel
.BA_BB
):
637 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BA
[2:5])
638 comb
+= self
.cr_bitfield
.ok
.eq(1)
639 comb
+= self
.cr_bitfield_b
.data
.eq(self
.dec
.BB
[2:5])
640 comb
+= self
.cr_bitfield_b
.ok
.eq(1)
641 comb
+= self
.cr_bitfield_o
.data
.eq(self
.dec
.BT
[2:5])
642 comb
+= self
.cr_bitfield_o
.ok
.eq(1)
643 with m
.Case(CRInSel
.BC
):
644 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BC
[2:5])
645 comb
+= self
.cr_bitfield
.ok
.eq(1)
646 with m
.Case(CRInSel
.WHOLE_REG
):
647 comb
+= self
.whole_reg
.ok
.eq(1)
648 move_one
= Signal(reset_less
=True)
649 comb
+= move_one
.eq(self
.insn_in
[20]) # MSB0 bit 11
650 with m
.If((op
.internal_op
== MicrOp
.OP_MFCR
) & move_one
):
651 # must one-hot the FXM field
652 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
653 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
655 # otherwise use all of it
656 comb
+= self
.whole_reg
.data
.eq(0xff)
661 class DecodeCROut(Elaboratable
):
662 """Decodes input CR from instruction
664 CR indices - insn fields - (not the data *in* the CR) require only 3
665 bits because they refer to CR0-CR7
668 def __init__(self
, dec
, op
):
671 self
.rc_in
= Signal(reset_less
=True)
672 self
.sel_in
= Signal(CROutSel
, reset_less
=True)
673 self
.insn_in
= Signal(32, reset_less
=True)
674 self
.cr_bitfield
= Data(3, "cr_bitfield")
675 self
.whole_reg
= Data(8, "cr_fxm")
676 self
.sv_override
= Signal(2, reset_less
=True) # do not do EXTRA spec
678 def elaborate(self
, platform
):
682 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
685 comb
+= self
.cr_bitfield
.ok
.eq(0)
686 comb
+= self
.whole_reg
.ok
.eq(0)
687 comb
+= self
.sv_override
.eq(0)
689 # please note these MUST match (setting of cr_bitfield.ok) exactly
690 # with write_cr0 below in PowerDecoder2. the reason it's separated
691 # is to avoid having duplicate copies of DecodeCROut in multiple
692 # PowerDecoderSubsets. register decoding should be a one-off in
693 # PowerDecoder2. see https://bugs.libre-soc.org/show_bug.cgi?id=606
695 with m
.Switch(self
.sel_in
):
696 with m
.Case(CROutSel
.NONE
):
697 pass # No bitfield activated
698 with m
.Case(CROutSel
.CR0
):
699 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
700 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
701 comb
+= self
.sv_override
.eq(1)
702 with m
.Case(CROutSel
.CR1
):
703 comb
+= self
.cr_bitfield
.data
.eq(1) # CR1 (MSB0 numbering)
704 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
705 comb
+= self
.sv_override
.eq(2)
706 with m
.Case(CROutSel
.BF
):
707 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BF
)
708 comb
+= self
.cr_bitfield
.ok
.eq(1)
709 with m
.Case(CROutSel
.BT
):
710 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormXL
.BT
[2:5])
711 comb
+= self
.cr_bitfield
.ok
.eq(1)
712 with m
.Case(CROutSel
.WHOLE_REG
):
713 comb
+= self
.whole_reg
.ok
.eq(1)
714 move_one
= Signal(reset_less
=True)
715 comb
+= move_one
.eq(self
.insn_in
[20])
716 with m
.If((op
.internal_op
== MicrOp
.OP_MTCRF
)):
718 # must one-hot the FXM field
719 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
720 with m
.If(ppick
.en_o
):
721 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
723 comb
+= self
.whole_reg
.data
.eq(0b00000001) # CR7
725 comb
+= self
.whole_reg
.data
.eq(self
.dec
.FXM
)
727 # otherwise use all of it
728 comb
+= self
.whole_reg
.data
.eq(0xff)
733 # dictionary of Input Record field names that, if they exist,
734 # will need a corresponding CSV Decoder file column (actually, PowerOp)
735 # to be decoded (this includes the single bit names)
736 record_names
= {'insn_type': 'internal_op',
737 'fn_unit': 'function_unit',
738 'SV_Ptype': 'SV_Ptype',
742 'imm_data': 'in2_sel',
743 'invert_in': 'inv_a',
744 'invert_out': 'inv_out',
747 'output_carry': 'cry_out',
748 'input_carry': 'cry_in',
749 'is_32bit': 'is_32b',
752 'data_len': 'ldst_len',
754 'byte_reverse': 'br',
755 'sign_extend': 'sgn_ext',
760 class PowerDecodeSubset(Elaboratable
):
761 """PowerDecodeSubset: dynamic subset decoder
763 only fields actually requested are copied over. hence, "subset" (duh).
766 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False, state
=None,
767 svp64_en
=True, regreduce_en
=False):
769 self
.svp64_en
= svp64_en
770 self
.regreduce_en
= regreduce_en
772 self
.is_svp64_mode
= Signal() # mark decoding as SVP64 Mode
773 self
.use_svp64_fft
= Signal() # FFT Mode
774 self
.sv_rm
= SVP64Rec(name
="dec_svp64") # SVP64 RM field
775 self
.rm_dec
= SVP64RMModeDecode("svp64_rm_dec")
776 # set these to the predicate mask bits needed for the ALU
777 self
.pred_sm
= Signal() # TODO expand to SIMD mask width
778 self
.pred_dm
= Signal() # TODO expand to SIMD mask width
779 self
.sv_a_nz
= Signal(1)
782 self
.fn_name
= fn_name
784 opkls
= Decode2ToOperand
785 self
.do
= opkls(fn_name
)
787 col_subset
= self
.get_col_subset(self
.do
)
788 row_subset
= self
.rowsubsetfn
793 # "conditions" for Decoders, to enable some weird and wonderful
794 # alternatives. useful for PCR (Program Compatibility Register)
795 # amongst other things
798 # XXX NO 'SVP64FFT': self.use_svp64_fft,
803 # only needed for "main" PowerDecode2
805 self
.e
= Decode2ToExecute1Type(name
=self
.fn_name
, do
=self
.do
,
806 regreduce_en
=regreduce_en
)
808 # create decoder if one not already given
810 dec
= create_pdecode(name
=fn_name
, col_subset
=col_subset
,
811 row_subset
=row_subset
,
812 conditions
=conditions
)
815 # set up a copy of the PowerOp
816 self
.op
= PowerOp
.like(self
.dec
.op
)
818 # state information needed by the Decoder
820 state
= CoreState("dec2")
823 def get_col_subset(self
, do
):
824 subset
= {'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
825 for k
, v
in record_names
.items():
828 log("get_col_subset", self
.fn_name
, do
.fields
, subset
)
831 def rowsubsetfn(self
, opcode
, row
):
832 """select per-Function-Unit subset of opcodes to be processed
834 normally this just looks at the "unit" column. MMU is different
835 in that it processes specific SPR set/get operations that the SPR
838 return (row
['unit'] == self
.fn_name
or
839 # sigh a dreadful hack: MTSPR and MFSPR need to be processed
840 # by the MMU pipeline so we direct those opcodes to MMU **AND**
841 # SPR pipelines, then selectively weed out the SPRs that should
842 # or should not not go to each pipeline, further down.
843 # really this should be done by modifying the CSV syntax
844 # to support multiple tasks (unit column multiple entries)
845 # see https://bugs.libre-soc.org/show_bug.cgi?id=310
846 (self
.fn_name
== 'MMU' and row
['unit'] == 'SPR' and
847 row
['internal op'] in ['OP_MTSPR', 'OP_MFSPR']) or
848 # urrr... and the KAIVB SPR, which must also be redirected
849 # (to the TRAP pipeline)
850 # see https://bugs.libre-soc.org/show_bug.cgi?id=859
851 (self
.fn_name
== 'TRAP' and row
['unit'] == 'SPR' and
852 row
['internal op'] in ['OP_MTSPR', 'OP_MFSPR'])
856 ports
= self
.dec
.ports() + self
.e
.ports()
858 ports
+= self
.sv_rm
.ports()
859 ports
.append(self
.is_svp64_mode
)
860 ports
.append(self
.use_svp64_fft
)
863 def needs_field(self
, field
, op_field
):
868 return hasattr(do
, field
) and self
.op_get(op_field
) is not None
870 def do_get(self
, field
, final
=False):
871 if final
or self
.final
:
875 return getattr(do
, field
, None)
877 def do_copy(self
, field
, val
, final
=False):
878 df
= self
.do_get(field
, final
)
879 if df
is not None and val
is not None:
883 def op_get(self
, op_field
):
884 return getattr(self
.op
, op_field
, None)
886 def elaborate(self
, platform
):
887 if self
.regreduce_en
:
894 op
, do
= self
.dec
.op
, self
.do
895 msr
, cia
, svstate
= state
.msr
, state
.pc
, state
.svstate
896 # fill in for a normal instruction (not an exception)
897 # copy over if non-exception, non-privileged etc. is detected
899 if self
.fn_name
is None:
902 name
= self
.fn_name
+ "tmp"
903 self
.e_tmp
= Decode2ToExecute1Type(name
=name
, opkls
=self
.opkls
,
904 regreduce_en
=self
.regreduce_en
)
906 # set up submodule decoders
907 m
.submodules
.dec
= dec
= self
.dec
908 m
.submodules
.dec_rc
= self
.dec_rc
= dec_rc
= DecodeRC(self
.dec
)
909 m
.submodules
.dec_oe
= dec_oe
= DecodeOE(self
.dec
, op
)
912 # and SVP64 RM mode decoder
913 m
.submodules
.sv_rm_dec
= rm_dec
= self
.rm_dec
915 # copy op from decoder
916 comb
+= self
.op
.eq(self
.dec
.op
)
918 # copy instruction through...
919 for i
in [do
.insn
, dec_rc
.insn_in
, dec_oe
.insn_in
, ]:
920 comb
+= i
.eq(self
.dec
.opcode_in
)
922 # ...and subdecoders' input fields
923 comb
+= dec_rc
.sel_in
.eq(self
.op_get("rc_sel"))
924 comb
+= dec_oe
.sel_in
.eq(self
.op_get("rc_sel")) # XXX should be OE sel
927 comb
+= self
.do_copy("msr", msr
)
928 comb
+= self
.do_copy("cia", cia
)
929 comb
+= self
.do_copy("svstate", svstate
)
931 # set up instruction type
932 # no op: defaults to OP_ILLEGAL
933 internal_op
= self
.op_get("internal_op")
934 comb
+= self
.do_copy("insn_type", internal_op
)
936 # function unit for decoded instruction: requires minor redirect
938 fn
= self
.op_get("function_unit")
939 spr
= Signal(10, reset_less
=True)
940 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
942 # Microwatt doesn't implement the partition table
943 # instead has PRTBL register (SPR) to point to process table
944 # Kestrel has a KAIVB SPR to "rebase" exceptions. rebasing is normally
945 # done with Hypervisor Mode which is not implemented (yet)
947 is_mmu_spr
= Signal()
948 is_trap_spr
= Signal()
949 comb
+= is_spr_mv
.eq((internal_op
== MicrOp
.OP_MTSPR
) |
950 (internal_op
== MicrOp
.OP_MFSPR
))
951 comb
+= is_mmu_spr
.eq((spr
== SPR
.DSISR
.value
) |
952 (spr
== SPR
.DAR
.value
) |
953 (spr
== SPR
.PRTBL
.value
) |
954 (spr
== SPR
.PIDR
.value
))
955 comb
+= is_trap_spr
.eq((spr
== SPR
.KAIVB
.value
)
957 # MMU must receive MMU SPRs
958 with m
.If(is_spr_mv
& (fn
== Function
.SPR
) & is_mmu_spr
):
959 comb
+= self
.do_copy("fn_unit", Function
.MMU
)
960 comb
+= self
.do_copy("insn_type", internal_op
)
961 # TRAP must receive TRAP SPR KAIVB
962 with m
.If(is_spr_mv
& (fn
== Function
.SPR
) & is_trap_spr
):
963 comb
+= self
.do_copy("fn_unit", Function
.TRAP
)
964 comb
+= self
.do_copy("insn_type", internal_op
)
965 # SPR pipe must *not* receive MMU or TRAP SPRs
966 with m
.Elif(is_spr_mv
& ((fn
== Function
.MMU
) & ~is_mmu_spr
) &
967 ((fn
== Function
.TRAP
) & ~is_trap_spr
)):
968 comb
+= self
.do_copy("fn_unit", Function
.NONE
)
969 comb
+= self
.do_copy("insn_type", MicrOp
.OP_ILLEGAL
)
972 comb
+= self
.do_copy("fn_unit", fn
)
975 if self
.needs_field("zero_a", "in1_sel"):
976 m
.submodules
.dec_ai
= dec_ai
= DecodeAImm(self
.dec
)
977 comb
+= dec_ai
.sv_nz
.eq(self
.sv_a_nz
)
978 comb
+= dec_ai
.sel_in
.eq(self
.op_get("in1_sel"))
979 comb
+= self
.do_copy("zero_a", dec_ai
.immz_out
) # RA==0 detected
980 if self
.needs_field("imm_data", "in2_sel"):
981 m
.submodules
.dec_bi
= dec_bi
= DecodeBImm(self
.dec
)
982 comb
+= dec_bi
.sel_in
.eq(self
.op_get("in2_sel"))
983 comb
+= self
.do_copy("imm_data", dec_bi
.imm_out
) # imm in RB
986 comb
+= self
.do_copy("rc", dec_rc
.rc_out
)
988 # OE only enabled when SVP64 not active
989 with m
.If(~self
.is_svp64_mode
):
990 comb
+= self
.do_copy("oe", dec_oe
.oe_out
)
992 comb
+= self
.do_copy("oe", dec_oe
.oe_out
)
994 # CR in/out - note: these MUST match with what happens in
996 rc_out
= self
.dec_rc
.rc_out
.data
997 with m
.Switch(self
.op_get("cr_out")):
998 with m
.Case(CROutSel
.CR0
, CROutSel
.CR1
):
999 comb
+= self
.do_copy("write_cr0", rc_out
) # only when RC=1
1000 with m
.Case(CROutSel
.BF
, CROutSel
.BT
):
1001 comb
+= self
.do_copy("write_cr0", 1)
1003 comb
+= self
.do_copy("input_cr", self
.op_get("cr_in")) # CR in
1004 comb
+= self
.do_copy("output_cr", self
.op_get("cr_out")) # CR out
1007 # connect up SVP64 RM Mode decoding. however... we need a shorter
1008 # path, for the LDST bit-reverse detection. so perform partial
1009 # decode when SVP64 is detected. then, bit-reverse mode can be
1010 # quickly determined, and the Decoder result MUXed over to
1011 # the alternative decoder, svdecldst. what a mess... *sigh*
1012 sv_ptype
= self
.op_get("SV_Ptype")
1013 fn
= self
.op_get("function_unit")
1014 comb
+= rm_dec
.fn_in
.eq(fn
) # decode needs to know Fn type
1015 comb
+= rm_dec
.ptype_in
.eq(sv_ptype
) # Single/Twin predicated
1016 comb
+= rm_dec
.rc_in
.eq(rc_out
) # Rc=1
1017 comb
+= rm_dec
.rm_in
.eq(self
.sv_rm
) # SVP64 RM mode
1018 if self
.needs_field("imm_data", "in2_sel"):
1019 bzero
= dec_bi
.imm_out
.ok
& ~dec_bi
.imm_out
.data
.bool()
1020 comb
+= rm_dec
.ldst_imz_in
.eq(bzero
) # B immediate is zero
1022 # main PowerDecoder2 determines if different SVP64 modes enabled
1023 # detect if SVP64 FFT mode enabled (really bad hack),
1024 # exclude fcfids and others
1025 # XXX this is a REALLY bad hack, REALLY has to be done better.
1026 # likely with a sub-decoder.
1027 # what this ultimately does is enable the 2nd implicit register
1028 # (FRS) for SVP64-decoding. all of these instructions are
1029 # 3-in 2-out but there is not enough room either in the
1030 # opcode *or* EXTRA2/3 to specify a 5th operand.
1032 comb
+= major
.eq(self
.dec
.opcode_in
[26:32])
1034 comb
+= xo
.eq(self
.dec
.opcode_in
[1:11])
1035 comb
+= self
.use_svp64_fft
.eq((major
== 59) & xo
.matches(
1036 '-----00100', # ffmsubs
1037 '-----00101', # ffmadds
1038 '-----00110', # ffnmsubs
1039 '-----00111', # ffnmadds
1040 '1000001100', # ffadds
1041 '-----11011', # fdmadds
1044 # decoded/selected instruction flags
1045 comb
+= self
.do_copy("data_len", self
.op_get("ldst_len"))
1046 comb
+= self
.do_copy("invert_in", self
.op_get("inv_a"))
1047 comb
+= self
.do_copy("invert_out", self
.op_get("inv_out"))
1048 comb
+= self
.do_copy("input_carry", self
.op_get("cry_in"))
1049 comb
+= self
.do_copy("output_carry", self
.op_get("cry_out"))
1050 comb
+= self
.do_copy("is_32bit", self
.op_get("is_32b"))
1051 comb
+= self
.do_copy("is_signed", self
.op_get("sgn"))
1052 lk
= self
.op_get("lk")
1055 comb
+= self
.do_copy("lk", self
.dec
.LK
) # XXX TODO: accessor
1057 comb
+= self
.do_copy("byte_reverse", self
.op_get("br"))
1058 comb
+= self
.do_copy("sign_extend", self
.op_get("sgn_ext"))
1059 comb
+= self
.do_copy("ldst_mode", self
.op_get("upd")) # LD/ST mode
1060 comb
+= self
.do_copy("reserve", self
.op_get("rsrv")) # atomic
1062 # copy over SVP64 input record fields (if they exist)
1064 # TODO, really do we have to do these explicitly?? sigh
1065 # for (field, _) in sv_input_record_layout:
1066 # comb += self.do_copy(field, self.rm_dec.op_get(field))
1067 comb
+= self
.do_copy("sv_saturate", self
.rm_dec
.saturate
)
1068 comb
+= self
.do_copy("sv_Ptype", self
.rm_dec
.ptype_in
)
1069 comb
+= self
.do_copy("sv_ldstmode", self
.rm_dec
.ldstmode
)
1070 # these get set up based on incoming mask bits. TODO:
1071 # pass in multiple bits (later, when SIMD backends are enabled)
1072 with m
.If(self
.rm_dec
.pred_sz
):
1073 comb
+= self
.do_copy("sv_pred_sz", ~self
.pred_sm
)
1074 with m
.If(self
.rm_dec
.pred_dz
):
1075 comb
+= self
.do_copy("sv_pred_dz", ~self
.pred_dm
)
1080 class PowerDecode2(PowerDecodeSubset
):
1081 """PowerDecode2: the main instruction decoder.
1083 whilst PowerDecode is responsible for decoding the actual opcode, this
1084 module encapsulates further specialist, sparse information and
1085 expansion of fields that is inconvenient to have in the CSV files.
1086 for example: the encoding of the immediates, which are detected
1087 and expanded out to their full value from an annotated (enum)
1090 implicit register usage is also set up, here. for example: OP_BC
1091 requires implicitly reading CTR, OP_RFID requires implicitly writing
1094 in addition, PowerDecoder2 is responsible for detecting whether
1095 instructions are illegal (or privileged) or not, and instead of
1096 just leaving at that, *replacing* the instruction to execute with
1097 a suitable alternative (trap).
1099 LDSTExceptions are done the cycle _after_ they're detected (after
1100 they come out of LDSTCompUnit). basically despite the instruction
1101 being decoded, the results of the decode are completely ignored
1102 and "exception.happened" used to set the "actual" instruction to
1103 "OP_TRAP". the LDSTException data structure gets filled in,
1104 in the CompTrapOpSubset and that's what it fills in SRR.
1106 to make this work, TestIssuer must notice "exception.happened"
1107 after the (failed) LD/ST and copies the LDSTException info from
1108 the output, into here (PowerDecoder2). without incrementing PC.
1110 also instr_fault works the same way: the instruction is "rewritten"
1111 so that the "fake" op that gets created is OP_FETCH_FAILED
1114 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False,
1115 state
=None, svp64_en
=True, regreduce_en
=False):
1116 super().__init
__(dec
, opkls
, fn_name
, final
, state
, svp64_en
,
1118 self
.ldst_exc
= LDSTException("dec2_exc") # rewrites as OP_TRAP
1119 self
.instr_fault
= Signal() # rewrites instruction as OP_FETCH_FAILED
1122 self
.cr_out_isvec
= Signal(1, name
="cr_out_isvec")
1123 self
.cr_in_isvec
= Signal(1, name
="cr_in_isvec")
1124 self
.cr_in_b_isvec
= Signal(1, name
="cr_in_b_isvec")
1125 self
.cr_in_o_isvec
= Signal(1, name
="cr_in_o_isvec")
1126 self
.in1_isvec
= Signal(1, name
="reg_a_isvec")
1127 self
.in2_isvec
= Signal(1, name
="reg_b_isvec")
1128 self
.in3_isvec
= Signal(1, name
="reg_c_isvec")
1129 self
.o_isvec
= Signal(7, name
="reg_o_isvec")
1130 self
.o2_isvec
= Signal(7, name
="reg_o2_isvec")
1131 self
.in1_step
= Signal(7, name
="reg_a_step")
1132 self
.in2_step
= Signal(7, name
="reg_b_step")
1133 self
.in3_step
= Signal(7, name
="reg_c_step")
1134 self
.o_step
= Signal(7, name
="reg_o_step")
1135 self
.o2_step
= Signal(7, name
="reg_o2_step")
1136 self
.remap_active
= Signal(5, name
="remap_active") # per reg
1137 self
.no_in_vec
= Signal(1, name
="no_in_vec") # no inputs vector
1138 self
.no_out_vec
= Signal(1, name
="no_out_vec") # no outputs vector
1139 self
.loop_continue
= Signal(1, name
="loop_continue")
1141 self
.no_in_vec
= Const(1, 1)
1142 self
.no_out_vec
= Const(1, 1)
1143 self
.loop_continue
= Const(0, 1)
1145 def get_col_subset(self
, opkls
):
1146 subset
= super().get_col_subset(opkls
)
1147 subset
.add("asmcode")
1148 subset
.add("in1_sel")
1149 subset
.add("in2_sel")
1150 subset
.add("in3_sel")
1151 subset
.add("out_sel")
1153 subset
.add("sv_in1")
1154 subset
.add("sv_in2")
1155 subset
.add("sv_in3")
1156 subset
.add("sv_out")
1157 subset
.add("sv_out2")
1158 subset
.add("sv_cr_in")
1159 subset
.add("sv_cr_out")
1160 subset
.add("SV_Etype")
1161 subset
.add("SV_Ptype")
1162 # from SVP64RMModeDecode
1163 for (field
, _
) in sv_input_record_layout
:
1166 subset
.add("internal_op")
1170 def elaborate(self
, platform
):
1171 m
= super().elaborate(platform
)
1174 op
, e_out
, do_out
= self
.op
, self
.e
, self
.e
.do
1175 dec_spr
, msr
, cia
, ext_irq
= state
.dec
, state
.msr
, state
.pc
, state
.eint
1176 rc_out
= self
.dec_rc
.rc_out
.data
1180 # fill in for a normal instruction (not an exception)
1181 # copy over if non-exception, non-privileged etc. is detected
1183 # set up submodule decoders
1184 m
.submodules
.dec_a
= dec_a
= DecodeA(self
.dec
, op
, self
.regreduce_en
)
1185 m
.submodules
.dec_b
= dec_b
= DecodeB(self
.dec
, op
)
1186 m
.submodules
.dec_c
= dec_c
= DecodeC(self
.dec
, op
)
1187 m
.submodules
.dec_o
= dec_o
= DecodeOut(self
.dec
, op
, self
.regreduce_en
)
1188 m
.submodules
.dec_o2
= dec_o2
= DecodeOut2(self
.dec
, op
)
1189 m
.submodules
.dec_cr_in
= self
.dec_cr_in
= DecodeCRIn(self
.dec
, op
)
1190 m
.submodules
.dec_cr_out
= self
.dec_cr_out
= DecodeCROut(self
.dec
, op
)
1191 comb
+= dec_a
.sv_nz
.eq(self
.sv_a_nz
)
1194 # and SVP64 Extra decoders
1195 m
.submodules
.crout_svdec
= crout_svdec
= SVP64CRExtra()
1196 m
.submodules
.crin_svdec
= crin_svdec
= SVP64CRExtra()
1197 m
.submodules
.crin_svdec_b
= crin_svdec_b
= SVP64CRExtra()
1198 m
.submodules
.crin_svdec_o
= crin_svdec_o
= SVP64CRExtra()
1199 m
.submodules
.in1_svdec
= in1_svdec
= SVP64RegExtra()
1200 m
.submodules
.in2_svdec
= in2_svdec
= SVP64RegExtra()
1201 m
.submodules
.in3_svdec
= in3_svdec
= SVP64RegExtra()
1202 m
.submodules
.o_svdec
= o_svdec
= SVP64RegExtra()
1203 m
.submodules
.o2_svdec
= o2_svdec
= SVP64RegExtra()
1205 # debug access to cr svdec (used in get_pdecode_cr_in/out)
1206 self
.crout_svdec
= crout_svdec
1207 self
.crin_svdec
= crin_svdec
1209 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
1210 reg
= Signal(5, reset_less
=True)
1212 # copy instruction through...
1213 for i
in [do
.insn
, dec_a
.insn_in
, dec_b
.insn_in
,
1214 self
.dec_cr_in
.insn_in
, self
.dec_cr_out
.insn_in
,
1215 dec_c
.insn_in
, dec_o
.insn_in
, dec_o2
.insn_in
]:
1216 comb
+= i
.eq(self
.dec
.opcode_in
)
1219 comb
+= self
.dec_cr_in
.sel_in
.eq(self
.op_get("cr_in"))
1220 comb
+= self
.dec_cr_out
.sel_in
.eq(self
.op_get("cr_out"))
1221 comb
+= self
.dec_cr_out
.rc_in
.eq(rc_out
)
1224 comb
+= self
.do_copy("read_cr_whole", self
.dec_cr_in
.whole_reg
)
1225 comb
+= self
.do_copy("write_cr_whole", self
.dec_cr_out
.whole_reg
)
1227 # ...and subdecoders' input fields
1228 comb
+= dec_a
.sel_in
.eq(self
.op_get("in1_sel"))
1229 comb
+= dec_b
.sel_in
.eq(self
.op_get("in2_sel"))
1230 comb
+= dec_c
.sel_in
.eq(self
.op_get("in3_sel"))
1231 comb
+= dec_o
.sel_in
.eq(self
.op_get("out_sel"))
1232 comb
+= dec_o2
.sel_in
.eq(self
.op_get("out_sel"))
1234 comb
+= dec_o2
.svp64_fft_mode
.eq(self
.use_svp64_fft
)
1235 if hasattr(do
, "lk"):
1236 comb
+= dec_o2
.lk
.eq(do
.lk
)
1239 # now do the SVP64 munging. op.SV_Etype and op.sv_in1 comes from
1240 # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
1241 # which in turn were auto-generated by sv_analysis.py
1242 extra
= self
.sv_rm
.extra
# SVP64 extra bits 10:18
1247 comb
+= crout_svdec
.idx
.eq(self
.op_get("sv_cr_out"))
1248 comb
+= self
.cr_out_isvec
.eq(crout_svdec
.isvec
)
1251 # CR in - selection slightly different due to shared CR field sigh
1252 cr_a_idx
= Signal(SVEXTRA
)
1253 cr_b_idx
= Signal(SVEXTRA
)
1255 # these change slightly, when decoding BA/BB. really should have
1256 # their own separate CSV column: sv_cr_in1 and sv_cr_in2, but hey
1257 comb
+= cr_a_idx
.eq(self
.op_get("sv_cr_in"))
1258 comb
+= cr_b_idx
.eq(SVEXTRA
.NONE
)
1259 with m
.If(self
.op_get("sv_cr_in") == SVEXTRA
.Idx_1_2
.value
):
1260 comb
+= cr_a_idx
.eq(SVEXTRA
.Idx1
)
1261 comb
+= cr_b_idx
.eq(SVEXTRA
.Idx2
)
1263 comb
+= self
.cr_in_isvec
.eq(crin_svdec
.isvec
)
1264 comb
+= self
.cr_in_b_isvec
.eq(crin_svdec_b
.isvec
)
1265 comb
+= self
.cr_in_o_isvec
.eq(crin_svdec_o
.isvec
)
1267 # indices are slightly different, BA/BB mess sorted above
1268 comb
+= crin_svdec
.idx
.eq(cr_a_idx
) # SVP64 CR in A
1269 comb
+= crin_svdec_b
.idx
.eq(cr_b_idx
) # SVP64 CR in B
1271 comb
+= crin_svdec_o
.idx
.eq(self
.op_get("sv_cr_out"))
1273 # get SVSTATE srcstep (TODO: elwidth etc.) needed below
1274 vl
= Signal
.like(self
.state
.svstate
.vl
)
1275 subvl
= Signal
.like(self
.rm_dec
.rm_in
.subvl
)
1276 srcstep
= Signal
.like(self
.state
.svstate
.srcstep
)
1277 dststep
= Signal
.like(self
.state
.svstate
.dststep
)
1278 ssubstep
= Signal
.like(self
.state
.svstate
.ssubstep
)
1279 dsubstep
= Signal
.like(self
.state
.svstate
.ssubstep
)
1280 comb
+= vl
.eq(self
.state
.svstate
.vl
)
1281 comb
+= subvl
.eq(self
.rm_dec
.rm_in
.subvl
)
1282 comb
+= srcstep
.eq(self
.state
.svstate
.srcstep
)
1283 comb
+= dststep
.eq(self
.state
.svstate
.dststep
)
1284 comb
+= ssubstep
.eq(self
.state
.svstate
.ssubstep
)
1285 comb
+= dsubstep
.eq(self
.state
.svstate
.dsubstep
)
1287 in1_step
, in2_step
= self
.in1_step
, self
.in2_step
1288 in3_step
= self
.in3_step
1289 o_step
, o2_step
= self
.o_step
, self
.o2_step
1291 # multiply vl by subvl - note that this is only 7 bit!
1292 # when elwidth overrides get involved this will have to go up
1294 comb
+= vmax
.eq(vl
*(subvl
+1))
1296 # registers a, b, c and out and out2 (LD/ST EA)
1297 sv_etype
= self
.op_get("SV_Etype")
1298 for i
, stuff
in enumerate((
1299 ("RA", e
.read_reg1
, dec_a
.reg_out
, in1_svdec
, in1_step
, False),
1300 ("RB", e
.read_reg2
, dec_b
.reg_out
, in2_svdec
, in2_step
, False),
1301 ("RC", e
.read_reg3
, dec_c
.reg_out
, in3_svdec
, in3_step
, False),
1302 ("RT", e
.write_reg
, dec_o
.reg_out
, o_svdec
, o_step
, True),
1303 ("EA", e
.write_ea
, dec_o2
.reg_out
, o2_svdec
, o2_step
, True))):
1304 rname
, to_reg
, fromreg
, svdec
, remapstep
, out
= stuff
1305 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1306 comb
+= svdec
.etype
.eq(sv_etype
) # EXTRA2/3 for this insn
1307 comb
+= svdec
.reg_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1308 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1309 # *screaam* FFT mode needs an extra offset for RB
1310 # similar to FRS/FRT (below). all of this needs cleanup
1311 offs
= Signal(7, name
="offs_"+rname
, reset_less
=True)
1314 # when FFT sv.ffmadd detected, and REMAP not in use,
1315 # automagically add on an extra offset to RB.
1316 # however when REMAP is active, the FFT REMAP
1317 # schedule takes care of this offset.
1318 with m
.If(dec_o2
.reg_out
.ok
& dec_o2
.fp_madd_en
):
1319 with m
.If(~self
.remap_active
[i
]):
1320 with m
.If(svdec
.isvec
):
1321 comb
+= offs
.eq(vl
) # VL for Vectors
1322 # detect if Vectorised: add srcstep/dststep if yes.
1323 # to_reg is 7-bits, outs get dststep added, ins get srcstep
1324 with m
.If(svdec
.isvec
):
1325 selectstep
= dststep
if out
else srcstep
1326 subselect
= dsubstep
if out
else ssubstep
1327 step
= Signal(7, name
="step_%s" % rname
.lower())
1328 with m
.If(self
.remap_active
[i
]):
1329 comb
+= step
.eq((remapstep
*(subvl
+1))+subselect
)
1331 comb
+= step
.eq((selectstep
*(subvl
+1))+subselect
)
1332 # reverse gear goes the opposite way
1333 with m
.If(self
.rm_dec
.reverse_gear
):
1334 comb
+= to_reg
.data
.eq(offs
+svdec
.reg_out
+(vmax
-1-step
))
1336 comb
+= to_reg
.data
.eq(offs
+step
+svdec
.reg_out
)
1338 comb
+= to_reg
.data
.eq(offs
+svdec
.reg_out
)
1340 # SVP64 in/out fields
1341 comb
+= in1_svdec
.idx
.eq(self
.op_get("sv_in1")) # reg #1 (in1_sel)
1342 comb
+= in2_svdec
.idx
.eq(self
.op_get("sv_in2")) # reg #2 (in2_sel)
1343 comb
+= in3_svdec
.idx
.eq(self
.op_get("sv_in3")) # reg #3 (in3_sel)
1344 comb
+= o_svdec
.idx
.eq(self
.op_get("sv_out")) # output (out_sel)
1346 comb
+= o2_svdec
.idx
.eq(self
.op_get("sv_out2"))
1347 # XXX TODO - work out where this should come from. the problem is
1348 # that LD-with-update is implied (computed from "is instruction in
1349 # "update mode" rather than specified cleanly as its own CSV column
1351 # output reg-is-vectorised (and when no in/out is vectorised)
1352 comb
+= self
.in1_isvec
.eq(in1_svdec
.isvec
)
1353 comb
+= self
.in2_isvec
.eq(in2_svdec
.isvec
)
1354 comb
+= self
.in3_isvec
.eq(in3_svdec
.isvec
)
1355 comb
+= self
.o_isvec
.eq(o_svdec
.isvec
)
1356 comb
+= self
.o2_isvec
.eq(o2_svdec
.isvec
)
1358 # urrr... don't ask... the implicit register FRS in FFT mode
1359 # "tracks" FRT exactly except it's offset by VL. rather than
1360 # mess up the above with if-statements, override it here.
1361 # same trick is applied to FRA, above, but it's a lot cleaner, there
1362 with m
.If(dec_o2
.reg_out
.ok
& dec_o2
.fp_madd_en
):
1364 with m
.If(~self
.remap_active
[4]):
1365 with m
.If(o2_svdec
.isvec
):
1366 comb
+= offs
.eq(vl
) # VL for Vectors
1368 comb
+= offs
.eq(1) # add 1 if scalar
1369 svdec
= o_svdec
# yes take source as o_svdec...
1370 with m
.If(svdec
.isvec
):
1371 step
= Signal(7, name
="step_%s" % rname
.lower())
1372 with m
.If(self
.remap_active
[4]):
1373 comb
+= step
.eq(o2_step
)
1375 comb
+= step
.eq(dststep
)
1376 # reverse gear goes the opposite way
1377 with m
.If(self
.rm_dec
.reverse_gear
):
1378 roffs
= offs
+(vl
-1-step
)
1379 comb
+= to_reg
.data
.eq(roffs
+svdec
.reg_out
)
1381 comb
+= to_reg
.data
.eq(offs
+step
+svdec
.reg_out
)
1383 comb
+= to_reg
.data
.eq(offs
+svdec
.reg_out
)
1384 # ... but write to *second* output
1385 comb
+= self
.o2_isvec
.eq(svdec
.isvec
)
1386 comb
+= o2_svdec
.idx
.eq(self
.op_get("sv_out"))
1388 # TODO add SPRs here. must be True when *all* are scalar
1389 l
= map(lambda svdec
: svdec
.isvec
, [in1_svdec
, in2_svdec
, in3_svdec
,
1390 crin_svdec
, crin_svdec_b
,
1392 comb
+= self
.no_in_vec
.eq(~
Cat(*l
).bool()) # all input scalar
1393 l
= map(lambda svdec
: svdec
.isvec
, [
1394 o2_svdec
, o_svdec
, crout_svdec
])
1395 # in mapreduce mode, scalar out is *allowed*
1396 with m
.If(self
.rm_dec
.mode
== SVP64RMMode
.MAPREDUCE
.value
):
1397 comb
+= self
.no_out_vec
.eq(0)
1400 comb
+= self
.no_out_vec
.eq(~
Cat(*l
).bool())
1401 # now create a general-purpose "test" as to whether looping
1402 # should continue. this doesn't include predication bit-tests
1403 loop
= self
.loop_continue
1404 with m
.Switch(self
.op_get("SV_Ptype")):
1405 with m
.Case(SVPtype
.P2
.value
):
1407 # TODO: *and cache-inhibited LD/ST!*
1408 comb
+= loop
.eq(~
(self
.no_in_vec | self
.no_out_vec
))
1409 with m
.Case(SVPtype
.P1
.value
):
1410 # single-predication, test relies on dest only
1411 comb
+= loop
.eq(~self
.no_out_vec
)
1413 # not an SV operation, no looping
1416 # condition registers (CR)
1417 for to_reg
, cr
, name
, svdec
, out
in (
1418 (e
.read_cr1
, self
.dec_cr_in
, "cr_bitfield", crin_svdec
, 0),
1419 (e
.read_cr2
, self
.dec_cr_in
, "cr_bitfield_b", crin_svdec_b
, 0),
1420 (e
.read_cr3
, self
.dec_cr_in
, "cr_bitfield_o", crin_svdec_o
, 0),
1421 (e
.write_cr
, self
.dec_cr_out
, "cr_bitfield", crout_svdec
, 1)):
1422 fromreg
= getattr(cr
, name
)
1423 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1424 comb
+= svdec
.etype
.eq(sv_etype
) # EXTRA2/3 for this insn
1425 comb
+= svdec
.cr_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1426 with m
.If(svdec
.isvec
):
1427 # check if this is CR0 or CR1: treated differently
1428 # (does not "listen" to EXTRA2/3 spec for a start)
1429 # also: the CRs start from completely different locations
1430 step
= dststep
if out
else srcstep
1431 with m
.If(cr
.sv_override
== 1): # CR0
1432 offs
= SVP64CROffs
.CR0
1433 comb
+= to_reg
.data
.eq(step
+offs
)
1434 with m
.Elif(cr
.sv_override
== 2): # CR1
1435 offs
= SVP64CROffs
.CR1
1436 comb
+= to_reg
.data
.eq(step
+1)
1438 comb
+= to_reg
.data
.eq(step
+svdec
.cr_out
) # 7-bit out
1440 comb
+= to_reg
.data
.eq(svdec
.cr_out
) # 7-bit output
1441 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1443 # sigh must determine if RA is nonzero (7 bit)
1444 comb
+= self
.sv_a_nz
.eq(e
.read_reg1
.data
!= Const(0, 7))
1446 # connect up to/from read/write GPRs
1447 for to_reg
, fromreg
in ((e
.read_reg1
, dec_a
.reg_out
),
1448 (e
.read_reg2
, dec_b
.reg_out
),
1449 (e
.read_reg3
, dec_c
.reg_out
),
1450 (e
.write_reg
, dec_o
.reg_out
),
1451 (e
.write_ea
, dec_o2
.reg_out
)):
1452 comb
+= to_reg
.data
.eq(fromreg
.data
)
1453 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1455 # connect up to/from read/write CRs
1456 for to_reg
, cr
, name
in (
1457 (e
.read_cr1
, self
.dec_cr_in
, "cr_bitfield", ),
1458 (e
.read_cr2
, self
.dec_cr_in
, "cr_bitfield_b", ),
1459 (e
.read_cr3
, self
.dec_cr_in
, "cr_bitfield_o", ),
1460 (e
.write_cr
, self
.dec_cr_out
, "cr_bitfield", )):
1461 fromreg
= getattr(cr
, name
)
1462 comb
+= to_reg
.data
.eq(fromreg
.data
)
1463 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1466 comb
+= self
.rm_dec
.ldst_ra_vec
.eq(self
.in1_isvec
) # RA is vector
1469 comb
+= e
.read_spr1
.eq(dec_a
.spr_out
)
1470 comb
+= e
.write_spr
.eq(dec_o
.spr_out
)
1472 # Fast regs out including SRR0/1/SVSRR0
1473 comb
+= e
.read_fast1
.eq(dec_a
.fast_out
)
1474 comb
+= e
.read_fast2
.eq(dec_b
.fast_out
)
1475 comb
+= e
.write_fast1
.eq(dec_o
.fast_out
) # SRR0 (OP_RFID)
1476 comb
+= e
.write_fast2
.eq(dec_o2
.fast_out
) # SRR1 (ditto)
1477 comb
+= e
.write_fast3
.eq(dec_o2
.fast_out3
) # SVSRR0 (ditto)
1478 # and State regs (DEC, TB)
1479 comb
+= e
.read_state1
.eq(dec_a
.state_out
) # DEC/TB
1480 comb
+= e
.write_state1
.eq(dec_o
.state_out
) # DEC/TB
1482 # sigh this is exactly the sort of thing for which the
1483 # decoder is designed to not need. MTSPR, MFSPR and others need
1484 # access to the XER bits. however setting e.oe is not appropriate
1485 internal_op
= self
.op_get("internal_op")
1486 with m
.If(internal_op
== MicrOp
.OP_MFSPR
):
1487 comb
+= e
.xer_in
.eq(0b111) # SO, CA, OV
1488 with m
.If(internal_op
== MicrOp
.OP_CMP
):
1489 comb
+= e
.xer_in
.eq(1 << XERRegsEnum
.SO
) # SO
1490 with m
.If(internal_op
== MicrOp
.OP_MTSPR
):
1491 comb
+= e
.xer_out
.eq(1)
1493 # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
1494 with m
.If(op
.internal_op
== MicrOp
.OP_TRAP
):
1495 # *DO NOT* call self.trap here. that would reset absolutely
1496 # everything including destroying read of RA and RB.
1497 comb
+= self
.do_copy("trapaddr", 0x70) # strip first nibble
1499 ####################
1500 # ok so the instruction's been decoded, blah blah, however
1501 # now we need to determine if it's actually going to go ahead...
1502 # *or* if in fact it's a privileged operation, whether there's
1503 # an external interrupt, etc. etc. this is a simple priority
1504 # if-elif-elif sequence. decrement takes highest priority,
1505 # EINT next highest, privileged operation third.
1507 # check if instruction is privileged
1508 is_priv_insn
= instr_is_priv(m
, op
.internal_op
, e
.do
.insn
)
1510 # different IRQ conditions
1511 ext_irq_ok
= Signal()
1512 dec_irq_ok
= Signal()
1515 ldst_exc
= self
.ldst_exc
1517 comb
+= ext_irq_ok
.eq(ext_irq
& msr
[MSR
.EE
]) # v3.0B p944 (MSR.EE)
1518 comb
+= dec_irq_ok
.eq(dec_spr
[63] & msr
[MSR
.EE
]) # 6.5.11 p1076
1519 comb
+= priv_ok
.eq(is_priv_insn
& msr
[MSR
.PR
])
1520 comb
+= illeg_ok
.eq(op
.internal_op
== MicrOp
.OP_ILLEGAL
)
1522 # absolute top priority: check for an instruction failed
1523 with m
.If(self
.instr_fault
):
1524 comb
+= self
.e
.eq(0) # reset eeeeeverything
1525 comb
+= self
.do_copy("insn", self
.dec
.opcode_in
, True)
1526 comb
+= self
.do_copy("insn_type", MicrOp
.OP_FETCH_FAILED
, True)
1527 comb
+= self
.do_copy("fn_unit", Function
.MMU
, True)
1528 comb
+= self
.do_copy("cia", self
.state
.pc
, True) # PC
1529 comb
+= self
.do_copy("msr", self
.state
.msr
, True) # MSR
1530 # special override on internal_op, due to being a "fake" op
1531 comb
+= self
.dec
.op
.internal_op
.eq(MicrOp
.OP_FETCH_FAILED
)
1533 # LD/ST exceptions. TestIssuer copies the exception info at us
1534 # after a failed LD/ST.
1535 with m
.Elif(ldst_exc
.happened
):
1536 with m
.If(ldst_exc
.alignment
):
1537 self
.trap(m
, TT
.MEMEXC
, 0x600)
1538 with m
.Elif(ldst_exc
.instr_fault
):
1539 with m
.If(ldst_exc
.segment_fault
):
1540 self
.trap(m
, TT
.MEMEXC
, 0x480)
1542 # pass exception info to trap to create SRR1
1543 self
.trap(m
, TT
.MEMEXC
, 0x400, ldst_exc
)
1545 with m
.If(ldst_exc
.segment_fault
):
1546 self
.trap(m
, TT
.MEMEXC
, 0x380)
1548 self
.trap(m
, TT
.MEMEXC
, 0x300)
1550 # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
1551 with m
.Elif(dec_irq_ok
):
1552 self
.trap(m
, TT
.DEC
, 0x900) # v3.0B 6.5 p1065
1554 # external interrupt? only if MSR.EE set
1555 with m
.Elif(ext_irq_ok
):
1556 self
.trap(m
, TT
.EINT
, 0x500)
1558 # privileged instruction trap
1559 with m
.Elif(priv_ok
):
1560 self
.trap(m
, TT
.PRIV
, 0x700)
1562 # illegal instruction must redirect to trap. this is done by
1563 # *overwriting* the decoded instruction and starting again.
1564 # (note: the same goes for interrupts and for privileged operations,
1565 # just with different trapaddr and traptype)
1566 with m
.Elif(illeg_ok
):
1567 # illegal instruction trap
1568 self
.trap(m
, TT
.ILLEG
, 0x700)
1570 # no exception, just copy things to the output
1574 ####################
1575 # follow-up after trap/irq to set up SRR0/1
1577 # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
1578 # Note: OP_SC could actually be modified to just be a trap
1579 with m
.If((do_out
.insn_type
== MicrOp
.OP_TRAP
) |
1580 (do_out
.insn_type
== MicrOp
.OP_SC
)):
1581 # TRAP write fast1 = SRR0
1582 comb
+= e_out
.write_fast1
.data
.eq(FastRegsEnum
.SRR0
) # SRR0
1583 comb
+= e_out
.write_fast1
.ok
.eq(1)
1584 # TRAP write fast2 = SRR1
1585 comb
+= e_out
.write_fast2
.data
.eq(FastRegsEnum
.SRR1
) # SRR1
1586 comb
+= e_out
.write_fast2
.ok
.eq(1)
1587 # TRAP write fast2 = SRR1
1588 comb
+= e_out
.write_fast3
.data
.eq(FastRegsEnum
.SVSRR0
) # SVSRR0
1589 comb
+= e_out
.write_fast3
.ok
.eq(1)
1591 # RFID: needs to read SRR0/1
1592 with m
.If(do_out
.insn_type
== MicrOp
.OP_RFID
):
1593 # TRAP read fast1 = SRR0
1594 comb
+= e_out
.read_fast1
.data
.eq(FastRegsEnum
.SRR0
) # SRR0
1595 comb
+= e_out
.read_fast1
.ok
.eq(1)
1596 # TRAP read fast2 = SRR1
1597 comb
+= e_out
.read_fast2
.data
.eq(FastRegsEnum
.SRR1
) # SRR1
1598 comb
+= e_out
.read_fast2
.ok
.eq(1)
1599 # TRAP read fast2 = SVSRR0
1600 comb
+= e_out
.read_fast3
.data
.eq(FastRegsEnum
.SVSRR0
) # SVSRR0
1601 comb
+= e_out
.read_fast3
.ok
.eq(1)
1603 # annoying simulator bug.
1604 # asmcode may end up getting used for perfcounters?
1605 asmcode
= self
.op_get("asmcode")
1606 if hasattr(e_out
, "asmcode") and asmcode
is not None:
1607 comb
+= e_out
.asmcode
.eq(asmcode
)
1611 def trap(self
, m
, traptype
, trapaddr
, ldst_exc
=None):
1612 """trap: this basically "rewrites" the decoded instruction as a trap
1616 comb
+= e
.eq(0) # reset eeeeeverything
1619 comb
+= self
.do_copy("insn", self
.dec
.opcode_in
, True)
1620 comb
+= self
.do_copy("insn_type", MicrOp
.OP_TRAP
, True)
1621 comb
+= self
.do_copy("fn_unit", Function
.TRAP
, True)
1622 comb
+= self
.do_copy("trapaddr", trapaddr
>> 4, True) # bottom 4 bits
1623 comb
+= self
.do_copy("traptype", traptype
, True) # request type
1624 comb
+= self
.do_copy("ldst_exc", ldst_exc
, True) # request type
1625 comb
+= self
.do_copy("msr", self
.state
.msr
,
1626 True) # copy of MSR "state"
1627 comb
+= self
.do_copy("cia", self
.state
.pc
, True) # copy of PC "state"
1628 comb
+= self
.do_copy("svstate", self
.state
.svstate
, True) # SVSTATE
1631 def get_rdflags(m
, e
, cu
):
1632 """returns a sequential list of the read "ok" flags for a given FU.
1633 this list is in order of the CompUnit input specs
1636 for idx
in range(cu
.n_src
):
1637 regfile
, regname
, _
= cu
.get_in_spec(idx
)
1638 decinfo
= regspec_decode_read(m
, e
, regfile
, regname
)
1639 rdl
.append(decinfo
.okflag
)
1644 if __name__
== '__main__':
1645 pdecode
= create_pdecode()
1646 dec2
= PowerDecode2(pdecode
, svp64_en
=True)
1647 vl
= rtlil
.convert(dec2
, ports
=dec2
.ports() + pdecode
.ports())
1648 with
open("dec2.il", "w") as f
: