1 """Power ISA Decoder second stage
3 based on Anton Blanchard microwatt decode2.vhdl
5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
6 over-riding the internal opcode when an exception is needed.
9 from nmigen
import Module
, Elaboratable
, Signal
, Mux
, Const
, Cat
, Repl
, Record
10 from nmigen
.cli
import rtlil
11 from nmutil
.util
import sel
13 from nmutil
.picker
import PriorityPicker
14 from nmutil
.iocontrol
import RecordObject
15 from nmutil
.extend
import exts
17 from openpower
.exceptions
import LDSTException
19 from openpower
.decoder
.power_svp64_prefix
import SVP64PrefixDecoder
20 from openpower
.decoder
.power_svp64_extra
import SVP64CRExtra
, SVP64RegExtra
21 from openpower
.decoder
.power_svp64_rm
import (SVP64RMModeDecode
,
22 sv_input_record_layout
,
24 from openpower
.sv
.svp64
import SVP64Rec
26 from openpower
.decoder
.power_regspec_map
import regspec_decode_read
27 from openpower
.decoder
.power_decoder
import (create_pdecode
,
28 create_pdecode_svp64_ldst
,
30 from openpower
.decoder
.power_enums
import (MicrOp
, CryIn
, Function
,
32 LdstLen
, In1Sel
, In2Sel
, In3Sel
,
33 OutSel
, SPRfull
, SPRreduced
,
34 RC
, SVP64LDSTmode
, LDSTMode
,
35 SVEXTRA
, SVEtype
, SVPtype
)
36 from openpower
.decoder
.decode2execute1
import (Decode2ToExecute1Type
, Data
,
39 from openpower
.consts
import (MSR
, SPEC
, EXTRA2
, EXTRA3
, SVP64P
, field
,
40 SPEC_SIZE
, SPECb
, SPEC_AUG_SIZE
, SVP64CROffs
,
41 FastRegsEnum
, XERRegsEnum
, TT
)
43 from openpower
.state
import CoreState
44 from openpower
.util
import (spr_to_fast
, spr_to_state
, log
)
47 def decode_spr_num(spr
):
48 return Cat(spr
[5:10], spr
[0:5])
51 def instr_is_priv(m
, op
, insn
):
52 """determines if the instruction is privileged or not
55 is_priv_insn
= Signal(reset_less
=True)
57 with m
.Case(MicrOp
.OP_ATTN
, MicrOp
.OP_MFMSR
, MicrOp
.OP_MTMSRD
,
58 MicrOp
.OP_MTMSR
, MicrOp
.OP_RFID
):
59 comb
+= is_priv_insn
.eq(1)
60 with m
.Case(MicrOp
.OP_TLBIE
):
61 comb
+= is_priv_insn
.eq(1)
62 with m
.Case(MicrOp
.OP_MFSPR
, MicrOp
.OP_MTSPR
):
63 with m
.If(insn
[20]): # field XFX.spr[-1] i think
64 comb
+= is_priv_insn
.eq(1)
68 class SPRMap(Elaboratable
):
69 """SPRMap: maps POWER9 SPR numbers to internal enum values, fast and slow
72 def __init__(self
, regreduce_en
):
73 self
.regreduce_en
= regreduce_en
79 self
.spr_i
= Signal(10, reset_less
=True)
80 self
.spr_o
= Data(SPR
, name
="spr_o")
81 self
.fast_o
= Data(4, name
="fast_o")
82 self
.state_o
= Data(3, name
="state_o")
84 def elaborate(self
, platform
):
90 with m
.Switch(self
.spr_i
):
91 for i
, x
in enumerate(SPR
):
93 m
.d
.comb
+= self
.spr_o
.data
.eq(i
)
94 m
.d
.comb
+= self
.spr_o
.ok
.eq(1)
95 for x
, v
in spr_to_fast
.items():
97 m
.d
.comb
+= self
.fast_o
.data
.eq(v
)
98 m
.d
.comb
+= self
.fast_o
.ok
.eq(1)
99 for x
, v
in spr_to_state
.items():
100 with m
.Case(x
.value
):
101 m
.d
.comb
+= self
.state_o
.data
.eq(v
)
102 m
.d
.comb
+= self
.state_o
.ok
.eq(1)
106 class DecodeA(Elaboratable
):
107 """DecodeA from instruction
109 decodes register RA, implicit and explicit CSRs
112 def __init__(self
, dec
, op
, regreduce_en
):
113 self
.regreduce_en
= regreduce_en
114 if self
.regreduce_en
:
120 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
121 self
.insn_in
= Signal(32, reset_less
=True)
122 self
.reg_out
= Data(5, name
="reg_a")
123 self
.spr_out
= Data(SPR
, "spr_a")
124 self
.fast_out
= Data(4, "fast_a")
125 self
.state_out
= Data(3, "state_a")
126 self
.sv_nz
= Signal(1)
128 def elaborate(self
, platform
):
133 m
.submodules
.sprmap
= sprmap
= SPRMap(self
.regreduce_en
)
135 # select Register A field, if *full 7 bits* are zero (2 more from SVP64)
136 ra
= Signal(5, reset_less
=True)
137 comb
+= ra
.eq(self
.dec
.RA
)
138 with m
.If((self
.sel_in
== In1Sel
.RA
) |
139 ((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
140 ((ra
!= Const(0, 5)) |
(self
.sv_nz
!= Const(0, 1))))):
141 comb
+= reg
.data
.eq(ra
)
144 # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
145 # moved it to 1st position (in1_sel)... because
146 rs
= Signal(5, reset_less
=True)
147 comb
+= rs
.eq(self
.dec
.RS
)
148 with m
.If(self
.sel_in
== In1Sel
.RS
):
149 comb
+= reg
.data
.eq(rs
)
152 # select Register FRA field,
153 fra
= Signal(5, reset_less
=True)
154 comb
+= fra
.eq(self
.dec
.FRA
)
155 with m
.If(self
.sel_in
== In1Sel
.FRA
):
156 comb
+= reg
.data
.eq(fra
)
159 # select Register FRS field,
160 frs
= Signal(5, reset_less
=True)
161 comb
+= frs
.eq(self
.dec
.FRS
)
162 with m
.If(self
.sel_in
== In1Sel
.FRS
):
163 comb
+= reg
.data
.eq(frs
)
166 # decode Fast-SPR based on instruction type
167 with m
.Switch(op
.internal_op
):
169 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
170 with m
.Case(MicrOp
.OP_BC
):
171 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
173 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.CTR
)
174 comb
+= self
.fast_out
.ok
.eq(1)
175 with m
.Case(MicrOp
.OP_BCREG
):
176 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
177 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
178 with m
.If(xo9
& ~xo5
):
180 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.CTR
)
181 comb
+= self
.fast_out
.ok
.eq(1)
183 # MFSPR move from SPRs
184 with m
.Case(MicrOp
.OP_MFSPR
):
185 spr
= Signal(10, reset_less
=True)
186 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
187 comb
+= sprmap
.spr_i
.eq(spr
)
188 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
189 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
190 comb
+= self
.state_out
.eq(sprmap
.state_o
)
195 class DecodeAImm(Elaboratable
):
196 """DecodeA immediate from instruction
198 decodes register RA, whether immediate-zero, implicit and
199 explicit CSRs. SVP64 mode requires 2 extra bits
202 def __init__(self
, dec
):
204 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
205 self
.immz_out
= Signal(reset_less
=True)
206 self
.sv_nz
= Signal(1) # EXTRA bits from SVP64
208 def elaborate(self
, platform
):
212 # zero immediate requested
213 ra
= Signal(5, reset_less
=True)
214 comb
+= ra
.eq(self
.dec
.RA
)
215 with m
.If((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
216 (ra
== Const(0, 5)) &
217 (self
.sv_nz
== Const(0, 1))):
218 comb
+= self
.immz_out
.eq(1)
223 class DecodeB(Elaboratable
):
224 """DecodeB from instruction
226 decodes register RB, different forms of immediate (signed, unsigned),
227 and implicit SPRs. register B is basically "lane 2" into the CompUnits.
228 by industry-standard convention, "lane 2" is where fully-decoded
229 immediates are muxed in.
232 def __init__(self
, dec
, op
):
235 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
236 self
.insn_in
= Signal(32, reset_less
=True)
237 self
.reg_out
= Data(7, "reg_b")
238 self
.reg_isvec
= Signal(1, name
="reg_b_isvec") # TODO: in reg_out
239 self
.fast_out
= Data(4, "fast_b")
241 def elaborate(self
, platform
):
247 # select Register B field
248 with m
.Switch(self
.sel_in
):
249 with m
.Case(In2Sel
.FRB
):
250 comb
+= reg
.data
.eq(self
.dec
.FRB
)
252 with m
.Case(In2Sel
.RB
):
253 comb
+= reg
.data
.eq(self
.dec
.RB
)
255 with m
.Case(In2Sel
.RS
):
256 # for M-Form shiftrot
257 comb
+= reg
.data
.eq(self
.dec
.RS
)
260 # decode SPR2 based on instruction type
261 # BCREG implicitly uses LR or TAR for 2nd reg
262 # CTR however is already in fast_spr1 *not* 2.
263 with m
.If(op
.internal_op
== MicrOp
.OP_BCREG
):
264 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
265 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
267 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.LR
)
268 comb
+= self
.fast_out
.ok
.eq(1)
270 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.TAR
)
271 comb
+= self
.fast_out
.ok
.eq(1)
276 class DecodeBImm(Elaboratable
):
277 """DecodeB immediate from instruction
280 def __init__(self
, dec
):
282 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
283 self
.imm_out
= Data(64, "imm_b")
285 def elaborate(self
, platform
):
289 # select Register B Immediate
290 with m
.Switch(self
.sel_in
):
291 with m
.Case(In2Sel
.CONST_UI
): # unsigned
292 comb
+= self
.imm_out
.data
.eq(self
.dec
.UI
)
293 comb
+= self
.imm_out
.ok
.eq(1)
294 with m
.Case(In2Sel
.CONST_SI
): # sign-extended 16-bit
295 si
= Signal(16, reset_less
=True)
296 comb
+= si
.eq(self
.dec
.SI
)
297 comb
+= self
.imm_out
.data
.eq(exts(si
, 16, 64))
298 comb
+= self
.imm_out
.ok
.eq(1)
299 with m
.Case(In2Sel
.CONST_SI_HI
): # sign-extended 16+16=32 bit
300 si_hi
= Signal(32, reset_less
=True)
301 comb
+= si_hi
.eq(self
.dec
.SI
<< 16)
302 comb
+= self
.imm_out
.data
.eq(exts(si_hi
, 32, 64))
303 comb
+= self
.imm_out
.ok
.eq(1)
304 with m
.Case(In2Sel
.CONST_UI_HI
): # unsigned
305 ui
= Signal(16, reset_less
=True)
306 comb
+= ui
.eq(self
.dec
.UI
)
307 comb
+= self
.imm_out
.data
.eq(ui
<< 16)
308 comb
+= self
.imm_out
.ok
.eq(1)
309 with m
.Case(In2Sel
.CONST_LI
): # sign-extend 24+2=26 bit
310 li
= Signal(26, reset_less
=True)
311 comb
+= li
.eq(self
.dec
.LI
<< 2)
312 comb
+= self
.imm_out
.data
.eq(exts(li
, 26, 64))
313 comb
+= self
.imm_out
.ok
.eq(1)
314 with m
.Case(In2Sel
.CONST_BD
): # sign-extend (14+2)=16 bit
315 bd
= Signal(16, reset_less
=True)
316 comb
+= bd
.eq(self
.dec
.BD
<< 2)
317 comb
+= self
.imm_out
.data
.eq(exts(bd
, 16, 64))
318 comb
+= self
.imm_out
.ok
.eq(1)
319 with m
.Case(In2Sel
.CONST_DS
): # sign-extended (14+2=16) bit
320 ds
= Signal(16, reset_less
=True)
321 comb
+= ds
.eq(self
.dec
.DS
<< 2)
322 comb
+= self
.imm_out
.data
.eq(exts(ds
, 16, 64))
323 comb
+= self
.imm_out
.ok
.eq(1)
324 with m
.Case(In2Sel
.CONST_M1
): # signed (-1)
325 comb
+= self
.imm_out
.data
.eq(~
Const(0, 64)) # all 1s
326 comb
+= self
.imm_out
.ok
.eq(1)
327 with m
.Case(In2Sel
.CONST_SH
): # unsigned - for shift
328 comb
+= self
.imm_out
.data
.eq(self
.dec
.sh
)
329 comb
+= self
.imm_out
.ok
.eq(1)
330 with m
.Case(In2Sel
.CONST_SH32
): # unsigned - for shift
331 comb
+= self
.imm_out
.data
.eq(self
.dec
.SH32
)
332 comb
+= self
.imm_out
.ok
.eq(1)
333 with m
.Case(In2Sel
.CONST_XBI
): # unsigned - for grevi
334 comb
+= self
.imm_out
.data
.eq(self
.dec
.FormXB
.XBI
)
335 comb
+= self
.imm_out
.ok
.eq(1)
340 class DecodeC(Elaboratable
):
341 """DecodeC from instruction
343 decodes register RC. this is "lane 3" into some CompUnits (not many)
346 def __init__(self
, dec
, op
):
349 self
.sel_in
= Signal(In3Sel
, reset_less
=True)
350 self
.insn_in
= Signal(32, reset_less
=True)
351 self
.reg_out
= Data(5, "reg_c")
353 def elaborate(self
, platform
):
359 # select Register C field
360 with m
.Switch(self
.sel_in
):
361 with m
.Case(In3Sel
.RB
):
362 # for M-Form shiftrot
363 comb
+= reg
.data
.eq(self
.dec
.RB
)
365 with m
.Case(In3Sel
.FRS
):
366 comb
+= reg
.data
.eq(self
.dec
.FRS
)
368 with m
.Case(In3Sel
.FRC
):
369 comb
+= reg
.data
.eq(self
.dec
.FRC
)
371 with m
.Case(In3Sel
.RS
):
372 comb
+= reg
.data
.eq(self
.dec
.RS
)
374 with m
.Case(In3Sel
.RC
):
375 comb
+= reg
.data
.eq(self
.dec
.RC
)
377 with m
.Case(In3Sel
.RT
):
378 # for TLI-form ternlogi
379 comb
+= reg
.data
.eq(self
.dec
.RT
)
385 class DecodeOut(Elaboratable
):
386 """DecodeOut from instruction
388 decodes output register RA, RT, FRS, FRT, or SPR
391 def __init__(self
, dec
, op
, regreduce_en
):
392 self
.regreduce_en
= regreduce_en
393 if self
.regreduce_en
:
399 self
.sel_in
= Signal(OutSel
, reset_less
=True)
400 self
.insn_in
= Signal(32, reset_less
=True)
401 self
.reg_out
= Data(5, "reg_o")
402 self
.spr_out
= Data(SPR
, "spr_o")
403 self
.fast_out
= Data(4, "fast_o")
404 self
.state_out
= Data(3, "state_o")
406 def elaborate(self
, platform
):
409 m
.submodules
.sprmap
= sprmap
= SPRMap(self
.regreduce_en
)
413 # select Register out field
414 with m
.Switch(self
.sel_in
):
415 with m
.Case(OutSel
.FRS
):
416 comb
+= reg
.data
.eq(self
.dec
.FRS
)
418 with m
.Case(OutSel
.FRT
):
419 comb
+= reg
.data
.eq(self
.dec
.FRT
)
421 with m
.Case(OutSel
.RT
):
422 comb
+= reg
.data
.eq(self
.dec
.RT
)
424 with m
.Case(OutSel
.RA
):
425 comb
+= reg
.data
.eq(self
.dec
.RA
)
427 with m
.Case(OutSel
.SPR
):
428 spr
= Signal(10, reset_less
=True)
429 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
430 # MFSPR move to SPRs - needs mapping
431 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
432 comb
+= sprmap
.spr_i
.eq(spr
)
433 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
434 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
435 comb
+= self
.state_out
.eq(sprmap
.state_o
)
438 with m
.Switch(op
.internal_op
):
440 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
441 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_BCREG
):
442 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
444 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.CTR
)
445 comb
+= self
.fast_out
.ok
.eq(1)
447 # RFID 1st spr (fast)
448 with m
.Case(MicrOp
.OP_RFID
):
449 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.SRR0
) # SRR0
450 comb
+= self
.fast_out
.ok
.eq(1)
455 class DecodeOut2(Elaboratable
):
456 """DecodeOut2 from instruction
458 decodes output registers (2nd one). note that RA is *implicit* below,
459 which now causes problems with SVP64
461 TODO: SVP64 is a little more complex, here. svp64 allows extending
462 by one more destination by having one more EXTRA field. RA-as-src
463 is not the same as RA-as-dest. limited in that it's the same first
464 5 bits (from the v3.0B opcode), but still kinda cool. mostly used
465 for operations that have src-as-dest: mostly this is LD/ST-with-update
466 but there are others.
469 def __init__(self
, dec
, op
):
472 self
.sel_in
= Signal(OutSel
, reset_less
=True)
473 self
.svp64_fft_mode
= Signal(reset_less
=True) # SVP64 FFT mode
474 self
.lk
= Signal(reset_less
=True)
475 self
.insn_in
= Signal(32, reset_less
=True)
476 self
.reg_out
= Data(5, "reg_o2")
477 self
.fp_madd_en
= Signal(reset_less
=True) # FFT instruction detected
478 self
.fast_out
= Data(4, "fast_o2")
479 self
.fast_out3
= Data(4, "fast_o3")
481 def elaborate(self
, platform
):
485 #m.submodules.svdec = svdec = SVP64RegExtra()
487 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
488 #reg = Signal(5, reset_less=True)
490 if hasattr(op
, "upd"):
491 # update mode LD/ST uses read-reg A also as an output
492 with m
.If(op
.upd
== LDSTMode
.update
):
493 comb
+= self
.reg_out
.data
.eq(self
.dec
.RA
)
494 comb
+= self
.reg_out
.ok
.eq(1)
496 # B, BC or BCREG: potential implicit register (LR) output
497 # these give bl, bcl, bclrl, etc.
498 with m
.Switch(op
.internal_op
):
500 # BC* implicit register (LR)
501 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_B
, MicrOp
.OP_BCREG
):
502 with m
.If(self
.lk
): # "link" mode
503 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.LR
) # LR
504 comb
+= self
.fast_out
.ok
.eq(1)
506 # RFID 2nd and 3rd spr (fast)
507 with m
.Case(MicrOp
.OP_RFID
):
508 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.SRR1
) # SRR1
509 comb
+= self
.fast_out
.ok
.eq(1)
510 comb
+= self
.fast_out3
.data
.eq(FastRegsEnum
.SVSRR0
) # SVSRR0
511 comb
+= self
.fast_out3
.ok
.eq(1)
513 # SVP64 FFT mode, FP mul-add: 2nd output reg (FRS) same as FRT
514 # will be offset by VL in hardware
515 # with m.Case(MicrOp.OP_FP_MADD):
516 with m
.If(self
.svp64_fft_mode
):
517 comb
+= self
.reg_out
.data
.eq(self
.dec
.FRT
)
518 comb
+= self
.reg_out
.ok
.eq(1)
519 comb
+= self
.fp_madd_en
.eq(1)
524 class DecodeRC(Elaboratable
):
525 """DecodeRc from instruction
527 decodes Record bit Rc
530 def __init__(self
, dec
):
532 self
.sel_in
= Signal(RC
, reset_less
=True)
533 self
.insn_in
= Signal(32, reset_less
=True)
534 self
.rc_out
= Data(1, "rc")
536 def elaborate(self
, platform
):
540 # select Record bit out field
541 with m
.Switch(self
.sel_in
):
543 comb
+= self
.rc_out
.data
.eq(self
.dec
.Rc
)
544 comb
+= self
.rc_out
.ok
.eq(1)
546 comb
+= self
.rc_out
.data
.eq(1)
547 comb
+= self
.rc_out
.ok
.eq(1)
548 with m
.Case(RC
.NONE
):
549 comb
+= self
.rc_out
.data
.eq(0)
550 comb
+= self
.rc_out
.ok
.eq(1)
555 class DecodeOE(Elaboratable
):
556 """DecodeOE from instruction
558 decodes OE field: uses RC decode detection which might not be good
560 -- For now, use "rc" in the decode table to decide whether oe exists.
561 -- This is not entirely correct architecturally: For mulhd and
562 -- mulhdu, the OE field is reserved. It remains to be seen what an
563 -- actual POWER9 does if we set it on those instructions, for now we
564 -- test that further down when assigning to the multiplier oe input.
567 def __init__(self
, dec
, op
):
570 self
.sel_in
= Signal(RC
, reset_less
=True)
571 self
.insn_in
= Signal(32, reset_less
=True)
572 self
.oe_out
= Data(1, "oe")
574 def elaborate(self
, platform
):
579 with m
.Switch(op
.internal_op
):
581 # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE
583 # XXX ARGH! ignoring OE causes incompatibility with microwatt
584 # http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-August/000302.html
585 with m
.Case(MicrOp
.OP_MUL_H64
, MicrOp
.OP_MUL_H32
,
586 MicrOp
.OP_EXTS
, MicrOp
.OP_CNTZ
,
587 MicrOp
.OP_SHL
, MicrOp
.OP_SHR
, MicrOp
.OP_RLC
,
588 MicrOp
.OP_LOAD
, MicrOp
.OP_STORE
,
589 MicrOp
.OP_RLCL
, MicrOp
.OP_RLCR
,
590 MicrOp
.OP_EXTSWSLI
, MicrOp
.OP_GREV
, MicrOp
.OP_TERNLOG
):
593 # all other ops decode OE field
595 # select OE bit out field
596 with m
.Switch(self
.sel_in
):
598 comb
+= self
.oe_out
.data
.eq(self
.dec
.OE
)
599 comb
+= self
.oe_out
.ok
.eq(1)
604 class DecodeCRIn(Elaboratable
):
605 """Decodes input CR from instruction
607 CR indices - insn fields - (not the data *in* the CR) require only 3
608 bits because they refer to CR0-CR7
611 def __init__(self
, dec
, op
):
614 self
.sel_in
= Signal(CRInSel
, reset_less
=True)
615 self
.insn_in
= Signal(32, reset_less
=True)
616 self
.cr_bitfield
= Data(3, "cr_bitfield")
617 self
.cr_bitfield_b
= Data(3, "cr_bitfield_b")
618 self
.cr_bitfield_o
= Data(3, "cr_bitfield_o")
619 self
.whole_reg
= Data(8, "cr_fxm")
620 self
.sv_override
= Signal(2, reset_less
=True) # do not do EXTRA spec
622 def elaborate(self
, platform
):
626 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
629 # zero-initialisation
630 comb
+= self
.cr_bitfield
.ok
.eq(0)
631 comb
+= self
.cr_bitfield_b
.ok
.eq(0)
632 comb
+= self
.cr_bitfield_o
.ok
.eq(0)
633 comb
+= self
.whole_reg
.ok
.eq(0)
634 comb
+= self
.sv_override
.eq(0)
636 # select the relevant CR bitfields
637 with m
.Switch(self
.sel_in
):
638 with m
.Case(CRInSel
.NONE
):
639 pass # No bitfield activated
640 with m
.Case(CRInSel
.CR0
):
641 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
642 comb
+= self
.cr_bitfield
.ok
.eq(1)
643 comb
+= self
.sv_override
.eq(1)
644 with m
.Case(CRInSel
.CR1
):
645 comb
+= self
.cr_bitfield
.data
.eq(1) # CR1 (MSB0 numbering)
646 comb
+= self
.cr_bitfield
.ok
.eq(1)
647 comb
+= self
.sv_override
.eq(2)
648 with m
.Case(CRInSel
.BI
):
649 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BI
[2:5])
650 comb
+= self
.cr_bitfield
.ok
.eq(1)
651 with m
.Case(CRInSel
.BFA
):
652 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BFA
)
653 comb
+= self
.cr_bitfield
.ok
.eq(1)
654 with m
.Case(CRInSel
.BA_BB
):
655 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BA
[2:5])
656 comb
+= self
.cr_bitfield
.ok
.eq(1)
657 comb
+= self
.cr_bitfield_b
.data
.eq(self
.dec
.BB
[2:5])
658 comb
+= self
.cr_bitfield_b
.ok
.eq(1)
659 comb
+= self
.cr_bitfield_o
.data
.eq(self
.dec
.BT
[2:5])
660 comb
+= self
.cr_bitfield_o
.ok
.eq(1)
661 with m
.Case(CRInSel
.BC
):
662 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BC
[2:5])
663 comb
+= self
.cr_bitfield
.ok
.eq(1)
664 with m
.Case(CRInSel
.WHOLE_REG
):
665 comb
+= self
.whole_reg
.ok
.eq(1)
666 move_one
= Signal(reset_less
=True)
667 comb
+= move_one
.eq(self
.insn_in
[20]) # MSB0 bit 11
668 with m
.If((op
.internal_op
== MicrOp
.OP_MFCR
) & move_one
):
669 # must one-hot the FXM field
670 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
671 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
673 # otherwise use all of it
674 comb
+= self
.whole_reg
.data
.eq(0xff)
679 class DecodeCROut(Elaboratable
):
680 """Decodes input CR from instruction
682 CR indices - insn fields - (not the data *in* the CR) require only 3
683 bits because they refer to CR0-CR7
686 def __init__(self
, dec
, op
):
689 self
.rc_in
= Signal(reset_less
=True)
690 self
.sel_in
= Signal(CROutSel
, reset_less
=True)
691 self
.insn_in
= Signal(32, reset_less
=True)
692 self
.cr_bitfield
= Data(3, "cr_bitfield")
693 self
.whole_reg
= Data(8, "cr_fxm")
694 self
.sv_override
= Signal(2, reset_less
=True) # do not do EXTRA spec
696 def elaborate(self
, platform
):
700 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
703 comb
+= self
.cr_bitfield
.ok
.eq(0)
704 comb
+= self
.whole_reg
.ok
.eq(0)
705 comb
+= self
.sv_override
.eq(0)
707 # please note these MUST match (setting of cr_bitfield.ok) exactly
708 # with write_cr0 below in PowerDecoder2. the reason it's separated
709 # is to avoid having duplicate copies of DecodeCROut in multiple
710 # PowerDecoderSubsets. register decoding should be a one-off in
711 # PowerDecoder2. see https://bugs.libre-soc.org/show_bug.cgi?id=606
713 with m
.Switch(self
.sel_in
):
714 with m
.Case(CROutSel
.NONE
):
715 pass # No bitfield activated
716 with m
.Case(CROutSel
.CR0
):
717 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
718 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
719 comb
+= self
.sv_override
.eq(1)
720 with m
.Case(CROutSel
.CR1
):
721 comb
+= self
.cr_bitfield
.data
.eq(1) # CR1 (MSB0 numbering)
722 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
723 comb
+= self
.sv_override
.eq(2)
724 with m
.Case(CROutSel
.BF
):
725 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BF
)
726 comb
+= self
.cr_bitfield
.ok
.eq(1)
727 with m
.Case(CROutSel
.BT
):
728 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormXL
.BT
[2:5])
729 comb
+= self
.cr_bitfield
.ok
.eq(1)
730 with m
.Case(CROutSel
.WHOLE_REG
):
731 comb
+= self
.whole_reg
.ok
.eq(1)
732 move_one
= Signal(reset_less
=True)
733 comb
+= move_one
.eq(self
.insn_in
[20])
734 with m
.If((op
.internal_op
== MicrOp
.OP_MTCRF
)):
736 # must one-hot the FXM field
737 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
738 with m
.If(ppick
.en_o
):
739 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
741 comb
+= self
.whole_reg
.data
.eq(0b00000001) # CR7
743 comb
+= self
.whole_reg
.data
.eq(self
.dec
.FXM
)
745 # otherwise use all of it
746 comb
+= self
.whole_reg
.data
.eq(0xff)
751 # dictionary of Input Record field names that, if they exist,
752 # will need a corresponding CSV Decoder file column (actually, PowerOp)
753 # to be decoded (this includes the single bit names)
754 record_names
= {'insn_type': 'internal_op',
755 'fn_unit': 'function_unit',
756 'SV_Ptype': 'SV_Ptype',
760 'imm_data': 'in2_sel',
761 'invert_in': 'inv_a',
762 'invert_out': 'inv_out',
765 'output_carry': 'cry_out',
766 'input_carry': 'cry_in',
767 'is_32bit': 'is_32b',
770 'data_len': 'ldst_len',
772 'byte_reverse': 'br',
773 'sign_extend': 'sgn_ext',
778 class PowerDecodeSubset(Elaboratable
):
779 """PowerDecodeSubset: dynamic subset decoder
781 only fields actually requested are copied over. hence, "subset" (duh).
784 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False, state
=None,
785 svp64_en
=True, regreduce_en
=False):
787 self
.svp64_en
= svp64_en
788 self
.regreduce_en
= regreduce_en
790 self
.is_svp64_mode
= Signal() # mark decoding as SVP64 Mode
791 self
.use_svp64_fft
= Signal() # FFT Mode
792 self
.sv_rm
= SVP64Rec(name
="dec_svp64") # SVP64 RM field
793 self
.rm_dec
= SVP64RMModeDecode("svp64_rm_dec")
794 # set these to the predicate mask bits needed for the ALU
795 self
.pred_sm
= Signal() # TODO expand to SIMD mask width
796 self
.pred_dm
= Signal() # TODO expand to SIMD mask width
797 self
.sv_a_nz
= Signal(1)
800 self
.fn_name
= fn_name
802 opkls
= Decode2ToOperand
803 self
.do
= opkls(fn_name
)
805 col_subset
= self
.get_col_subset(self
.do
)
806 row_subset
= self
.rowsubsetfn
811 # "conditions" for Decoders, to enable some weird and wonderful
812 # alternatives. useful for PCR (Program Compatibility Register)
813 # amongst other things
816 'SVP64FFT': self
.use_svp64_fft
,
821 # only needed for "main" PowerDecode2
823 self
.e
= Decode2ToExecute1Type(name
=self
.fn_name
, do
=self
.do
,
824 regreduce_en
=regreduce_en
)
826 # create decoder if one not already given
828 dec
= create_pdecode(name
=fn_name
, col_subset
=col_subset
,
829 row_subset
=row_subset
,
830 conditions
=conditions
)
833 # set up a copy of the PowerOp
834 self
.op
= PowerOp
.like(self
.dec
.op
)
836 # state information needed by the Decoder
838 state
= CoreState("dec2")
841 def get_col_subset(self
, do
):
842 subset
= {'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
843 for k
, v
in record_names
.items():
846 log("get_col_subset", self
.fn_name
, do
.fields
, subset
)
849 def rowsubsetfn(self
, opcode
, row
):
850 """select per-Function-Unit subset of opcodes to be processed
852 normally this just looks at the "unit" column. MMU is different
853 in that it processes specific SPR set/get operations that the SPR
856 return (row
['unit'] == self
.fn_name
or
857 # sigh a dreadful hack: MTSPR and MFSPR need to be processed
858 # by the MMU pipeline so we direct those opcodes to MMU **AND**
859 # SPR pipelines, then selectively weed out the SPRs that should
860 # or should not not go to each pipeline, further down.
861 # really this should be done by modifying the CSV syntax
862 # to support multiple tasks (unit column multiple entries)
863 # see https://bugs.libre-soc.org/show_bug.cgi?id=310
864 (self
.fn_name
== 'MMU' and row
['unit'] == 'SPR' and
865 row
['internal op'] in ['OP_MTSPR', 'OP_MFSPR']) or
866 # urrr... and the KAIVB SPR, which must also be redirected
867 # (to the TRAP pipeline)
868 # see https://bugs.libre-soc.org/show_bug.cgi?id=859
869 (self
.fn_name
== 'TRAP' and row
['unit'] == 'SPR' and
870 row
['internal op'] in ['OP_MTSPR', 'OP_MFSPR'])
874 ports
= self
.dec
.ports() + self
.e
.ports()
876 ports
+= self
.sv_rm
.ports()
877 ports
.append(self
.is_svp64_mode
)
878 ports
.append(self
.use_svp64_fft
)
881 def needs_field(self
, field
, op_field
):
886 return hasattr(do
, field
) and self
.op_get(op_field
) is not None
888 def do_get(self
, field
, final
=False):
889 if final
or self
.final
:
893 return getattr(do
, field
, None)
895 def do_copy(self
, field
, val
, final
=False):
896 df
= self
.do_get(field
, final
)
897 if df
is not None and val
is not None:
901 def op_get(self
, op_field
):
902 return getattr(self
.op
, op_field
, None)
904 def elaborate(self
, platform
):
905 if self
.regreduce_en
:
912 op
, do
= self
.dec
.op
, self
.do
913 msr
, cia
, svstate
= state
.msr
, state
.pc
, state
.svstate
914 # fill in for a normal instruction (not an exception)
915 # copy over if non-exception, non-privileged etc. is detected
917 if self
.fn_name
is None:
920 name
= self
.fn_name
+ "tmp"
921 self
.e_tmp
= Decode2ToExecute1Type(name
=name
, opkls
=self
.opkls
,
922 regreduce_en
=self
.regreduce_en
)
924 # set up submodule decoders
925 m
.submodules
.dec
= dec
= self
.dec
926 m
.submodules
.dec_rc
= self
.dec_rc
= dec_rc
= DecodeRC(self
.dec
)
927 m
.submodules
.dec_oe
= dec_oe
= DecodeOE(self
.dec
, op
)
930 # and SVP64 RM mode decoder
931 m
.submodules
.sv_rm_dec
= rm_dec
= self
.rm_dec
933 # copy op from decoder
934 comb
+= self
.op
.eq(self
.dec
.op
)
936 # copy instruction through...
937 for i
in [do
.insn
, dec_rc
.insn_in
, dec_oe
.insn_in
, ]:
938 comb
+= i
.eq(self
.dec
.opcode_in
)
940 # ...and subdecoders' input fields
941 comb
+= dec_rc
.sel_in
.eq(self
.op_get("rc_sel"))
942 comb
+= dec_oe
.sel_in
.eq(self
.op_get("rc_sel")) # XXX should be OE sel
945 comb
+= self
.do_copy("msr", msr
)
946 comb
+= self
.do_copy("cia", cia
)
947 comb
+= self
.do_copy("svstate", svstate
)
949 # set up instruction type
950 # no op: defaults to OP_ILLEGAL
951 internal_op
= self
.op_get("internal_op")
952 comb
+= self
.do_copy("insn_type", internal_op
)
954 # function unit for decoded instruction: requires minor redirect
956 fn
= self
.op_get("function_unit")
957 spr
= Signal(10, reset_less
=True)
958 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
960 # Microwatt doesn't implement the partition table
961 # instead has PRTBL register (SPR) to point to process table
962 # Kestrel has a KAIVB SPR to "rebase" exceptions. rebasing is normally
963 # done with Hypervisor Mode which is not implemented (yet)
965 is_mmu_spr
= Signal()
966 is_trap_spr
= Signal()
967 comb
+= is_spr_mv
.eq((internal_op
== MicrOp
.OP_MTSPR
) |
968 (internal_op
== MicrOp
.OP_MFSPR
))
969 comb
+= is_mmu_spr
.eq((spr
== SPR
.DSISR
.value
) |
970 (spr
== SPR
.DAR
.value
) |
971 (spr
== SPR
.PRTBL
.value
) |
972 (spr
== SPR
.PIDR
.value
))
973 comb
+= is_trap_spr
.eq((spr
== SPR
.KAIVB
.value
)
975 # MMU must receive MMU SPRs
976 with m
.If(is_spr_mv
& (fn
== Function
.SPR
) & is_mmu_spr
):
977 comb
+= self
.do_copy("fn_unit", Function
.MMU
)
978 comb
+= self
.do_copy("insn_type", internal_op
)
979 # TRAP must receive TRAP SPR KAIVB
980 with m
.If(is_spr_mv
& (fn
== Function
.SPR
) & is_trap_spr
):
981 comb
+= self
.do_copy("fn_unit", Function
.TRAP
)
982 comb
+= self
.do_copy("insn_type", internal_op
)
983 # SPR pipe must *not* receive MMU or TRAP SPRs
984 with m
.Elif(is_spr_mv
& ((fn
== Function
.MMU
) & ~is_mmu_spr
) &
985 ((fn
== Function
.TRAP
) & ~is_trap_spr
)):
986 comb
+= self
.do_copy("fn_unit", Function
.NONE
)
987 comb
+= self
.do_copy("insn_type", MicrOp
.OP_ILLEGAL
)
990 comb
+= self
.do_copy("fn_unit", fn
)
993 if self
.needs_field("zero_a", "in1_sel"):
994 m
.submodules
.dec_ai
= dec_ai
= DecodeAImm(self
.dec
)
995 comb
+= dec_ai
.sv_nz
.eq(self
.sv_a_nz
)
996 comb
+= dec_ai
.sel_in
.eq(self
.op_get("in1_sel"))
997 comb
+= self
.do_copy("zero_a", dec_ai
.immz_out
) # RA==0 detected
998 if self
.needs_field("imm_data", "in2_sel"):
999 m
.submodules
.dec_bi
= dec_bi
= DecodeBImm(self
.dec
)
1000 comb
+= dec_bi
.sel_in
.eq(self
.op_get("in2_sel"))
1001 comb
+= self
.do_copy("imm_data", dec_bi
.imm_out
) # imm in RB
1004 comb
+= self
.do_copy("rc", dec_rc
.rc_out
)
1006 # OE only enabled when SVP64 not active
1007 with m
.If(~self
.is_svp64_mode
):
1008 comb
+= self
.do_copy("oe", dec_oe
.oe_out
)
1010 comb
+= self
.do_copy("oe", dec_oe
.oe_out
)
1012 # CR in/out - note: these MUST match with what happens in
1014 rc_out
= self
.dec_rc
.rc_out
.data
1015 with m
.Switch(self
.op_get("cr_out")):
1016 with m
.Case(CROutSel
.CR0
, CROutSel
.CR1
):
1017 comb
+= self
.do_copy("write_cr0", rc_out
) # only when RC=1
1018 with m
.Case(CROutSel
.BF
, CROutSel
.BT
):
1019 comb
+= self
.do_copy("write_cr0", 1)
1021 comb
+= self
.do_copy("input_cr", self
.op_get("cr_in")) # CR in
1022 comb
+= self
.do_copy("output_cr", self
.op_get("cr_out")) # CR out
1025 # connect up SVP64 RM Mode decoding. however... we need a shorter
1026 # path, for the LDST bit-reverse detection. so perform partial
1027 # decode when SVP64 is detected. then, bit-reverse mode can be
1028 # quickly determined, and the Decoder result MUXed over to
1029 # the alternative decoder, svdecldst. what a mess... *sigh*
1030 sv_ptype
= self
.op_get("SV_Ptype")
1031 fn
= self
.op_get("function_unit")
1032 comb
+= rm_dec
.fn_in
.eq(fn
) # decode needs to know Fn type
1033 comb
+= rm_dec
.ptype_in
.eq(sv_ptype
) # Single/Twin predicated
1034 comb
+= rm_dec
.rc_in
.eq(rc_out
) # Rc=1
1035 comb
+= rm_dec
.rm_in
.eq(self
.sv_rm
) # SVP64 RM mode
1036 if self
.needs_field("imm_data", "in2_sel"):
1037 bzero
= dec_bi
.imm_out
.ok
& ~dec_bi
.imm_out
.data
.bool()
1038 comb
+= rm_dec
.ldst_imz_in
.eq(bzero
) # B immediate is zero
1040 # main PowerDecoder2 determines if different SVP64 modes enabled
1041 # detect if SVP64 FFT mode enabled (really bad hack),
1042 # exclude fcfids and others
1043 # XXX this is a REALLY bad hack, REALLY has to be done better.
1044 # likely with a sub-decoder.
1046 comb
+= major
.eq(self
.dec
.opcode_in
[26:32])
1047 xo5
= Signal(1) # 1 bit from Minor 59 XO field == 0b0XXXX
1048 comb
+= xo5
.eq(self
.dec
.opcode_in
[5])
1049 xo
= Signal(5) # 5 bits from Minor 59 fcfids == 0b01110
1050 comb
+= xo
.eq(self
.dec
.opcode_in
[1:6])
1051 comb
+= self
.use_svp64_fft
.eq((major
== 59) & (xo5
== 0b0) &
1054 # decoded/selected instruction flags
1055 comb
+= self
.do_copy("data_len", self
.op_get("ldst_len"))
1056 comb
+= self
.do_copy("invert_in", self
.op_get("inv_a"))
1057 comb
+= self
.do_copy("invert_out", self
.op_get("inv_out"))
1058 comb
+= self
.do_copy("input_carry", self
.op_get("cry_in"))
1059 comb
+= self
.do_copy("output_carry", self
.op_get("cry_out"))
1060 comb
+= self
.do_copy("is_32bit", self
.op_get("is_32b"))
1061 comb
+= self
.do_copy("is_signed", self
.op_get("sgn"))
1062 lk
= self
.op_get("lk")
1065 comb
+= self
.do_copy("lk", self
.dec
.LK
) # XXX TODO: accessor
1067 comb
+= self
.do_copy("byte_reverse", self
.op_get("br"))
1068 comb
+= self
.do_copy("sign_extend", self
.op_get("sgn_ext"))
1069 comb
+= self
.do_copy("ldst_mode", self
.op_get("upd")) # LD/ST mode
1070 comb
+= self
.do_copy("reserve", self
.op_get("rsrv")) # atomic
1072 # copy over SVP64 input record fields (if they exist)
1074 # TODO, really do we have to do these explicitly?? sigh
1075 # for (field, _) in sv_input_record_layout:
1076 # comb += self.do_copy(field, self.rm_dec.op_get(field))
1077 comb
+= self
.do_copy("sv_saturate", self
.rm_dec
.saturate
)
1078 comb
+= self
.do_copy("sv_Ptype", self
.rm_dec
.ptype_in
)
1079 comb
+= self
.do_copy("sv_ldstmode", self
.rm_dec
.ldstmode
)
1080 # these get set up based on incoming mask bits. TODO:
1081 # pass in multiple bits (later, when SIMD backends are enabled)
1082 with m
.If(self
.rm_dec
.pred_sz
):
1083 comb
+= self
.do_copy("sv_pred_sz", ~self
.pred_sm
)
1084 with m
.If(self
.rm_dec
.pred_dz
):
1085 comb
+= self
.do_copy("sv_pred_dz", ~self
.pred_dm
)
1090 class PowerDecode2(PowerDecodeSubset
):
1091 """PowerDecode2: the main instruction decoder.
1093 whilst PowerDecode is responsible for decoding the actual opcode, this
1094 module encapsulates further specialist, sparse information and
1095 expansion of fields that is inconvenient to have in the CSV files.
1096 for example: the encoding of the immediates, which are detected
1097 and expanded out to their full value from an annotated (enum)
1100 implicit register usage is also set up, here. for example: OP_BC
1101 requires implicitly reading CTR, OP_RFID requires implicitly writing
1104 in addition, PowerDecoder2 is responsible for detecting whether
1105 instructions are illegal (or privileged) or not, and instead of
1106 just leaving at that, *replacing* the instruction to execute with
1107 a suitable alternative (trap).
1109 LDSTExceptions are done the cycle _after_ they're detected (after
1110 they come out of LDSTCompUnit). basically despite the instruction
1111 being decoded, the results of the decode are completely ignored
1112 and "exception.happened" used to set the "actual" instruction to
1113 "OP_TRAP". the LDSTException data structure gets filled in,
1114 in the CompTrapOpSubset and that's what it fills in SRR.
1116 to make this work, TestIssuer must notice "exception.happened"
1117 after the (failed) LD/ST and copies the LDSTException info from
1118 the output, into here (PowerDecoder2). without incrementing PC.
1120 also instr_fault works the same way: the instruction is "rewritten"
1121 so that the "fake" op that gets created is OP_FETCH_FAILED
1124 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False,
1125 state
=None, svp64_en
=True, regreduce_en
=False):
1126 super().__init
__(dec
, opkls
, fn_name
, final
, state
, svp64_en
,
1128 self
.ldst_exc
= LDSTException("dec2_exc") # rewrites as OP_TRAP
1129 self
.instr_fault
= Signal() # rewrites instruction as OP_FETCH_FAILED
1132 self
.cr_out_isvec
= Signal(1, name
="cr_out_isvec")
1133 self
.cr_in_isvec
= Signal(1, name
="cr_in_isvec")
1134 self
.cr_in_b_isvec
= Signal(1, name
="cr_in_b_isvec")
1135 self
.cr_in_o_isvec
= Signal(1, name
="cr_in_o_isvec")
1136 self
.in1_isvec
= Signal(1, name
="reg_a_isvec")
1137 self
.in2_isvec
= Signal(1, name
="reg_b_isvec")
1138 self
.in3_isvec
= Signal(1, name
="reg_c_isvec")
1139 self
.o_isvec
= Signal(7, name
="reg_o_isvec")
1140 self
.o2_isvec
= Signal(7, name
="reg_o2_isvec")
1141 self
.in1_step
= Signal(7, name
="reg_a_step")
1142 self
.in2_step
= Signal(7, name
="reg_b_step")
1143 self
.in3_step
= Signal(7, name
="reg_c_step")
1144 self
.o_step
= Signal(7, name
="reg_o_step")
1145 self
.o2_step
= Signal(7, name
="reg_o2_step")
1146 self
.remap_active
= Signal(5, name
="remap_active") # per reg
1147 self
.no_in_vec
= Signal(1, name
="no_in_vec") # no inputs vector
1148 self
.no_out_vec
= Signal(1, name
="no_out_vec") # no outputs vector
1149 self
.loop_continue
= Signal(1, name
="loop_continue")
1151 self
.no_in_vec
= Const(1, 1)
1152 self
.no_out_vec
= Const(1, 1)
1153 self
.loop_continue
= Const(0, 1)
1155 def get_col_subset(self
, opkls
):
1156 subset
= super().get_col_subset(opkls
)
1157 subset
.add("asmcode")
1158 subset
.add("in1_sel")
1159 subset
.add("in2_sel")
1160 subset
.add("in3_sel")
1161 subset
.add("out_sel")
1163 subset
.add("sv_in1")
1164 subset
.add("sv_in2")
1165 subset
.add("sv_in3")
1166 subset
.add("sv_out")
1167 subset
.add("sv_out2")
1168 subset
.add("sv_cr_in")
1169 subset
.add("sv_cr_out")
1170 subset
.add("SV_Etype")
1171 subset
.add("SV_Ptype")
1172 # from SVP64RMModeDecode
1173 for (field
, _
) in sv_input_record_layout
:
1176 subset
.add("internal_op")
1180 def elaborate(self
, platform
):
1181 m
= super().elaborate(platform
)
1184 op
, e_out
, do_out
= self
.op
, self
.e
, self
.e
.do
1185 dec_spr
, msr
, cia
, ext_irq
= state
.dec
, state
.msr
, state
.pc
, state
.eint
1186 rc_out
= self
.dec_rc
.rc_out
.data
1190 # fill in for a normal instruction (not an exception)
1191 # copy over if non-exception, non-privileged etc. is detected
1193 # set up submodule decoders
1194 m
.submodules
.dec_a
= dec_a
= DecodeA(self
.dec
, op
, self
.regreduce_en
)
1195 m
.submodules
.dec_b
= dec_b
= DecodeB(self
.dec
, op
)
1196 m
.submodules
.dec_c
= dec_c
= DecodeC(self
.dec
, op
)
1197 m
.submodules
.dec_o
= dec_o
= DecodeOut(self
.dec
, op
, self
.regreduce_en
)
1198 m
.submodules
.dec_o2
= dec_o2
= DecodeOut2(self
.dec
, op
)
1199 m
.submodules
.dec_cr_in
= self
.dec_cr_in
= DecodeCRIn(self
.dec
, op
)
1200 m
.submodules
.dec_cr_out
= self
.dec_cr_out
= DecodeCROut(self
.dec
, op
)
1201 comb
+= dec_a
.sv_nz
.eq(self
.sv_a_nz
)
1204 # and SVP64 Extra decoders
1205 m
.submodules
.crout_svdec
= crout_svdec
= SVP64CRExtra()
1206 m
.submodules
.crin_svdec
= crin_svdec
= SVP64CRExtra()
1207 m
.submodules
.crin_svdec_b
= crin_svdec_b
= SVP64CRExtra()
1208 m
.submodules
.crin_svdec_o
= crin_svdec_o
= SVP64CRExtra()
1209 m
.submodules
.in1_svdec
= in1_svdec
= SVP64RegExtra()
1210 m
.submodules
.in2_svdec
= in2_svdec
= SVP64RegExtra()
1211 m
.submodules
.in3_svdec
= in3_svdec
= SVP64RegExtra()
1212 m
.submodules
.o_svdec
= o_svdec
= SVP64RegExtra()
1213 m
.submodules
.o2_svdec
= o2_svdec
= SVP64RegExtra()
1215 # debug access to cr svdec (used in get_pdecode_cr_in/out)
1216 self
.crout_svdec
= crout_svdec
1217 self
.crin_svdec
= crin_svdec
1219 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
1220 reg
= Signal(5, reset_less
=True)
1222 # copy instruction through...
1223 for i
in [do
.insn
, dec_a
.insn_in
, dec_b
.insn_in
,
1224 self
.dec_cr_in
.insn_in
, self
.dec_cr_out
.insn_in
,
1225 dec_c
.insn_in
, dec_o
.insn_in
, dec_o2
.insn_in
]:
1226 comb
+= i
.eq(self
.dec
.opcode_in
)
1229 comb
+= self
.dec_cr_in
.sel_in
.eq(self
.op_get("cr_in"))
1230 comb
+= self
.dec_cr_out
.sel_in
.eq(self
.op_get("cr_out"))
1231 comb
+= self
.dec_cr_out
.rc_in
.eq(rc_out
)
1234 comb
+= self
.do_copy("read_cr_whole", self
.dec_cr_in
.whole_reg
)
1235 comb
+= self
.do_copy("write_cr_whole", self
.dec_cr_out
.whole_reg
)
1237 # ...and subdecoders' input fields
1238 comb
+= dec_a
.sel_in
.eq(self
.op_get("in1_sel"))
1239 comb
+= dec_b
.sel_in
.eq(self
.op_get("in2_sel"))
1240 comb
+= dec_c
.sel_in
.eq(self
.op_get("in3_sel"))
1241 comb
+= dec_o
.sel_in
.eq(self
.op_get("out_sel"))
1242 comb
+= dec_o2
.sel_in
.eq(self
.op_get("out_sel"))
1244 comb
+= dec_o2
.svp64_fft_mode
.eq(self
.use_svp64_fft
)
1245 if hasattr(do
, "lk"):
1246 comb
+= dec_o2
.lk
.eq(do
.lk
)
1249 # now do the SVP64 munging. op.SV_Etype and op.sv_in1 comes from
1250 # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
1251 # which in turn were auto-generated by sv_analysis.py
1252 extra
= self
.sv_rm
.extra
# SVP64 extra bits 10:18
1257 comb
+= crout_svdec
.idx
.eq(self
.op_get("sv_cr_out"))
1258 comb
+= self
.cr_out_isvec
.eq(crout_svdec
.isvec
)
1261 # CR in - selection slightly different due to shared CR field sigh
1262 cr_a_idx
= Signal(SVEXTRA
)
1263 cr_b_idx
= Signal(SVEXTRA
)
1265 # these change slightly, when decoding BA/BB. really should have
1266 # their own separate CSV column: sv_cr_in1 and sv_cr_in2, but hey
1267 comb
+= cr_a_idx
.eq(self
.op_get("sv_cr_in"))
1268 comb
+= cr_b_idx
.eq(SVEXTRA
.NONE
)
1269 with m
.If(self
.op_get("sv_cr_in") == SVEXTRA
.Idx_1_2
.value
):
1270 comb
+= cr_a_idx
.eq(SVEXTRA
.Idx1
)
1271 comb
+= cr_b_idx
.eq(SVEXTRA
.Idx2
)
1273 comb
+= self
.cr_in_isvec
.eq(crin_svdec
.isvec
)
1274 comb
+= self
.cr_in_b_isvec
.eq(crin_svdec_b
.isvec
)
1275 comb
+= self
.cr_in_o_isvec
.eq(crin_svdec_o
.isvec
)
1277 # indices are slightly different, BA/BB mess sorted above
1278 comb
+= crin_svdec
.idx
.eq(cr_a_idx
) # SVP64 CR in A
1279 comb
+= crin_svdec_b
.idx
.eq(cr_b_idx
) # SVP64 CR in B
1281 comb
+= crin_svdec_o
.idx
.eq(self
.op_get("sv_cr_out"))
1283 # get SVSTATE srcstep (TODO: elwidth etc.) needed below
1284 vl
= Signal
.like(self
.state
.svstate
.vl
)
1285 subvl
= Signal
.like(self
.rm_dec
.rm_in
.subvl
)
1286 srcstep
= Signal
.like(self
.state
.svstate
.srcstep
)
1287 dststep
= Signal
.like(self
.state
.svstate
.dststep
)
1288 ssubstep
= Signal
.like(self
.state
.svstate
.ssubstep
)
1289 dsubstep
= Signal
.like(self
.state
.svstate
.ssubstep
)
1290 comb
+= vl
.eq(self
.state
.svstate
.vl
)
1291 comb
+= subvl
.eq(self
.rm_dec
.rm_in
.subvl
)
1292 comb
+= srcstep
.eq(self
.state
.svstate
.srcstep
)
1293 comb
+= dststep
.eq(self
.state
.svstate
.dststep
)
1294 comb
+= ssubstep
.eq(self
.state
.svstate
.ssubstep
)
1295 comb
+= dsubstep
.eq(self
.state
.svstate
.dsubstep
)
1297 in1_step
, in2_step
= self
.in1_step
, self
.in2_step
1298 in3_step
= self
.in3_step
1299 o_step
, o2_step
= self
.o_step
, self
.o2_step
1301 # multiply vl by subvl - note that this is only 7 bit!
1302 # when elwidth overrides get involved this will have to go up
1304 comb
+= vmax
.eq(vl
*(subvl
+1))
1306 # registers a, b, c and out and out2 (LD/ST EA)
1307 sv_etype
= self
.op_get("SV_Etype")
1308 for i
, stuff
in enumerate((
1309 ("RA", e
.read_reg1
, dec_a
.reg_out
, in1_svdec
, in1_step
, False),
1310 ("RB", e
.read_reg2
, dec_b
.reg_out
, in2_svdec
, in2_step
, False),
1311 ("RC", e
.read_reg3
, dec_c
.reg_out
, in3_svdec
, in3_step
, False),
1312 ("RT", e
.write_reg
, dec_o
.reg_out
, o_svdec
, o_step
, True),
1313 ("EA", e
.write_ea
, dec_o2
.reg_out
, o2_svdec
, o2_step
, True))):
1314 rname
, to_reg
, fromreg
, svdec
, remapstep
, out
= stuff
1315 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1316 comb
+= svdec
.etype
.eq(sv_etype
) # EXTRA2/3 for this insn
1317 comb
+= svdec
.reg_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1318 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1319 # *screaam* FFT mode needs an extra offset for RB
1320 # similar to FRS/FRT (below). all of this needs cleanup
1321 offs
= Signal(7, name
="offs_"+rname
, reset_less
=True)
1324 # when FFT sv.ffmadd detected, and REMAP not in use,
1325 # automagically add on an extra offset to RB.
1326 # however when REMAP is active, the FFT REMAP
1327 # schedule takes care of this offset.
1328 with m
.If(dec_o2
.reg_out
.ok
& dec_o2
.fp_madd_en
):
1329 with m
.If(~self
.remap_active
[i
]):
1330 with m
.If(svdec
.isvec
):
1331 comb
+= offs
.eq(vl
) # VL for Vectors
1332 # detect if Vectorised: add srcstep/dststep if yes.
1333 # to_reg is 7-bits, outs get dststep added, ins get srcstep
1334 with m
.If(svdec
.isvec
):
1335 selectstep
= dststep
if out
else srcstep
1336 subselect
= dsubstep
if out
else ssubstep
1337 step
= Signal(7, name
="step_%s" % rname
.lower())
1338 with m
.If(self
.remap_active
[i
]):
1339 comb
+= step
.eq((remapstep
*(subvl
+1))+subselect
)
1341 comb
+= step
.eq((selectstep
*(subvl
+1))+subselect
)
1342 # reverse gear goes the opposite way
1343 with m
.If(self
.rm_dec
.reverse_gear
):
1344 comb
+= to_reg
.data
.eq(offs
+svdec
.reg_out
+(vmax
-1-step
))
1346 comb
+= to_reg
.data
.eq(offs
+step
+svdec
.reg_out
)
1348 comb
+= to_reg
.data
.eq(offs
+svdec
.reg_out
)
1350 # SVP64 in/out fields
1351 comb
+= in1_svdec
.idx
.eq(self
.op_get("sv_in1")) # reg #1 (in1_sel)
1352 comb
+= in2_svdec
.idx
.eq(self
.op_get("sv_in2")) # reg #2 (in2_sel)
1353 comb
+= in3_svdec
.idx
.eq(self
.op_get("sv_in3")) # reg #3 (in3_sel)
1354 comb
+= o_svdec
.idx
.eq(self
.op_get("sv_out")) # output (out_sel)
1356 comb
+= o2_svdec
.idx
.eq(self
.op_get("sv_out2"))
1357 # XXX TODO - work out where this should come from. the problem is
1358 # that LD-with-update is implied (computed from "is instruction in
1359 # "update mode" rather than specified cleanly as its own CSV column
1361 # output reg-is-vectorised (and when no in/out is vectorised)
1362 comb
+= self
.in1_isvec
.eq(in1_svdec
.isvec
)
1363 comb
+= self
.in2_isvec
.eq(in2_svdec
.isvec
)
1364 comb
+= self
.in3_isvec
.eq(in3_svdec
.isvec
)
1365 comb
+= self
.o_isvec
.eq(o_svdec
.isvec
)
1366 comb
+= self
.o2_isvec
.eq(o2_svdec
.isvec
)
1368 # urrr... don't ask... the implicit register FRS in FFT mode
1369 # "tracks" FRT exactly except it's offset by VL. rather than
1370 # mess up the above with if-statements, override it here.
1371 # same trick is applied to FRA, above, but it's a lot cleaner, there
1372 with m
.If(dec_o2
.reg_out
.ok
& dec_o2
.fp_madd_en
):
1374 with m
.If(~self
.remap_active
[4]):
1375 with m
.If(o2_svdec
.isvec
):
1376 comb
+= offs
.eq(vl
) # VL for Vectors
1378 comb
+= offs
.eq(1) # add 1 if scalar
1379 svdec
= o_svdec
# yes take source as o_svdec...
1380 with m
.If(svdec
.isvec
):
1381 step
= Signal(7, name
="step_%s" % rname
.lower())
1382 with m
.If(self
.remap_active
[4]):
1383 comb
+= step
.eq(o2_step
)
1385 comb
+= step
.eq(dststep
)
1386 # reverse gear goes the opposite way
1387 with m
.If(self
.rm_dec
.reverse_gear
):
1388 roffs
= offs
+(vl
-1-step
)
1389 comb
+= to_reg
.data
.eq(roffs
+svdec
.reg_out
)
1391 comb
+= to_reg
.data
.eq(offs
+step
+svdec
.reg_out
)
1393 comb
+= to_reg
.data
.eq(offs
+svdec
.reg_out
)
1394 # ... but write to *second* output
1395 comb
+= self
.o2_isvec
.eq(svdec
.isvec
)
1396 comb
+= o2_svdec
.idx
.eq(self
.op_get("sv_out"))
1398 # TODO add SPRs here. must be True when *all* are scalar
1399 l
= map(lambda svdec
: svdec
.isvec
, [in1_svdec
, in2_svdec
, in3_svdec
,
1400 crin_svdec
, crin_svdec_b
,
1402 comb
+= self
.no_in_vec
.eq(~
Cat(*l
).bool()) # all input scalar
1403 l
= map(lambda svdec
: svdec
.isvec
, [
1404 o2_svdec
, o_svdec
, crout_svdec
])
1405 # in mapreduce mode, scalar out is *allowed*
1406 with m
.If(self
.rm_dec
.mode
== SVP64RMMode
.MAPREDUCE
.value
):
1407 comb
+= self
.no_out_vec
.eq(0)
1410 comb
+= self
.no_out_vec
.eq(~
Cat(*l
).bool())
1411 # now create a general-purpose "test" as to whether looping
1412 # should continue. this doesn't include predication bit-tests
1413 loop
= self
.loop_continue
1414 with m
.Switch(self
.op_get("SV_Ptype")):
1415 with m
.Case(SVPtype
.P2
.value
):
1417 # TODO: *and cache-inhibited LD/ST!*
1418 comb
+= loop
.eq(~
(self
.no_in_vec | self
.no_out_vec
))
1419 with m
.Case(SVPtype
.P1
.value
):
1420 # single-predication, test relies on dest only
1421 comb
+= loop
.eq(~self
.no_out_vec
)
1423 # not an SV operation, no looping
1426 # condition registers (CR)
1427 for to_reg
, cr
, name
, svdec
, out
in (
1428 (e
.read_cr1
, self
.dec_cr_in
, "cr_bitfield", crin_svdec
, 0),
1429 (e
.read_cr2
, self
.dec_cr_in
, "cr_bitfield_b", crin_svdec_b
, 0),
1430 (e
.read_cr3
, self
.dec_cr_in
, "cr_bitfield_o", crin_svdec_o
, 0),
1431 (e
.write_cr
, self
.dec_cr_out
, "cr_bitfield", crout_svdec
, 1)):
1432 fromreg
= getattr(cr
, name
)
1433 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1434 comb
+= svdec
.etype
.eq(sv_etype
) # EXTRA2/3 for this insn
1435 comb
+= svdec
.cr_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1436 with m
.If(svdec
.isvec
):
1437 # check if this is CR0 or CR1: treated differently
1438 # (does not "listen" to EXTRA2/3 spec for a start)
1439 # also: the CRs start from completely different locations
1440 step
= dststep
if out
else srcstep
1441 with m
.If(cr
.sv_override
== 1): # CR0
1442 offs
= SVP64CROffs
.CR0
1443 comb
+= to_reg
.data
.eq(step
+offs
)
1444 with m
.Elif(cr
.sv_override
== 2): # CR1
1445 offs
= SVP64CROffs
.CR1
1446 comb
+= to_reg
.data
.eq(step
+1)
1448 comb
+= to_reg
.data
.eq(step
+svdec
.cr_out
) # 7-bit out
1450 comb
+= to_reg
.data
.eq(svdec
.cr_out
) # 7-bit output
1451 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1453 # sigh must determine if RA is nonzero (7 bit)
1454 comb
+= self
.sv_a_nz
.eq(e
.read_reg1
.data
!= Const(0, 7))
1456 # connect up to/from read/write GPRs
1457 for to_reg
, fromreg
in ((e
.read_reg1
, dec_a
.reg_out
),
1458 (e
.read_reg2
, dec_b
.reg_out
),
1459 (e
.read_reg3
, dec_c
.reg_out
),
1460 (e
.write_reg
, dec_o
.reg_out
),
1461 (e
.write_ea
, dec_o2
.reg_out
)):
1462 comb
+= to_reg
.data
.eq(fromreg
.data
)
1463 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1465 # connect up to/from read/write CRs
1466 for to_reg
, cr
, name
in (
1467 (e
.read_cr1
, self
.dec_cr_in
, "cr_bitfield", ),
1468 (e
.read_cr2
, self
.dec_cr_in
, "cr_bitfield_b", ),
1469 (e
.read_cr3
, self
.dec_cr_in
, "cr_bitfield_o", ),
1470 (e
.write_cr
, self
.dec_cr_out
, "cr_bitfield", )):
1471 fromreg
= getattr(cr
, name
)
1472 comb
+= to_reg
.data
.eq(fromreg
.data
)
1473 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1476 comb
+= self
.rm_dec
.ldst_ra_vec
.eq(self
.in1_isvec
) # RA is vector
1479 comb
+= e
.read_spr1
.eq(dec_a
.spr_out
)
1480 comb
+= e
.write_spr
.eq(dec_o
.spr_out
)
1482 # Fast regs out including SRR0/1/SVSRR0
1483 comb
+= e
.read_fast1
.eq(dec_a
.fast_out
)
1484 comb
+= e
.read_fast2
.eq(dec_b
.fast_out
)
1485 comb
+= e
.write_fast1
.eq(dec_o
.fast_out
) # SRR0 (OP_RFID)
1486 comb
+= e
.write_fast2
.eq(dec_o2
.fast_out
) # SRR1 (ditto)
1487 comb
+= e
.write_fast3
.eq(dec_o2
.fast_out3
) # SVSRR0 (ditto)
1488 # and State regs (DEC, TB)
1489 comb
+= e
.read_state1
.eq(dec_a
.state_out
) # DEC/TB
1490 comb
+= e
.write_state1
.eq(dec_o
.state_out
) # DEC/TB
1492 # sigh this is exactly the sort of thing for which the
1493 # decoder is designed to not need. MTSPR, MFSPR and others need
1494 # access to the XER bits. however setting e.oe is not appropriate
1495 internal_op
= self
.op_get("internal_op")
1496 with m
.If(internal_op
== MicrOp
.OP_MFSPR
):
1497 comb
+= e
.xer_in
.eq(0b111) # SO, CA, OV
1498 with m
.If(internal_op
== MicrOp
.OP_CMP
):
1499 comb
+= e
.xer_in
.eq(1 << XERRegsEnum
.SO
) # SO
1500 with m
.If(internal_op
== MicrOp
.OP_MTSPR
):
1501 comb
+= e
.xer_out
.eq(1)
1503 # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
1504 with m
.If(op
.internal_op
== MicrOp
.OP_TRAP
):
1505 # *DO NOT* call self.trap here. that would reset absolutely
1506 # everything including destroying read of RA and RB.
1507 comb
+= self
.do_copy("trapaddr", 0x70) # strip first nibble
1509 ####################
1510 # ok so the instruction's been decoded, blah blah, however
1511 # now we need to determine if it's actually going to go ahead...
1512 # *or* if in fact it's a privileged operation, whether there's
1513 # an external interrupt, etc. etc. this is a simple priority
1514 # if-elif-elif sequence. decrement takes highest priority,
1515 # EINT next highest, privileged operation third.
1517 # check if instruction is privileged
1518 is_priv_insn
= instr_is_priv(m
, op
.internal_op
, e
.do
.insn
)
1520 # different IRQ conditions
1521 ext_irq_ok
= Signal()
1522 dec_irq_ok
= Signal()
1525 ldst_exc
= self
.ldst_exc
1527 comb
+= ext_irq_ok
.eq(ext_irq
& msr
[MSR
.EE
]) # v3.0B p944 (MSR.EE)
1528 comb
+= dec_irq_ok
.eq(dec_spr
[63] & msr
[MSR
.EE
]) # 6.5.11 p1076
1529 comb
+= priv_ok
.eq(is_priv_insn
& msr
[MSR
.PR
])
1530 comb
+= illeg_ok
.eq(op
.internal_op
== MicrOp
.OP_ILLEGAL
)
1532 # absolute top priority: check for an instruction failed
1533 with m
.If(self
.instr_fault
):
1534 comb
+= self
.e
.eq(0) # reset eeeeeverything
1535 comb
+= self
.do_copy("insn", self
.dec
.opcode_in
, True)
1536 comb
+= self
.do_copy("insn_type", MicrOp
.OP_FETCH_FAILED
, True)
1537 comb
+= self
.do_copy("fn_unit", Function
.MMU
, True)
1538 comb
+= self
.do_copy("cia", self
.state
.pc
, True) # PC
1539 comb
+= self
.do_copy("msr", self
.state
.msr
, True) # MSR
1540 # special override on internal_op, due to being a "fake" op
1541 comb
+= self
.dec
.op
.internal_op
.eq(MicrOp
.OP_FETCH_FAILED
)
1543 # LD/ST exceptions. TestIssuer copies the exception info at us
1544 # after a failed LD/ST.
1545 with m
.Elif(ldst_exc
.happened
):
1546 with m
.If(ldst_exc
.alignment
):
1547 self
.trap(m
, TT
.MEMEXC
, 0x600)
1548 with m
.Elif(ldst_exc
.instr_fault
):
1549 with m
.If(ldst_exc
.segment_fault
):
1550 self
.trap(m
, TT
.MEMEXC
, 0x480)
1552 # pass exception info to trap to create SRR1
1553 self
.trap(m
, TT
.MEMEXC
, 0x400, ldst_exc
)
1555 with m
.If(ldst_exc
.segment_fault
):
1556 self
.trap(m
, TT
.MEMEXC
, 0x380)
1558 self
.trap(m
, TT
.MEMEXC
, 0x300)
1560 # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
1561 with m
.Elif(dec_irq_ok
):
1562 self
.trap(m
, TT
.DEC
, 0x900) # v3.0B 6.5 p1065
1564 # external interrupt? only if MSR.EE set
1565 with m
.Elif(ext_irq_ok
):
1566 self
.trap(m
, TT
.EINT
, 0x500)
1568 # privileged instruction trap
1569 with m
.Elif(priv_ok
):
1570 self
.trap(m
, TT
.PRIV
, 0x700)
1572 # illegal instruction must redirect to trap. this is done by
1573 # *overwriting* the decoded instruction and starting again.
1574 # (note: the same goes for interrupts and for privileged operations,
1575 # just with different trapaddr and traptype)
1576 with m
.Elif(illeg_ok
):
1577 # illegal instruction trap
1578 self
.trap(m
, TT
.ILLEG
, 0x700)
1580 # no exception, just copy things to the output
1584 ####################
1585 # follow-up after trap/irq to set up SRR0/1
1587 # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
1588 # Note: OP_SC could actually be modified to just be a trap
1589 with m
.If((do_out
.insn_type
== MicrOp
.OP_TRAP
) |
1590 (do_out
.insn_type
== MicrOp
.OP_SC
)):
1591 # TRAP write fast1 = SRR0
1592 comb
+= e_out
.write_fast1
.data
.eq(FastRegsEnum
.SRR0
) # SRR0
1593 comb
+= e_out
.write_fast1
.ok
.eq(1)
1594 # TRAP write fast2 = SRR1
1595 comb
+= e_out
.write_fast2
.data
.eq(FastRegsEnum
.SRR1
) # SRR1
1596 comb
+= e_out
.write_fast2
.ok
.eq(1)
1597 # TRAP write fast2 = SRR1
1598 comb
+= e_out
.write_fast3
.data
.eq(FastRegsEnum
.SVSRR0
) # SVSRR0
1599 comb
+= e_out
.write_fast3
.ok
.eq(1)
1601 # RFID: needs to read SRR0/1
1602 with m
.If(do_out
.insn_type
== MicrOp
.OP_RFID
):
1603 # TRAP read fast1 = SRR0
1604 comb
+= e_out
.read_fast1
.data
.eq(FastRegsEnum
.SRR0
) # SRR0
1605 comb
+= e_out
.read_fast1
.ok
.eq(1)
1606 # TRAP read fast2 = SRR1
1607 comb
+= e_out
.read_fast2
.data
.eq(FastRegsEnum
.SRR1
) # SRR1
1608 comb
+= e_out
.read_fast2
.ok
.eq(1)
1609 # TRAP read fast2 = SVSRR0
1610 comb
+= e_out
.read_fast3
.data
.eq(FastRegsEnum
.SVSRR0
) # SVSRR0
1611 comb
+= e_out
.read_fast3
.ok
.eq(1)
1613 # annoying simulator bug.
1614 # asmcode may end up getting used for perfcounters?
1615 asmcode
= self
.op_get("asmcode")
1616 if hasattr(e_out
, "asmcode") and asmcode
is not None:
1617 comb
+= e_out
.asmcode
.eq(asmcode
)
1621 def trap(self
, m
, traptype
, trapaddr
, ldst_exc
=None):
1622 """trap: this basically "rewrites" the decoded instruction as a trap
1626 comb
+= e
.eq(0) # reset eeeeeverything
1629 comb
+= self
.do_copy("insn", self
.dec
.opcode_in
, True)
1630 comb
+= self
.do_copy("insn_type", MicrOp
.OP_TRAP
, True)
1631 comb
+= self
.do_copy("fn_unit", Function
.TRAP
, True)
1632 comb
+= self
.do_copy("trapaddr", trapaddr
>> 4, True) # bottom 4 bits
1633 comb
+= self
.do_copy("traptype", traptype
, True) # request type
1634 comb
+= self
.do_copy("ldst_exc", ldst_exc
, True) # request type
1635 comb
+= self
.do_copy("msr", self
.state
.msr
,
1636 True) # copy of MSR "state"
1637 comb
+= self
.do_copy("cia", self
.state
.pc
, True) # copy of PC "state"
1638 comb
+= self
.do_copy("svstate", self
.state
.svstate
, True) # SVSTATE
1641 def get_rdflags(m
, e
, cu
):
1642 """returns a sequential list of the read "ok" flags for a given FU.
1643 this list is in order of the CompUnit input specs
1646 for idx
in range(cu
.n_src
):
1647 regfile
, regname
, _
= cu
.get_in_spec(idx
)
1648 decinfo
= regspec_decode_read(m
, e
, regfile
, regname
)
1649 rdl
.append(decinfo
.okflag
)
1654 if __name__
== '__main__':
1655 pdecode
= create_pdecode()
1656 dec2
= PowerDecode2(pdecode
, svp64_en
=True)
1657 vl
= rtlil
.convert(dec2
, ports
=dec2
.ports() + pdecode
.ports())
1658 with
open("dec2.il", "w") as f
: