src/openpower/decoder/power_decoder2.py

   1 """Power ISA Decoder second stage
   2
   3 based on Anton Blanchard microwatt decode2.vhdl
   4
   5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
   6 over-riding the internal opcode when an exception is needed.
   7 """
   8
   9 from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl, Record
  10 from nmigen.cli import rtlil
  11 from nmutil.util import sel
  12
  13 from nmutil.picker import PriorityPicker
  14 from nmutil.iocontrol import RecordObject
  15 from nmutil.extend import exts
  16
  17 from openpower.exceptions import LDSTException
  18
  19 from openpower.decoder.power_svp64_prefix import SVP64PrefixDecoder
  20 from openpower.decoder.power_svp64_extra import SVP64CRExtra, SVP64RegExtra
  21 from openpower.decoder.power_svp64_rm import (SVP64RMModeDecode,
  22                                               sv_input_record_layout,
  23                                               SVP64RMMode)
  24 from openpower.sv.svp64 import SVP64Rec
  25
  26 from openpower.decoder.power_regspec_map import regspec_decode_read
  27 from openpower.decoder.power_decoder import (create_pdecode,
  28                                              create_pdecode_svp64_ldst,
  29                                              PowerOp)
  30 from openpower.decoder.power_enums import (MicrOp, CryIn, Function,
  31                                      CRInSel, CROutSel,
  32                                      LdstLen, In1Sel, In2Sel, In3Sel,
  33                                      OutSel, SPRfull, SPRreduced,
  34                                      RC, SVP64LDSTmode, LDSTMode,
  35                                      SVEXTRA, SVEtype, SVPtype)
  36 from openpower.decoder.decode2execute1 import (Decode2ToExecute1Type, Data,
  37                                                Decode2ToOperand)
  38
  39 from openpower.consts import (MSR, SPEC, EXTRA2, EXTRA3, SVP64P, field,
  40                               SPEC_SIZE, SPECb, SPEC_AUG_SIZE, SVP64CROffs,
  41                               FastRegsEnum, XERRegsEnum, TT)
  42
  43 from openpower.state import CoreState
  44 from openpower.util import (spr_to_fast, log)
  45
  46
  47 def decode_spr_num(spr):
  48     return Cat(spr[5:10], spr[0:5])
  49
  50
  51 def instr_is_priv(m, op, insn):
  52     """determines if the instruction is privileged or not
  53     """
  54     comb = m.d.comb
  55     is_priv_insn = Signal(reset_less=True)
  56     with m.Switch(op):
  57         with m.Case(MicrOp.OP_ATTN, MicrOp.OP_MFMSR, MicrOp.OP_MTMSRD,
  58                     MicrOp.OP_MTMSR, MicrOp.OP_RFID):
  59             comb += is_priv_insn.eq(1)
  60         with m.Case(MicrOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
  61         with m.Case(MicrOp.OP_MFSPR, MicrOp.OP_MTSPR):
  62             with m.If(insn[20]):  # field XFX.spr[-1] i think
  63                 comb += is_priv_insn.eq(1)
  64     return is_priv_insn
  65
  66
  67 class SPRMap(Elaboratable):
  68     """SPRMap: maps POWER9 SPR numbers to internal enum values, fast and slow
  69     """
  70
  71     def __init__(self, regreduce_en):
  72         self.regreduce_en = regreduce_en
  73         if regreduce_en:
  74             SPR = SPRreduced
  75         else:
  76             SPR = SPRfull
  77
  78         self.spr_i = Signal(10, reset_less=True)
  79         self.spr_o = Data(SPR, name="spr_o")
  80         self.fast_o = Data(3, name="fast_o")
  81
  82     def elaborate(self, platform):
  83         m = Module()
  84         if self.regreduce_en:
  85             SPR = SPRreduced
  86         else:
  87             SPR = SPRfull
  88         with m.Switch(self.spr_i):
  89             for i, x in enumerate(SPR):
  90                 with m.Case(x.value):
  91                     m.d.comb += self.spr_o.data.eq(i)
  92                     m.d.comb += self.spr_o.ok.eq(1)
  93             for x, v in spr_to_fast.items():
  94                 with m.Case(x.value):
  95                     m.d.comb += self.fast_o.data.eq(v)
  96                     m.d.comb += self.fast_o.ok.eq(1)
  97         return m
  98
  99
 100 class DecodeA(Elaboratable):
 101     """DecodeA from instruction
 102
 103     decodes register RA, implicit and explicit CSRs
 104     """
 105
 106     def __init__(self, dec, op, regreduce_en):
 107         self.regreduce_en = regreduce_en
 108         if self.regreduce_en:
 109             SPR = SPRreduced
 110         else:
 111             SPR = SPRfull
 112         self.dec = dec
 113         self.op = op
 114         self.sel_in = Signal(In1Sel, reset_less=True)
 115         self.insn_in = Signal(32, reset_less=True)
 116         self.reg_out = Data(5, name="reg_a")
 117         self.spr_out = Data(SPR, "spr_a")
 118         self.fast_out = Data(3, "fast_a")
 119         self.sv_nz = Signal(1)
 120
 121     def elaborate(self, platform):
 122         m = Module()
 123         comb = m.d.comb
 124         op = self.op
 125         reg = self.reg_out
 126         m.submodules.sprmap = sprmap = SPRMap(self.regreduce_en)
 127
 128         # select Register A field, if *full 7 bits* are zero (2 more from SVP64)
 129         ra = Signal(5, reset_less=True)
 130         comb += ra.eq(self.dec.RA)
 131         with m.If((self.sel_in == In1Sel.RA) |
 132                   ((self.sel_in == In1Sel.RA_OR_ZERO) &
 133                    ((ra != Const(0, 5)) | (self.sv_nz != Const(0, 1))))):
 134             comb += reg.data.eq(ra)
 135             comb += reg.ok.eq(1)
 136
 137         # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
 138         # moved it to 1st position (in1_sel)... because
 139         rs = Signal(5, reset_less=True)
 140         comb += rs.eq(self.dec.RS)
 141         with m.If(self.sel_in == In1Sel.RS):
 142             comb += reg.data.eq(rs)
 143             comb += reg.ok.eq(1)
 144
 145         # select Register FRA field,
 146         fra = Signal(5, reset_less=True)
 147         comb += fra.eq(self.dec.FRA)
 148         with m.If(self.sel_in == In1Sel.FRA):
 149             comb += reg.data.eq(fra)
 150             comb += reg.ok.eq(1)
 151
 152         # select Register FRS field,
 153         frs = Signal(5, reset_less=True)
 154         comb += frs.eq(self.dec.FRS)
 155         with m.If(self.sel_in == In1Sel.FRS):
 156             comb += reg.data.eq(frs)
 157             comb += reg.ok.eq(1)
 158
 159         # decode Fast-SPR based on instruction type
 160         with m.Switch(op.internal_op):
 161
 162             # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
 163             with m.Case(MicrOp.OP_BC):
 164                 with m.If(~self.dec.BO[2]):  # 3.0B p38 BO2=0, use CTR reg
 165                     # constant: CTR
 166                     comb += self.fast_out.data.eq(FastRegsEnum.CTR)
 167                     comb += self.fast_out.ok.eq(1)
 168             with m.Case(MicrOp.OP_BCREG):
 169                 xo9 = self.dec.FormXL.XO[9]  # 3.0B p38 top bit of XO
 170                 xo5 = self.dec.FormXL.XO[5]  # 3.0B p38
 171                 with m.If(xo9 & ~xo5):
 172                     # constant: CTR
 173                     comb += self.fast_out.data.eq(FastRegsEnum.CTR)
 174                     comb += self.fast_out.ok.eq(1)
 175
 176             # MFSPR move from SPRs
 177             with m.Case(MicrOp.OP_MFSPR):
 178                 spr = Signal(10, reset_less=True)
 179                 comb += spr.eq(decode_spr_num(self.dec.SPR))  # from XFX
 180                 comb += sprmap.spr_i.eq(spr)
 181                 comb += self.spr_out.eq(sprmap.spr_o)
 182                 comb += self.fast_out.eq(sprmap.fast_o)
 183
 184         return m
 185
 186
 187 class DecodeAImm(Elaboratable):
 188     """DecodeA immediate from instruction
 189
 190     decodes register RA, whether immediate-zero, implicit and
 191     explicit CSRs.  SVP64 mode requires 2 extra bits
 192     """
 193
 194     def __init__(self, dec):
 195         self.dec = dec
 196         self.sel_in = Signal(In1Sel, reset_less=True)
 197         self.immz_out = Signal(reset_less=True)
 198         self.sv_nz = Signal(1) # EXTRA bits from SVP64
 199
 200     def elaborate(self, platform):
 201         m = Module()
 202         comb = m.d.comb
 203
 204         # zero immediate requested
 205         ra = Signal(5, reset_less=True)
 206         comb += ra.eq(self.dec.RA)
 207         with m.If((self.sel_in == In1Sel.RA_OR_ZERO) &
 208                     (ra == Const(0, 5)) &
 209                     (self.sv_nz == Const(0, 1))):
 210             comb += self.immz_out.eq(1)
 211
 212         return m
 213
 214
 215 class DecodeB(Elaboratable):
 216     """DecodeB from instruction
 217
 218     decodes register RB, different forms of immediate (signed, unsigned),
 219     and implicit SPRs.  register B is basically "lane 2" into the CompUnits.
 220     by industry-standard convention, "lane 2" is where fully-decoded
 221     immediates are muxed in.
 222     """
 223
 224     def __init__(self, dec, op):
 225         self.dec = dec
 226         self.op = op
 227         self.sel_in = Signal(In2Sel, reset_less=True)
 228         self.insn_in = Signal(32, reset_less=True)
 229         self.reg_out = Data(7, "reg_b")
 230         self.reg_isvec = Signal(1, name="reg_b_isvec") # TODO: in reg_out
 231         self.fast_out = Data(3, "fast_b")
 232
 233     def elaborate(self, platform):
 234         m = Module()
 235         comb = m.d.comb
 236         op = self.op
 237         reg = self.reg_out
 238
 239         # select Register B field
 240         with m.Switch(self.sel_in):
 241             with m.Case(In2Sel.FRB):
 242                 comb += reg.data.eq(self.dec.FRB)
 243                 comb += reg.ok.eq(1)
 244             with m.Case(In2Sel.RB):
 245                 comb += reg.data.eq(self.dec.RB)
 246                 comb += reg.ok.eq(1)
 247             with m.Case(In2Sel.RS):
 248                 # for M-Form shiftrot
 249                 comb += reg.data.eq(self.dec.RS)
 250                 comb += reg.ok.eq(1)
 251
 252         # decode SPR2 based on instruction type
 253         # BCREG implicitly uses LR or TAR for 2nd reg
 254         # CTR however is already in fast_spr1 *not* 2.
 255         with m.If(op.internal_op == MicrOp.OP_BCREG):
 256             xo9 = self.dec.FormXL.XO[9]  # 3.0B p38 top bit of XO
 257             xo5 = self.dec.FormXL.XO[5]  # 3.0B p38
 258             with m.If(~xo9):
 259                 comb += self.fast_out.data.eq(FastRegsEnum.LR)
 260                 comb += self.fast_out.ok.eq(1)
 261             with m.Elif(xo5):
 262                 comb += self.fast_out.data.eq(FastRegsEnum.TAR)
 263                 comb += self.fast_out.ok.eq(1)
 264
 265         return m
 266
 267
 268 class DecodeBImm(Elaboratable):
 269     """DecodeB immediate from instruction
 270     """
 271     def __init__(self, dec):
 272         self.dec = dec
 273         self.sel_in = Signal(In2Sel, reset_less=True)
 274         self.imm_out = Data(64, "imm_b")
 275
 276     def elaborate(self, platform):
 277         m = Module()
 278         comb = m.d.comb
 279
 280         # select Register B Immediate
 281         with m.Switch(self.sel_in):
 282             with m.Case(In2Sel.CONST_UI): # unsigned
 283                 comb += self.imm_out.data.eq(self.dec.UI)
 284                 comb += self.imm_out.ok.eq(1)
 285             with m.Case(In2Sel.CONST_SI):  # sign-extended 16-bit
 286                 si = Signal(16, reset_less=True)
 287                 comb += si.eq(self.dec.SI)
 288                 comb += self.imm_out.data.eq(exts(si, 16, 64))
 289                 comb += self.imm_out.ok.eq(1)
 290             with m.Case(In2Sel.CONST_SI_HI):  # sign-extended 16+16=32 bit
 291                 si_hi = Signal(32, reset_less=True)
 292                 comb += si_hi.eq(self.dec.SI << 16)
 293                 comb += self.imm_out.data.eq(exts(si_hi, 32, 64))
 294                 comb += self.imm_out.ok.eq(1)
 295             with m.Case(In2Sel.CONST_UI_HI): # unsigned
 296                 ui = Signal(16, reset_less=True)
 297                 comb += ui.eq(self.dec.UI)
 298                 comb += self.imm_out.data.eq(ui << 16)
 299                 comb += self.imm_out.ok.eq(1)
 300             with m.Case(In2Sel.CONST_LI): # sign-extend 24+2=26 bit
 301                 li = Signal(26, reset_less=True)
 302                 comb += li.eq(self.dec.LI << 2)
 303                 comb += self.imm_out.data.eq(exts(li, 26, 64))
 304                 comb += self.imm_out.ok.eq(1)
 305             with m.Case(In2Sel.CONST_BD): # sign-extend (14+2)=16 bit
 306                 bd = Signal(16, reset_less=True)
 307                 comb += bd.eq(self.dec.BD << 2)
 308                 comb += self.imm_out.data.eq(exts(bd, 16, 64))
 309                 comb += self.imm_out.ok.eq(1)
 310             with m.Case(In2Sel.CONST_DS): # sign-extended (14+2=16) bit
 311                 ds = Signal(16, reset_less=True)
 312                 comb += ds.eq(self.dec.DS << 2)
 313                 comb += self.imm_out.data.eq(exts(ds, 16, 64))
 314                 comb += self.imm_out.ok.eq(1)
 315             with m.Case(In2Sel.CONST_M1): # signed (-1)
 316                 comb += self.imm_out.data.eq(~Const(0, 64))  # all 1s
 317                 comb += self.imm_out.ok.eq(1)
 318             with m.Case(In2Sel.CONST_SH): # unsigned - for shift
 319                 comb += self.imm_out.data.eq(self.dec.sh)
 320                 comb += self.imm_out.ok.eq(1)
 321             with m.Case(In2Sel.CONST_SH32): # unsigned - for shift
 322                 comb += self.imm_out.data.eq(self.dec.SH32)
 323                 comb += self.imm_out.ok.eq(1)
 324
 325         return m
 326
 327
 328 class DecodeC(Elaboratable):
 329     """DecodeC from instruction
 330
 331     decodes register RC.  this is "lane 3" into some CompUnits (not many)
 332     """
 333
 334     def __init__(self, dec, op):
 335         self.dec = dec
 336         self.op = op
 337         self.sel_in = Signal(In3Sel, reset_less=True)
 338         self.insn_in = Signal(32, reset_less=True)
 339         self.reg_out = Data(5, "reg_c")
 340
 341     def elaborate(self, platform):
 342         m = Module()
 343         comb = m.d.comb
 344         op = self.op
 345         reg = self.reg_out
 346
 347         # select Register C field
 348         with m.Switch(self.sel_in):
 349             with m.Case(In3Sel.RB):
 350                 # for M-Form shiftrot
 351                 comb += reg.data.eq(self.dec.RB)
 352                 comb += reg.ok.eq(1)
 353             with m.Case(In3Sel.FRS):
 354                 comb += reg.data.eq(self.dec.FRS)
 355                 comb += reg.ok.eq(1)
 356             with m.Case(In3Sel.FRC):
 357                 comb += reg.data.eq(self.dec.FRC)
 358                 comb += reg.ok.eq(1)
 359             with m.Case(In3Sel.RS):
 360                 comb += reg.data.eq(self.dec.RS)
 361                 comb += reg.ok.eq(1)
 362             with m.Case(In3Sel.RC):
 363                 comb += reg.data.eq(self.dec.RC)
 364                 comb += reg.ok.eq(1)
 365
 366         return m
 367
 368
 369 class DecodeOut(Elaboratable):
 370     """DecodeOut from instruction
 371
 372     decodes output register RA, RT or SPR
 373     """
 374
 375     def __init__(self, dec, op, regreduce_en):
 376         self.regreduce_en = regreduce_en
 377         if self.regreduce_en:
 378             SPR = SPRreduced
 379         else:
 380             SPR = SPRfull
 381         self.dec = dec
 382         self.op = op
 383         self.sel_in = Signal(OutSel, reset_less=True)
 384         self.insn_in = Signal(32, reset_less=True)
 385         self.reg_out = Data(5, "reg_o")
 386         self.spr_out = Data(SPR, "spr_o")
 387         self.fast_out = Data(3, "fast_o")
 388
 389     def elaborate(self, platform):
 390         m = Module()
 391         comb = m.d.comb
 392         m.submodules.sprmap = sprmap = SPRMap(self.regreduce_en)
 393         op = self.op
 394         reg = self.reg_out
 395
 396         # select Register out field
 397         with m.Switch(self.sel_in):
 398             with m.Case(OutSel.FRT):
 399                 comb += reg.data.eq(self.dec.FRT)
 400                 comb += reg.ok.eq(1)
 401             with m.Case(OutSel.RT):
 402                 comb += reg.data.eq(self.dec.RT)
 403                 comb += reg.ok.eq(1)
 404             with m.Case(OutSel.RA):
 405                 comb += reg.data.eq(self.dec.RA)
 406                 comb += reg.ok.eq(1)
 407             with m.Case(OutSel.SPR):
 408                 spr = Signal(10, reset_less=True)
 409                 comb += spr.eq(decode_spr_num(self.dec.SPR))  # from XFX
 410                 # MFSPR move to SPRs - needs mapping
 411                 with m.If(op.internal_op == MicrOp.OP_MTSPR):
 412                     comb += sprmap.spr_i.eq(spr)
 413                     comb += self.spr_out.eq(sprmap.spr_o)
 414                     comb += self.fast_out.eq(sprmap.fast_o)
 415
 416         # determine Fast Reg
 417         with m.Switch(op.internal_op):
 418
 419             # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
 420             with m.Case(MicrOp.OP_BC, MicrOp.OP_BCREG):
 421                 with m.If(~self.dec.BO[2]):  # 3.0B p38 BO2=0, use CTR reg
 422                     # constant: CTR
 423                     comb += self.fast_out.data.eq(FastRegsEnum.CTR)
 424                     comb += self.fast_out.ok.eq(1)
 425
 426             # RFID 1st spr (fast)
 427             with m.Case(MicrOp.OP_RFID):
 428                 comb += self.fast_out.data.eq(FastRegsEnum.SRR0)  # SRR0
 429                 comb += self.fast_out.ok.eq(1)
 430
 431         return m
 432
 433
 434 class DecodeOut2(Elaboratable):
 435     """DecodeOut2 from instruction
 436
 437     decodes output registers (2nd one).  note that RA is *implicit* below,
 438     which now causes problems with SVP64
 439
 440     TODO: SVP64 is a little more complex, here.  svp64 allows extending
 441     by one more destination by having one more EXTRA field.  RA-as-src
 442     is not the same as RA-as-dest.  limited in that it's the same first
 443     5 bits (from the v3.0B opcode), but still kinda cool.  mostly used
 444     for operations that have src-as-dest: mostly this is LD/ST-with-update
 445     but there are others.
 446     """
 447
 448     def __init__(self, dec, op):
 449         self.dec = dec
 450         self.op = op
 451         self.sel_in = Signal(OutSel, reset_less=True)
 452         self.lk = Signal(reset_less=True)
 453         self.insn_in = Signal(32, reset_less=True)
 454         self.reg_out = Data(5, "reg_o2")
 455         self.fast_out = Data(3, "fast_o2")
 456         self.fast_out3 = Data(3, "fast_o3")
 457
 458     def elaborate(self, platform):
 459         m = Module()
 460         comb = m.d.comb
 461         op = self.op
 462         #m.submodules.svdec = svdec = SVP64RegExtra()
 463
 464         # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
 465         #reg = Signal(5, reset_less=True)
 466
 467         if hasattr(op, "upd"):
 468             # update mode LD/ST uses read-reg A also as an output
 469             with m.If(op.upd == LDSTMode.update):
 470                 comb += self.reg_out.data.eq(self.dec.RA)
 471                 comb += self.reg_out.ok.eq(1)
 472
 473         # B, BC or BCREG: potential implicit register (LR) output
 474         # these give bl, bcl, bclrl, etc.
 475         with m.Switch(op.internal_op):
 476
 477             # BC* implicit register (LR)
 478             with m.Case(MicrOp.OP_BC, MicrOp.OP_B, MicrOp.OP_BCREG):
 479                 with m.If(self.lk):  # "link" mode
 480                     comb += self.fast_out.data.eq(FastRegsEnum.LR)  # LR
 481                     comb += self.fast_out.ok.eq(1)
 482
 483             # RFID 2nd and 3rd spr (fast)
 484             with m.Case(MicrOp.OP_RFID):
 485                 comb += self.fast_out.data.eq(FastRegsEnum.SRR1)  # SRR1
 486                 comb += self.fast_out.ok.eq(1)
 487                 comb += self.fast_out3.data.eq(FastRegsEnum.SVSRR0) # SVSRR0
 488                 comb += self.fast_out3.ok.eq(1)
 489
 490         return m
 491
 492
 493 class DecodeRC(Elaboratable):
 494     """DecodeRc from instruction
 495
 496     decodes Record bit Rc
 497     """
 498
 499     def __init__(self, dec):
 500         self.dec = dec
 501         self.sel_in = Signal(RC, reset_less=True)
 502         self.insn_in = Signal(32, reset_less=True)
 503         self.rc_out = Data(1, "rc")
 504
 505     def elaborate(self, platform):
 506         m = Module()
 507         comb = m.d.comb
 508
 509         # select Record bit out field
 510         with m.Switch(self.sel_in):
 511             with m.Case(RC.RC):
 512                 comb += self.rc_out.data.eq(self.dec.Rc)
 513                 comb += self.rc_out.ok.eq(1)
 514             with m.Case(RC.ONE):
 515                 comb += self.rc_out.data.eq(1)
 516                 comb += self.rc_out.ok.eq(1)
 517             with m.Case(RC.NONE):
 518                 comb += self.rc_out.data.eq(0)
 519                 comb += self.rc_out.ok.eq(1)
 520
 521         return m
 522
 523
 524 class DecodeOE(Elaboratable):
 525     """DecodeOE from instruction
 526
 527     decodes OE field: uses RC decode detection which might not be good
 528
 529     -- For now, use "rc" in the decode table to decide whether oe exists.
 530     -- This is not entirely correct architecturally: For mulhd and
 531     -- mulhdu, the OE field is reserved. It remains to be seen what an
 532     -- actual POWER9 does if we set it on those instructions, for now we
 533     -- test that further down when assigning to the multiplier oe input.
 534     """
 535
 536     def __init__(self, dec, op):
 537         self.dec = dec
 538         self.op = op
 539         self.sel_in = Signal(RC, reset_less=True)
 540         self.insn_in = Signal(32, reset_less=True)
 541         self.oe_out = Data(1, "oe")
 542
 543     def elaborate(self, platform):
 544         m = Module()
 545         comb = m.d.comb
 546         op = self.op
 547
 548         with m.Switch(op.internal_op):
 549
 550             # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE
 551             # also rotate
 552             # XXX ARGH! ignoring OE causes incompatibility with microwatt
 553             # http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-August/000302.html
 554             with m.Case(MicrOp.OP_MUL_H64, MicrOp.OP_MUL_H32,
 555                         MicrOp.OP_EXTS, MicrOp.OP_CNTZ,
 556                         MicrOp.OP_SHL, MicrOp.OP_SHR, MicrOp.OP_RLC,
 557                         MicrOp.OP_LOAD, MicrOp.OP_STORE,
 558                         MicrOp.OP_RLCL, MicrOp.OP_RLCR,
 559                         MicrOp.OP_EXTSWSLI):
 560                 pass
 561
 562             # all other ops decode OE field
 563             with m.Default():
 564                 # select OE bit out field
 565                 with m.Switch(self.sel_in):
 566                     with m.Case(RC.RC):
 567                         comb += self.oe_out.data.eq(self.dec.OE)
 568                         comb += self.oe_out.ok.eq(1)
 569
 570         return m
 571
 572
 573 class DecodeCRIn(Elaboratable):
 574     """Decodes input CR from instruction
 575
 576     CR indices - insn fields - (not the data *in* the CR) require only 3
 577     bits because they refer to CR0-CR7
 578     """
 579
 580     def __init__(self, dec, op):
 581         self.dec = dec
 582         self.op = op
 583         self.sel_in = Signal(CRInSel, reset_less=True)
 584         self.insn_in = Signal(32, reset_less=True)
 585         self.cr_bitfield = Data(3, "cr_bitfield")
 586         self.cr_bitfield_b = Data(3, "cr_bitfield_b")
 587         self.cr_bitfield_o = Data(3, "cr_bitfield_o")
 588         self.whole_reg = Data(8,  "cr_fxm")
 589         self.sv_override = Signal(2, reset_less=True) # do not do EXTRA spec
 590
 591     def elaborate(self, platform):
 592         m = Module()
 593         comb = m.d.comb
 594         op = self.op
 595         m.submodules.ppick = ppick = PriorityPicker(8, reverse_i=True,
 596                                                        reverse_o=True)
 597
 598         # zero-initialisation
 599         comb += self.cr_bitfield.ok.eq(0)
 600         comb += self.cr_bitfield_b.ok.eq(0)
 601         comb += self.cr_bitfield_o.ok.eq(0)
 602         comb += self.whole_reg.ok.eq(0)
 603         comb += self.sv_override.eq(0)
 604
 605         # select the relevant CR bitfields
 606         with m.Switch(self.sel_in):
 607             with m.Case(CRInSel.NONE):
 608                 pass  # No bitfield activated
 609             with m.Case(CRInSel.CR0):
 610                 comb += self.cr_bitfield.data.eq(0) # CR0 (MSB0 numbering)
 611                 comb += self.cr_bitfield.ok.eq(1)
 612                 comb += self.sv_override.eq(1)
 613             with m.Case(CRInSel.CR1):
 614                 comb += self.cr_bitfield.data.eq(1) # CR1 (MSB0 numbering)
 615                 comb += self.cr_bitfield.ok.eq(1)
 616                 comb += self.sv_override.eq(2)
 617             with m.Case(CRInSel.BI):
 618                 comb += self.cr_bitfield.data.eq(self.dec.BI[2:5])
 619                 comb += self.cr_bitfield.ok.eq(1)
 620             with m.Case(CRInSel.BFA):
 621                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BFA)
 622                 comb += self.cr_bitfield.ok.eq(1)
 623             with m.Case(CRInSel.BA_BB):
 624                 comb += self.cr_bitfield.data.eq(self.dec.BA[2:5])
 625                 comb += self.cr_bitfield.ok.eq(1)
 626                 comb += self.cr_bitfield_b.data.eq(self.dec.BB[2:5])
 627                 comb += self.cr_bitfield_b.ok.eq(1)
 628                 comb += self.cr_bitfield_o.data.eq(self.dec.BT[2:5])
 629                 comb += self.cr_bitfield_o.ok.eq(1)
 630             with m.Case(CRInSel.BC):
 631                 comb += self.cr_bitfield.data.eq(self.dec.BC[2:5])
 632                 comb += self.cr_bitfield.ok.eq(1)
 633             with m.Case(CRInSel.WHOLE_REG):
 634                 comb += self.whole_reg.ok.eq(1)
 635                 move_one = Signal(reset_less=True)
 636                 comb += move_one.eq(self.insn_in[20]) # MSB0 bit 11
 637                 with m.If((op.internal_op == MicrOp.OP_MFCR) & move_one):
 638                     # must one-hot the FXM field
 639                     comb += ppick.i.eq(self.dec.FXM)
 640                     comb += self.whole_reg.data.eq(ppick.o)
 641                 with m.Else():
 642                     # otherwise use all of it
 643                     comb += self.whole_reg.data.eq(0xff)
 644
 645         return m
 646
 647
 648 class DecodeCROut(Elaboratable):
 649     """Decodes input CR from instruction
 650
 651     CR indices - insn fields - (not the data *in* the CR) require only 3
 652     bits because they refer to CR0-CR7
 653     """
 654
 655     def __init__(self, dec, op):
 656         self.dec = dec
 657         self.op = op
 658         self.rc_in = Signal(reset_less=True)
 659         self.sel_in = Signal(CROutSel, reset_less=True)
 660         self.insn_in = Signal(32, reset_less=True)
 661         self.cr_bitfield = Data(3, "cr_bitfield")
 662         self.whole_reg = Data(8,  "cr_fxm")
 663         self.sv_override = Signal(2, reset_less=True) # do not do EXTRA spec
 664
 665     def elaborate(self, platform):
 666         m = Module()
 667         comb = m.d.comb
 668         op = self.op
 669         m.submodules.ppick = ppick = PriorityPicker(8, reverse_i=True,
 670                                                        reverse_o=True)
 671
 672         comb += self.cr_bitfield.ok.eq(0)
 673         comb += self.whole_reg.ok.eq(0)
 674         comb += self.sv_override.eq(0)
 675
 676         # please note these MUST match (setting of cr_bitfield.ok) exactly
 677         # with write_cr0 below in PowerDecoder2.  the reason it's separated
 678         # is to avoid having duplicate copies of DecodeCROut in multiple
 679         # PowerDecoderSubsets.  register decoding should be a one-off in
 680         # PowerDecoder2.  see https://bugs.libre-soc.org/show_bug.cgi?id=606
 681
 682         with m.Switch(self.sel_in):
 683             with m.Case(CROutSel.NONE):
 684                 pass  # No bitfield activated
 685             with m.Case(CROutSel.CR0):
 686                 comb += self.cr_bitfield.data.eq(0) # CR0 (MSB0 numbering)
 687                 comb += self.cr_bitfield.ok.eq(self.rc_in)  # only when RC=1
 688                 comb += self.sv_override.eq(1)
 689             with m.Case(CROutSel.CR1):
 690                 comb += self.cr_bitfield.data.eq(1) # CR1 (MSB0 numbering)
 691                 comb += self.cr_bitfield.ok.eq(self.rc_in)  # only when RC=1
 692                 comb += self.sv_override.eq(2)
 693             with m.Case(CROutSel.BF):
 694                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BF)
 695                 comb += self.cr_bitfield.ok.eq(1)
 696             with m.Case(CROutSel.BT):
 697                 comb += self.cr_bitfield.data.eq(self.dec.FormXL.BT[2:5])
 698                 comb += self.cr_bitfield.ok.eq(1)
 699             with m.Case(CROutSel.WHOLE_REG):
 700                 comb += self.whole_reg.ok.eq(1)
 701                 move_one = Signal(reset_less=True)
 702                 comb += move_one.eq(self.insn_in[20])
 703                 with m.If((op.internal_op == MicrOp.OP_MTCRF)):
 704                     with m.If(move_one):
 705                         # must one-hot the FXM field
 706                         comb += ppick.i.eq(self.dec.FXM)
 707                         with m.If(ppick.en_o):
 708                             comb += self.whole_reg.data.eq(ppick.o)
 709                         with m.Else():
 710                             comb += self.whole_reg.data.eq(0b00000001) # CR7
 711                     with m.Else():
 712                         comb += self.whole_reg.data.eq(self.dec.FXM)
 713                 with m.Else():
 714                     # otherwise use all of it
 715                     comb += self.whole_reg.data.eq(0xff)
 716
 717         return m
 718
 719 # dictionary of Input Record field names that, if they exist,
 720 # will need a corresponding CSV Decoder file column (actually, PowerOp)
 721 # to be decoded (this includes the single bit names)
 722 record_names = {'insn_type': 'internal_op',
 723                 'fn_unit': 'function_unit',
 724                 'SV_Ptype': 'SV_Ptype',
 725                 'rc': 'rc_sel',
 726                 'oe': 'rc_sel',
 727                 'zero_a': 'in1_sel',
 728                 'imm_data': 'in2_sel',
 729                 'invert_in': 'inv_a',
 730                 'invert_out': 'inv_out',
 731                 'rc': 'cr_out',
 732                 'oe': 'cr_in',
 733                 'output_carry': 'cry_out',
 734                 'input_carry': 'cry_in',
 735                 'is_32bit': 'is_32b',
 736                 'is_signed': 'sgn',
 737                 'lk': 'lk',
 738                 'data_len': 'ldst_len',
 739                 'byte_reverse': 'br',
 740                 'sign_extend': 'sgn_ext',
 741                 'ldst_mode': 'upd',
 742                 }
 743
 744
 745 class PowerDecodeSubset(Elaboratable):
 746     """PowerDecodeSubset: dynamic subset decoder
 747
 748     only fields actually requested are copied over. hence, "subset" (duh).
 749     """
 750     def __init__(self, dec, opkls=None, fn_name=None, final=False, state=None,
 751                             svp64_en=True, regreduce_en=False):
 752
 753         self.svp64_en = svp64_en
 754         self.regreduce_en = regreduce_en
 755         if svp64_en:
 756             self.is_svp64_mode = Signal() # mark decoding as SVP64 Mode
 757             self.use_svp64_ldst_dec = Signal() # must use LDST decoder
 758             self.sv_rm = SVP64Rec(name="dec_svp64") # SVP64 RM field
 759             self.rm_dec = SVP64RMModeDecode("svp64_rm_dec")
 760             # set these to the predicate mask bits needed for the ALU
 761             self.pred_sm = Signal() # TODO expand to SIMD mask width
 762             self.pred_dm = Signal() # TODO expand to SIMD mask width
 763         self.sv_a_nz = Signal(1)
 764         self.final = final
 765         self.opkls = opkls
 766         self.fn_name = fn_name
 767         if opkls is None:
 768             opkls = Decode2ToOperand
 769         self.do = opkls(fn_name)
 770         col_subset = self.get_col_subset(self.do)
 771
 772         # only needed for "main" PowerDecode2
 773         if not self.final:
 774             self.e = Decode2ToExecute1Type(name=self.fn_name, do=self.do,
 775                                            regreduce_en=regreduce_en)
 776
 777         # create decoder if one not already given
 778         if dec is None:
 779             dec = create_pdecode(name=fn_name, col_subset=col_subset,
 780                                       row_subset=self.rowsubsetfn)
 781         self.dec = dec
 782
 783         # create SVP64 LDST decoder
 784         if svp64_en and (not final or fn_name.lower().startswith("ldst")):
 785             if fn_name:
 786                 name = "sv_"+fn_name
 787             else:
 788                 name = "svdec"
 789             svdecldst = create_pdecode_svp64_ldst(name=name,
 790                                               col_subset=col_subset,
 791                                               row_subset=self.rowsubsetfn)
 792             self.svdecldst = svdecldst
 793         else:
 794             self.svdecldst = None
 795
 796         # set up a copy of the PowerOp
 797         self.op = PowerOp.like(self.dec.op)
 798
 799         # state information needed by the Decoder
 800         if state is None:
 801             state = CoreState("dec2")
 802         self.state = state
 803
 804     def get_col_subset(self, do):
 805         subset = { 'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
 806         for k, v in record_names.items():
 807             if hasattr(do, k):
 808                 subset.add(v)
 809         log ("get_col_subset", self.fn_name, do.fields, subset)
 810         return subset
 811
 812     def rowsubsetfn(self, opcode, row):
 813         """select per-Function-Unit subset of opcodes to be processed
 814
 815         normally this just looks at the "unit" column.  MMU is different
 816         in that it processes specific SPR set/get operations that the SPR
 817         pipeline should not.
 818         """
 819         return (row['unit'] == self.fn_name or
 820                 # sigh a dreadful hack: MTSPR and MFSPR need to be processed
 821                 # by the MMU pipeline so we direct those opcodes to MMU **AND**
 822                 # SPR pipelines, then selectively weed out the SPRs that should
 823                 # or should not not go to each pipeline, further down.
 824                 # really this should be done by modifying the CSV syntax
 825                 # to support multiple tasks (unit column multiple entries)
 826                 # see https://bugs.libre-soc.org/show_bug.cgi?id=310
 827                (self.fn_name == 'MMU' and row['unit'] == 'SPR' and
 828                 row['internal op'] in ['OP_MTSPR', 'OP_MFSPR'])
 829                 )
 830
 831     def ports(self):
 832         ports = self.dec.ports() + self.e.ports()
 833         if self.svp64_en:
 834             ports += self.sv_rm.ports()
 835         if self.svdecldst:
 836             ports += self.svdecldst.ports()
 837         return ports
 838
 839     def needs_field(self, field, op_field):
 840         if self.final:
 841             do = self.do
 842         else:
 843             do = self.e_tmp.do
 844         return hasattr(do, field) and self.op_get(op_field) is not None
 845
 846     def do_get(self, field, final=False):
 847         if final or self.final:
 848             do = self.do
 849         else:
 850             do = self.e_tmp.do
 851         return getattr(do, field, None)
 852
 853     def do_copy(self, field, val, final=False):
 854         df = self.do_get(field, final)
 855         if df is not None and val is not None:
 856             return df.eq(val)
 857         return []
 858
 859     def op_get(self, op_field):
 860         return getattr(self.op, op_field, None)
 861
 862     def elaborate(self, platform):
 863         if self.regreduce_en:
 864             SPR = SPRreduced
 865         else:
 866             SPR = SPRfull
 867         m = Module()
 868         comb = m.d.comb
 869         state = self.state
 870         op, do = self.dec.op, self.do
 871         msr, cia, svstate = state.msr, state.pc, state.svstate
 872         # fill in for a normal instruction (not an exception)
 873         # copy over if non-exception, non-privileged etc. is detected
 874         if not self.final:
 875             if self.fn_name is None:
 876                 name = "tmp"
 877             else:
 878                 name = self.fn_name + "tmp"
 879             self.e_tmp = Decode2ToExecute1Type(name=name, opkls=self.opkls,
 880                                            regreduce_en=self.regreduce_en)
 881
 882         # set up submodule decoders
 883         m.submodules.dec = self.dec
 884         m.submodules.dec_rc = self.dec_rc = dec_rc = DecodeRC(self.dec)
 885         m.submodules.dec_oe = dec_oe = DecodeOE(self.dec, op)
 886
 887         # use op from first decoder (self.dec.op) if not in SVP64-LDST mode
 888         # (TODO)
 889         comb += self.op.eq(self.dec.op)
 890
 891         if self.svp64_en:
 892             # and SVP64 RM mode decoder
 893             m.submodules.sv_rm_dec = rm_dec = self.rm_dec
 894         if self.svdecldst:
 895             # and SVP64 decoder
 896             m.submodules.svdecldst = svdecldst = self.svdecldst
 897
 898         # copy instruction through...
 899         for i in [do.insn, dec_rc.insn_in, dec_oe.insn_in, ]:
 900             comb += i.eq(self.dec.opcode_in)
 901
 902         # ...and subdecoders' input fields
 903         comb += dec_rc.sel_in.eq(self.op_get("rc_sel"))
 904         comb += dec_oe.sel_in.eq(self.op_get("rc_sel"))  # XXX should be OE sel
 905
 906         # copy "state" over
 907         comb += self.do_copy("msr", msr)
 908         comb += self.do_copy("cia", cia)
 909         comb += self.do_copy("svstate", svstate)
 910
 911         # set up instruction type
 912         # no op: defaults to OP_ILLEGAL
 913         internal_op = self.op_get("internal_op")
 914         comb += self.do_copy("insn_type", internal_op)
 915
 916         # function unit for decoded instruction: requires minor redirect
 917         # for SPR set/get
 918         fn = self.op_get("function_unit")
 919         spr = Signal(10, reset_less=True)
 920         comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
 921
 922         # Microwatt doesn't implement the partition table
 923         # instead has PRTBL register (SPR) to point to process table
 924         is_spr_mv = Signal()
 925         is_mmu_spr = Signal()
 926         comb += is_spr_mv.eq((internal_op == MicrOp.OP_MTSPR) |
 927                              (internal_op == MicrOp.OP_MFSPR))
 928         comb += is_mmu_spr.eq((spr == SPR.DSISR.value) |
 929                               (spr == SPR.DAR.value) |
 930                               (spr == SPR.PRTBL.value) |
 931                               (spr == SPR.PIDR.value))
 932         # MMU must receive MMU SPRs
 933         with m.If(is_spr_mv & (fn == Function.SPR) & is_mmu_spr):
 934             comb += self.do_copy("fn_unit", Function.NONE)
 935             comb += self.do_copy("insn_type", MicrOp.OP_ILLEGAL)
 936         # SPR pipe must *not* receive MMU SPRs
 937         with m.Elif(is_spr_mv & (fn == Function.MMU) & ~is_mmu_spr):
 938             comb += self.do_copy("fn_unit", Function.NONE)
 939             comb += self.do_copy("insn_type", MicrOp.OP_ILLEGAL)
 940         # all others ok
 941         with m.Else():
 942             comb += self.do_copy("fn_unit", fn)
 943
 944         # immediates
 945         if self.needs_field("zero_a", "in1_sel"):
 946             m.submodules.dec_ai = dec_ai = DecodeAImm(self.dec)
 947             comb += dec_ai.sv_nz.eq(self.sv_a_nz)
 948             comb += dec_ai.sel_in.eq(self.op_get("in1_sel"))
 949             comb += self.do_copy("zero_a", dec_ai.immz_out)  # RA==0 detected
 950         if self.needs_field("imm_data", "in2_sel"):
 951             m.submodules.dec_bi = dec_bi = DecodeBImm(self.dec)
 952             comb += dec_bi.sel_in.eq(self.op_get("in2_sel"))
 953             comb += self.do_copy("imm_data", dec_bi.imm_out) # imm in RB
 954
 955         # rc and oe out
 956         comb += self.do_copy("rc", dec_rc.rc_out)
 957         comb += self.do_copy("oe", dec_oe.oe_out)
 958
 959         # CR in/out - note: these MUST match with what happens in
 960         # DecodeCROut!
 961         rc_out = self.dec_rc.rc_out.data
 962         with m.Switch(self.op_get("cr_out")):
 963             with m.Case(CROutSel.CR0, CROutSel.CR1):
 964                 comb += self.do_copy("write_cr0", rc_out) # only when RC=1
 965             with m.Case(CROutSel.BF, CROutSel.BT):
 966                 comb += self.do_copy("write_cr0", 1)
 967
 968         comb += self.do_copy("input_cr", self.op_get("cr_in"))   # CR in
 969         comb += self.do_copy("output_cr", self.op_get("cr_out"))  # CR out
 970
 971         if self.svp64_en:
 972             # connect up SVP64 RM Mode decoding.  however... we need a shorter
 973             # path, for the LDST bit-reverse detection.  so perform partial
 974             # decode when SVP64 is detected.  then, bit-reverse mode can be
 975             # quickly determined, and the Decoder result MUXed over to
 976             # the alternative decoder, svdecldst. what a mess... *sigh*
 977             sv_ptype = self.op_get("SV_Ptype")
 978             fn = self.op_get("function_unit")
 979             # detect major opcode for LDs: include 58 here. from CSV files.
 980             is_major_ld = Signal()
 981             major = Signal(6) # bits... errr... MSB0 0..5 which is 26:32 python
 982             comb += major.eq(self.dec.opcode_in[26:32])
 983             comb += is_major_ld.eq((major == 34) | (major == 35) |
 984                                    (major == 50) | (major == 51) |
 985                                    (major == 48) | (major == 49) |
 986                                    (major == 42) | (major == 43) |
 987                                    (major == 40) | (major == 41) |
 988                                    (major == 32) | (major == 33) |
 989                                    (major == 58))
 990             with m.If(self.is_svp64_mode & is_major_ld):
 991                 # straight-up: "it's a LD"
 992                 comb += rm_dec.fn_in.eq(Function.LDST)
 993             with m.Else():
 994                 comb += rm_dec.fn_in.eq(fn) # decode needs to know Fn type
 995             comb += rm_dec.ptype_in.eq(sv_ptype) # Single/Twin predicated
 996             comb += rm_dec.rc_in.eq(rc_out) # Rc=1
 997             comb += rm_dec.rm_in.eq(self.sv_rm) # SVP64 RM mode
 998             if self.needs_field("imm_data", "in2_sel"):
 999                 bzero = dec_bi.imm_out.ok & ~dec_bi.imm_out.data.bool()
1000                 comb += rm_dec.ldst_imz_in.eq(bzero) # B immediate is zero
1001             # main PowerDecoder2 determines if bit-reverse mode requested
1002             if not self.final:
1003                 bitrev = rm_dec.ldstmode == SVP64LDSTmode.BITREVERSE
1004                 comb += self.use_svp64_ldst_dec.eq(bitrev)
1005
1006         # decoded/selected instruction flags
1007         comb += self.do_copy("data_len", self.op_get("ldst_len"))
1008         comb += self.do_copy("invert_in", self.op_get("inv_a"))
1009         comb += self.do_copy("invert_out", self.op_get("inv_out"))
1010         comb += self.do_copy("input_carry", self.op_get("cry_in"))
1011         comb += self.do_copy("output_carry", self.op_get("cry_out"))
1012         comb += self.do_copy("is_32bit", self.op_get("is_32b"))
1013         comb += self.do_copy("is_signed", self.op_get("sgn"))
1014         lk = self.op_get("lk")
1015         if lk is not None:
1016             with m.If(lk):
1017                 comb += self.do_copy("lk", self.dec.LK)  # XXX TODO: accessor
1018
1019         comb += self.do_copy("byte_reverse", self.op_get("br"))
1020         comb += self.do_copy("sign_extend", self.op_get("sgn_ext"))
1021         comb += self.do_copy("ldst_mode", self.op_get("upd"))  # LD/ST mode
1022
1023         # copy over SVP64 input record fields (if they exist)
1024         if self.svp64_en:
1025             # TODO, really do we have to do these explicitly?? sigh
1026             #for (field, _) in sv_input_record_layout:
1027             #    comb += self.do_copy(field, self.rm_dec.op_get(field))
1028             comb += self.do_copy("sv_saturate", self.rm_dec.saturate)
1029             comb += self.do_copy("sv_Ptype", self.rm_dec.ptype_in)
1030             comb += self.do_copy("sv_ldstmode", self.rm_dec.ldstmode)
1031             # these get set up based on incoming mask bits.  TODO:
1032             # pass in multiple bits (later, when SIMD backends are enabled)
1033             with m.If(self.rm_dec.pred_sz):
1034                 comb += self.do_copy("sv_pred_sz", ~self.pred_sm)
1035             with m.If(self.rm_dec.pred_dz):
1036                 comb += self.do_copy("sv_pred_dz", ~self.pred_dm)
1037
1038         return m
1039
1040
1041 class PowerDecode2(PowerDecodeSubset):
1042     """PowerDecode2: the main instruction decoder.
1043
1044     whilst PowerDecode is responsible for decoding the actual opcode, this
1045     module encapsulates further specialist, sparse information and
1046     expansion of fields that is inconvenient to have in the CSV files.
1047     for example: the encoding of the immediates, which are detected
1048     and expanded out to their full value from an annotated (enum)
1049     representation.
1050
1051     implicit register usage is also set up, here.  for example: OP_BC
1052     requires implicitly reading CTR, OP_RFID requires implicitly writing
1053     to SRR1 and so on.
1054
1055     in addition, PowerDecoder2 is responsible for detecting whether
1056     instructions are illegal (or privileged) or not, and instead of
1057     just leaving at that, *replacing* the instruction to execute with
1058     a suitable alternative (trap).
1059
1060     LDSTExceptions are done the cycle _after_ they're detected (after
1061     they come out of LDSTCompUnit).  basically despite the instruction
1062     being decoded, the results of the decode are completely ignored
1063     and "exception.happened" used to set the "actual" instruction to
1064     "OP_TRAP".  the LDSTException data structure gets filled in,
1065     in the CompTrapOpSubset and that's what it fills in SRR.
1066
1067     to make this work, TestIssuer must notice "exception.happened"
1068     after the (failed) LD/ST and copies the LDSTException info from
1069     the output, into here (PowerDecoder2).  without incrementing PC.
1070     """
1071
1072     def __init__(self, dec, opkls=None, fn_name=None, final=False,
1073                             state=None, svp64_en=True, regreduce_en=False):
1074         super().__init__(dec, opkls, fn_name, final, state, svp64_en,
1075                          regreduce_en=False)
1076         self.ldst_exc = LDSTException("dec2_exc")
1077
1078         if self.svp64_en:
1079             self.cr_out_isvec = Signal(1, name="cr_out_isvec")
1080             self.cr_in_isvec = Signal(1, name="cr_in_isvec")
1081             self.cr_in_b_isvec = Signal(1, name="cr_in_b_isvec")
1082             self.cr_in_o_isvec = Signal(1, name="cr_in_o_isvec")
1083             self.in1_isvec = Signal(1, name="reg_a_isvec")
1084             self.in2_isvec = Signal(1, name="reg_b_isvec")
1085             self.in3_isvec = Signal(1, name="reg_c_isvec")
1086             self.o_isvec = Signal(1, name="reg_o_isvec")
1087             self.o2_isvec = Signal(1, name="reg_o2_isvec")
1088             self.no_in_vec = Signal(1, name="no_in_vec") # no inputs vector
1089             self.no_out_vec = Signal(1, name="no_out_vec") # no outputs vector
1090             self.loop_continue = Signal(1, name="loop_continue")
1091         else:
1092             self.no_in_vec = Const(1, 1)
1093             self.no_out_vec = Const(1, 1)
1094             self.loop_continue = Const(0, 1)
1095
1096     def get_col_subset(self, opkls):
1097         subset = super().get_col_subset(opkls)
1098         subset.add("asmcode")
1099         subset.add("in1_sel")
1100         subset.add("in2_sel")
1101         subset.add("in3_sel")
1102         subset.add("out_sel")
1103         if self.svp64_en:
1104             subset.add("sv_in1")
1105             subset.add("sv_in2")
1106             subset.add("sv_in3")
1107             subset.add("sv_out")
1108             subset.add("sv_out2")
1109             subset.add("sv_cr_in")
1110             subset.add("sv_cr_out")
1111             subset.add("SV_Etype")
1112             subset.add("SV_Ptype")
1113             # from SVP64RMModeDecode
1114             for (field, _) in sv_input_record_layout:
1115                 subset.add(field)
1116         subset.add("lk")
1117         subset.add("internal_op")
1118         subset.add("form")
1119         return subset
1120
1121     def elaborate(self, platform):
1122         m = super().elaborate(platform)
1123         comb = m.d.comb
1124         state = self.state
1125         op, e_out, do_out = self.op, self.e, self.e.do
1126         dec_spr, msr, cia, ext_irq = state.dec, state.msr, state.pc, state.eint
1127         rc_out = self.dec_rc.rc_out.data
1128         e = self.e_tmp
1129         do = e.do
1130
1131         # fill in for a normal instruction (not an exception)
1132         # copy over if non-exception, non-privileged etc. is detected
1133
1134         # set up submodule decoders
1135         m.submodules.dec_a = dec_a = DecodeA(self.dec, op, self.regreduce_en)
1136         m.submodules.dec_b = dec_b = DecodeB(self.dec, op)
1137         m.submodules.dec_c = dec_c = DecodeC(self.dec, op)
1138         m.submodules.dec_o = dec_o = DecodeOut(self.dec, op, self.regreduce_en)
1139         m.submodules.dec_o2 = dec_o2 = DecodeOut2(self.dec, op)
1140         m.submodules.dec_cr_in = self.dec_cr_in = DecodeCRIn(self.dec, op)
1141         m.submodules.dec_cr_out = self.dec_cr_out = DecodeCROut(self.dec, op)
1142         comb += dec_a.sv_nz.eq(self.sv_a_nz)
1143
1144         if self.svp64_en:
1145             # and SVP64 Extra decoders
1146             m.submodules.crout_svdec = crout_svdec = SVP64CRExtra()
1147             m.submodules.crin_svdec = crin_svdec = SVP64CRExtra()
1148             m.submodules.crin_svdec_b = crin_svdec_b = SVP64CRExtra()
1149             m.submodules.crin_svdec_o = crin_svdec_o = SVP64CRExtra()
1150             m.submodules.in1_svdec = in1_svdec = SVP64RegExtra()
1151             m.submodules.in2_svdec = in2_svdec = SVP64RegExtra()
1152             m.submodules.in3_svdec = in3_svdec = SVP64RegExtra()
1153             m.submodules.o_svdec = o_svdec = SVP64RegExtra()
1154             m.submodules.o2_svdec = o2_svdec = SVP64RegExtra()
1155
1156             # debug access to crout_svdec (used in get_pdecode_cr_out)
1157             self.crout_svdec = crout_svdec
1158
1159         # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
1160         reg = Signal(5, reset_less=True)
1161
1162         # copy instruction through...
1163         for i in [do.insn, dec_a.insn_in, dec_b.insn_in,
1164                   self.dec_cr_in.insn_in, self.dec_cr_out.insn_in,
1165                   dec_c.insn_in, dec_o.insn_in, dec_o2.insn_in]:
1166             comb += i.eq(self.dec.opcode_in)
1167
1168         # CR setup
1169         comb += self.dec_cr_in.sel_in.eq(self.op_get("cr_in"))
1170         comb += self.dec_cr_out.sel_in.eq(self.op_get("cr_out"))
1171         comb += self.dec_cr_out.rc_in.eq(rc_out)
1172
1173         # CR register info
1174         comb += self.do_copy("read_cr_whole", self.dec_cr_in.whole_reg)
1175         comb += self.do_copy("write_cr_whole", self.dec_cr_out.whole_reg)
1176
1177         # ...and subdecoders' input fields
1178         comb += dec_a.sel_in.eq(self.op_get("in1_sel"))
1179         comb += dec_b.sel_in.eq(self.op_get("in2_sel"))
1180         comb += dec_c.sel_in.eq(self.op_get("in3_sel"))
1181         comb += dec_o.sel_in.eq(self.op_get("out_sel"))
1182         comb += dec_o2.sel_in.eq(self.op_get("out_sel"))
1183         if hasattr(do, "lk"):
1184             comb += dec_o2.lk.eq(do.lk)
1185
1186         if self.svp64_en:
1187             # now do the SVP64 munging.  op.SV_Etype and op.sv_in1 comes from
1188             # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
1189             # which in turn were auto-generated by sv_analysis.py
1190             extra = self.sv_rm.extra            # SVP64 extra bits 10:18
1191
1192             #######
1193             # CR out
1194             comb += crout_svdec.idx.eq(self.op_get("sv_cr_out")) # SVP64 CR out
1195             comb += self.cr_out_isvec.eq(crout_svdec.isvec)
1196
1197             #######
1198             # CR in - selection slightly different due to shared CR field sigh
1199             cr_a_idx = Signal(SVEXTRA)
1200             cr_b_idx = Signal(SVEXTRA)
1201
1202             # these change slightly, when decoding BA/BB.  really should have
1203             # their own separate CSV column: sv_cr_in1 and sv_cr_in2, but hey
1204             comb += cr_a_idx.eq(self.op_get("sv_cr_in"))
1205             comb += cr_b_idx.eq(SVEXTRA.NONE)
1206             with m.If(self.op_get("sv_cr_in") == SVEXTRA.Idx_1_2.value):
1207                 comb += cr_a_idx.eq(SVEXTRA.Idx1)
1208                 comb += cr_b_idx.eq(SVEXTRA.Idx2)
1209
1210             comb += self.cr_in_isvec.eq(crin_svdec.isvec)
1211             comb += self.cr_in_b_isvec.eq(crin_svdec_b.isvec)
1212             comb += self.cr_in_o_isvec.eq(crin_svdec_o.isvec)
1213
1214             # indices are slightly different, BA/BB mess sorted above
1215             comb += crin_svdec.idx.eq(cr_a_idx)       # SVP64 CR in A
1216             comb += crin_svdec_b.idx.eq(cr_b_idx)     # SVP64 CR in B
1217             comb += crin_svdec_o.idx.eq(self.op_get("sv_cr_out")) # SVP64 CR out
1218
1219             # get SVSTATE srcstep (TODO: elwidth etc.) needed below
1220             vl = Signal.like(self.state.svstate.vl)
1221             srcstep = Signal.like(self.state.svstate.srcstep)
1222             dststep = Signal.like(self.state.svstate.dststep)
1223             comb += vl.eq(self.state.svstate.vl)
1224             comb += srcstep.eq(self.state.svstate.srcstep)
1225             comb += dststep.eq(self.state.svstate.dststep)
1226
1227             # registers a, b, c and out and out2 (LD/ST EA)
1228             sv_etype = self.op_get("SV_Etype")
1229             for to_reg, fromreg, svdec, out in (
1230                 (e.read_reg1, dec_a.reg_out, in1_svdec, False),
1231                 (e.read_reg2, dec_b.reg_out, in2_svdec, False),
1232                 (e.read_reg3, dec_c.reg_out, in3_svdec, False),
1233                 (e.write_reg, dec_o.reg_out, o_svdec, True),
1234                 (e.write_ea, dec_o2.reg_out, o2_svdec, True)):
1235                 comb += svdec.extra.eq(extra)     # EXTRA field of SVP64 RM
1236                 comb += svdec.etype.eq(sv_etype)  # EXTRA2/3 for this insn
1237                 comb += svdec.reg_in.eq(fromreg.data) # 3-bit (CR0/BC/BFA)
1238                 comb += to_reg.ok.eq(fromreg.ok)
1239                 # detect if Vectorised: add srcstep/dststep if yes.
1240                 # to_reg is 7-bits, outs get dststep added, ins get srcstep
1241                 with m.If(svdec.isvec):
1242                     step = dststep if out else srcstep
1243                     # reverse gear goes the opposite way
1244                     with m.If(self.rm_dec.reverse_gear):
1245                         comb += to_reg.data.eq(svdec.reg_out+(vl-1-step))
1246                     with m.Else():
1247                         comb += to_reg.data.eq(step+svdec.reg_out)
1248                 with m.Else():
1249                     comb += to_reg.data.eq(svdec.reg_out)
1250
1251             # SVP64 in/out fields
1252             comb += in1_svdec.idx.eq(self.op_get("sv_in1")) # reg #1 (in1_sel)
1253             comb += in2_svdec.idx.eq(self.op_get("sv_in2"))  # reg #2 (in2_sel)
1254             comb += in3_svdec.idx.eq(self.op_get("sv_in3"))  # reg #3 (in3_sel)
1255             comb += o_svdec.idx.eq(self.op_get("sv_out"))    # output (out_sel)
1256             comb += o2_svdec.idx.eq(self.op_get("sv_out2"))  # output (implicit)
1257             # XXX TODO - work out where this should come from.  the problem is
1258             # that LD-with-update is implied (computed from "is instruction in
1259             # "update mode" rather than specified cleanly as its own CSV column
1260
1261             # output reg-is-vectorised (and when no in/out is vectorised)
1262             comb += self.in1_isvec.eq(in1_svdec.isvec)
1263             comb += self.in2_isvec.eq(in2_svdec.isvec)
1264             comb += self.in3_isvec.eq(in3_svdec.isvec)
1265             comb += self.o_isvec.eq(o_svdec.isvec)
1266             comb += self.o2_isvec.eq(o2_svdec.isvec)
1267             # TODO add SPRs here.  must be True when *all* are scalar
1268             l = map(lambda svdec: svdec.isvec, [in1_svdec, in2_svdec, in3_svdec,
1269                                         crin_svdec, crin_svdec_b, crin_svdec_o])
1270             comb += self.no_in_vec.eq(~Cat(*l).bool()) # all input scalar
1271             l = map(lambda svdec: svdec.isvec, [o2_svdec, o_svdec, crout_svdec])
1272             # in mapreduce mode, scalar out is *allowed*
1273             with m.If(self.rm_dec.mode == SVP64RMMode.MAPREDUCE.value):
1274                 comb += self.no_out_vec.eq(0)
1275             with m.Else():
1276                 comb += self.no_out_vec.eq(~Cat(*l).bool()) # all output scalar
1277             # now create a general-purpose "test" as to whether looping
1278             # should continue.  this doesn't include predication bit-tests
1279             loop = self.loop_continue
1280             with m.Switch(self.op_get("SV_Ptype")):
1281                 with m.Case(SVPtype.P2.value):
1282                     # twin-predication
1283                     # TODO: *and cache-inhibited LD/ST!*
1284                     comb += loop.eq(~(self.no_in_vec | self.no_out_vec))
1285                 with m.Case(SVPtype.P1.value):
1286                     # single-predication, test relies on dest only
1287                     comb += loop.eq(~self.no_out_vec)
1288                 with m.Default():
1289                     # not an SV operation, no looping
1290                     comb += loop.eq(0)
1291
1292             # condition registers (CR)
1293             for to_reg, cr, name, svdec, out in (
1294                 (e.read_cr1, self.dec_cr_in, "cr_bitfield", crin_svdec, 0),
1295                 (e.read_cr2, self.dec_cr_in, "cr_bitfield_b", crin_svdec_b, 0),
1296                 (e.read_cr3, self.dec_cr_in, "cr_bitfield_o", crin_svdec_o, 0),
1297                 (e.write_cr, self.dec_cr_out, "cr_bitfield", crout_svdec, 1)):
1298                 fromreg = getattr(cr, name)
1299                 comb += svdec.extra.eq(extra)     # EXTRA field of SVP64 RM
1300                 comb += svdec.etype.eq(sv_etype)  # EXTRA2/3 for this insn
1301                 comb += svdec.cr_in.eq(fromreg.data) # 3-bit (CR0/BC/BFA)
1302                 with m.If(svdec.isvec):
1303                     # check if this is CR0 or CR1: treated differently
1304                     # (does not "listen" to EXTRA2/3 spec for a start)
1305                     # also: the CRs start from completely different locations
1306                     step = dststep if out else srcstep
1307                     with m.If(cr.sv_override == 1): # CR0
1308                         offs = SVP64CROffs.CR0
1309                         comb += to_reg.data.eq(step+offs)
1310                     with m.Elif(cr.sv_override == 2): # CR1
1311                         offs = SVP64CROffs.CR1
1312                         comb += to_reg.data.eq(step+1)
1313                     with m.Else():
1314                         comb += to_reg.data.eq(step+svdec.cr_out) # 7-bit out
1315                 with m.Else():
1316                     comb += to_reg.data.eq(svdec.cr_out) # 7-bit output
1317                 comb += to_reg.ok.eq(fromreg.ok)
1318
1319             # sigh must determine if RA is nonzero (7 bit)
1320             comb += self.sv_a_nz.eq(e.read_reg1.data != Const(0, 7))
1321         else:
1322             # connect up to/from read/write GPRs
1323             for to_reg, fromreg in ((e.read_reg1, dec_a.reg_out),
1324                                     (e.read_reg2, dec_b.reg_out),
1325                                     (e.read_reg3, dec_c.reg_out),
1326                                     (e.write_reg, dec_o.reg_out),
1327                                     (e.write_ea, dec_o2.reg_out)):
1328                 comb += to_reg.data.eq(fromreg.data)
1329                 comb += to_reg.ok.eq(fromreg.ok)
1330
1331             # connect up to/from read/write CRs
1332             for to_reg, cr, name in (
1333                         (e.read_cr1, self.dec_cr_in, "cr_bitfield", ),
1334                         (e.read_cr2, self.dec_cr_in, "cr_bitfield_b", ),
1335                         (e.read_cr3, self.dec_cr_in, "cr_bitfield_o", ),
1336                         (e.write_cr, self.dec_cr_out, "cr_bitfield", )):
1337                 fromreg = getattr(cr, name)
1338                 comb += to_reg.data.eq(fromreg.data)
1339                 comb += to_reg.ok.eq(fromreg.ok)
1340
1341         if self.svp64_en:
1342             comb += self.rm_dec.ldst_ra_vec.eq(self.in1_isvec) # RA is vector
1343
1344         # SPRs out
1345         comb += e.read_spr1.eq(dec_a.spr_out)
1346         comb += e.write_spr.eq(dec_o.spr_out)
1347
1348         # Fast regs out including SRR0/1/SVSRR0
1349         comb += e.read_fast1.eq(dec_a.fast_out)
1350         comb += e.read_fast2.eq(dec_b.fast_out)
1351         comb += e.write_fast1.eq(dec_o.fast_out)   # SRR0 (OP_RFID)
1352         comb += e.write_fast2.eq(dec_o2.fast_out)  # SRR1 (ditto)
1353         comb += e.write_fast3.eq(dec_o2.fast_out3) # SVSRR0 (ditto)
1354
1355         # sigh this is exactly the sort of thing for which the
1356         # decoder is designed to not need.  MTSPR, MFSPR and others need
1357         # access to the XER bits.  however setting e.oe is not appropriate
1358         internal_op = self.op_get("internal_op")
1359         with m.If(internal_op == MicrOp.OP_MFSPR):
1360             comb += e.xer_in.eq(0b111) # SO, CA, OV
1361         with m.If(internal_op == MicrOp.OP_CMP):
1362             comb += e.xer_in.eq(1<<XERRegsEnum.SO) # SO
1363         with m.If(internal_op == MicrOp.OP_MTSPR):
1364             comb += e.xer_out.eq(1)
1365
1366         # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
1367         with m.If(op.internal_op == MicrOp.OP_TRAP):
1368             # *DO NOT* call self.trap here.  that would reset absolutely
1369             # everything including destroying read of RA and RB.
1370             comb += self.do_copy("trapaddr", 0x70) # strip first nibble
1371
1372         ####################
1373         # ok so the instruction's been decoded, blah blah, however
1374         # now we need to determine if it's actually going to go ahead...
1375         # *or* if in fact it's a privileged operation, whether there's
1376         # an external interrupt, etc. etc.  this is a simple priority
1377         # if-elif-elif sequence.  decrement takes highest priority,
1378         # EINT next highest, privileged operation third.
1379
1380         # check if instruction is privileged
1381         is_priv_insn = instr_is_priv(m, op.internal_op, e.do.insn)
1382
1383         # different IRQ conditions
1384         ext_irq_ok = Signal()
1385         dec_irq_ok = Signal()
1386         priv_ok = Signal()
1387         illeg_ok = Signal()
1388         ldst_exc = self.ldst_exc
1389
1390         comb += ext_irq_ok.eq(ext_irq & msr[MSR.EE]) # v3.0B p944 (MSR.EE)
1391         comb += dec_irq_ok.eq(dec_spr[63] & msr[MSR.EE]) # 6.5.11 p1076
1392         comb += priv_ok.eq(is_priv_insn & msr[MSR.PR])
1393         comb += illeg_ok.eq(op.internal_op == MicrOp.OP_ILLEGAL)
1394
1395         # LD/ST exceptions.  TestIssuer copies the exception info at us
1396         # after a failed LD/ST.
1397         with m.If(ldst_exc.happened):
1398             with m.If(ldst_exc.alignment):
1399                 self.trap(m, TT.PRIV, 0x600)
1400             with m.Elif(ldst_exc.instr_fault):
1401                 with m.If(ldst_exc.segment_fault):
1402                     self.trap(m, TT.PRIV, 0x480)
1403                 with m.Else():
1404                     # pass exception info to trap to create SRR1
1405                     self.trap(m, TT.MEMEXC, 0x400, ldst_exc)
1406             with m.Else():
1407                 with m.If(ldst_exc.segment_fault):
1408                     self.trap(m, TT.PRIV, 0x380)
1409                 with m.Else():
1410                     self.trap(m, TT.PRIV, 0x300)
1411
1412         # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
1413         with m.Elif(dec_irq_ok):
1414             self.trap(m, TT.DEC, 0x900)   # v3.0B 6.5 p1065
1415
1416         # external interrupt? only if MSR.EE set
1417         with m.Elif(ext_irq_ok):
1418             self.trap(m, TT.EINT, 0x500)
1419
1420         # privileged instruction trap
1421         with m.Elif(priv_ok):
1422             self.trap(m, TT.PRIV, 0x700)
1423
1424         # illegal instruction must redirect to trap. this is done by
1425         # *overwriting* the decoded instruction and starting again.
1426         # (note: the same goes for interrupts and for privileged operations,
1427         # just with different trapaddr and traptype)
1428         with m.Elif(illeg_ok):
1429             # illegal instruction trap
1430             self.trap(m, TT.ILLEG, 0x700)
1431
1432         # no exception, just copy things to the output
1433         with m.Else():
1434             comb += e_out.eq(e)
1435
1436         ####################
1437         # follow-up after trap/irq to set up SRR0/1
1438
1439         # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
1440         # Note: OP_SC could actually be modified to just be a trap
1441         with m.If((do_out.insn_type == MicrOp.OP_TRAP) |
1442                   (do_out.insn_type == MicrOp.OP_SC)):
1443             # TRAP write fast1 = SRR0
1444             comb += e_out.write_fast1.data.eq(FastRegsEnum.SRR0)  # SRR0
1445             comb += e_out.write_fast1.ok.eq(1)
1446             # TRAP write fast2 = SRR1
1447             comb += e_out.write_fast2.data.eq(FastRegsEnum.SRR1)  # SRR1
1448             comb += e_out.write_fast2.ok.eq(1)
1449             # TRAP write fast2 = SRR1
1450             comb += e_out.write_fast3.data.eq(FastRegsEnum.SVSRR0)  # SVSRR0
1451             comb += e_out.write_fast3.ok.eq(1)
1452
1453         # RFID: needs to read SRR0/1
1454         with m.If(do_out.insn_type == MicrOp.OP_RFID):
1455             # TRAP read fast1 = SRR0
1456             comb += e_out.read_fast1.data.eq(FastRegsEnum.SRR0)  # SRR0
1457             comb += e_out.read_fast1.ok.eq(1)
1458             # TRAP read fast2 = SRR1
1459             comb += e_out.read_fast2.data.eq(FastRegsEnum.SRR1)  # SRR1
1460             comb += e_out.read_fast2.ok.eq(1)
1461             # TRAP read fast2 = SVSRR0
1462             comb += e_out.read_fast3.data.eq(FastRegsEnum.SVSRR0)  # SVSRR0
1463             comb += e_out.read_fast3.ok.eq(1)
1464
1465         # annoying simulator bug.
1466         # asmcode may end up getting used for perfcounters?
1467         asmcode = self.op_get("asmcode")
1468         if hasattr(e_out, "asmcode") and asmcode is not None:
1469             comb += e_out.asmcode.eq(asmcode)
1470
1471         return m
1472
1473     def trap(self, m, traptype, trapaddr, ldst_exc=None):
1474         """trap: this basically "rewrites" the decoded instruction as a trap
1475         """
1476         comb = m.d.comb
1477         e = self.e
1478         comb += e.eq(0)  # reset eeeeeverything
1479
1480         # start again
1481         comb += self.do_copy("insn", self.dec.opcode_in, True)
1482         comb += self.do_copy("insn_type", MicrOp.OP_TRAP, True)
1483         comb += self.do_copy("fn_unit", Function.TRAP, True)
1484         comb += self.do_copy("trapaddr", trapaddr >> 4, True) # bottom 4 bits
1485         comb += self.do_copy("traptype", traptype, True)  # request type
1486         comb += self.do_copy("ldst_exc", ldst_exc, True)  # request type
1487         comb += self.do_copy("msr", self.state.msr, True) # copy of MSR "state"
1488         comb += self.do_copy("cia", self.state.pc, True)  # copy of PC "state"
1489         comb += self.do_copy("svstate", self.state.svstate, True)  # SVSTATE
1490
1491
1492
1493 def get_rdflags(e, cu):
1494     rdl = []
1495     for idx in range(cu.n_src):
1496         regfile, regname, _ = cu.get_in_spec(idx)
1497         rdflag, read = regspec_decode_read(e, regfile, regname)
1498         rdl.append(rdflag)
1499     log("rdflags", rdl)
1500     return Cat(*rdl)
1501
1502
1503 if __name__ == '__main__':
1504     pdecode = create_pdecode()
1505     dec2 = PowerDecode2(pdecode)
1506     vl = rtlil.convert(dec2, ports=dec2.ports() + pdecode.ports())
1507     with open("dec2.il", "w") as f:
1508         f.write(vl)