1 """Power ISA Decoder second stage
3 based on Anton Blanchard microwatt decode2.vhdl
5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
6 over-riding the internal opcode when an exception is needed.
9 from nmigen
import Module
, Elaboratable
, Signal
, Mux
, Const
, Cat
, Repl
, Record
10 from nmigen
.cli
import rtlil
11 from nmutil
.util
import sel
13 from nmutil
.picker
import PriorityPicker
14 from nmutil
.iocontrol
import RecordObject
15 from nmutil
.extend
import exts
17 from openpower
.exceptions
import LDSTException
19 from openpower
.decoder
.power_svp64_prefix
import SVP64PrefixDecoder
20 from openpower
.decoder
.power_svp64_extra
import SVP64CRExtra
, SVP64RegExtra
21 from openpower
.decoder
.power_svp64_rm
import (SVP64RMModeDecode
,
22 sv_input_record_layout
,
24 from openpower
.sv
.svp64
import SVP64Rec
26 from openpower
.decoder
.power_regspec_map
import regspec_decode_read
27 from openpower
.decoder
.power_decoder
import (create_pdecode
,
28 create_pdecode_svp64_ldst
,
30 from openpower
.decoder
.power_enums
import (MicrOp
, CryIn
, Function
,
32 LdstLen
, In1Sel
, In2Sel
, In3Sel
,
33 OutSel
, SPRfull
, SPRreduced
,
34 RC
, SVP64LDSTmode
, LDSTMode
,
35 SVEXTRA
, SVEtype
, SVPtype
)
36 from openpower
.decoder
.decode2execute1
import (Decode2ToExecute1Type
, Data
,
39 from openpower
.consts
import (MSR
, SPEC
, EXTRA2
, EXTRA3
, SVP64P
, field
,
40 SPEC_SIZE
, SPECb
, SPEC_AUG_SIZE
, SVP64CROffs
,
41 FastRegsEnum
, XERRegsEnum
, TT
)
43 from openpower
.state
import CoreState
44 from openpower
.util
import (spr_to_fast
, spr_to_state
, log
)
47 def decode_spr_num(spr
):
48 return Cat(spr
[5:10], spr
[0:5])
51 def instr_is_priv(m
, op
, insn
):
52 """determines if the instruction is privileged or not
55 is_priv_insn
= Signal(reset_less
=True)
57 with m
.Case(MicrOp
.OP_ATTN
, MicrOp
.OP_MFMSR
, MicrOp
.OP_MTMSRD
,
58 MicrOp
.OP_MTMSR
, MicrOp
.OP_RFID
):
59 comb
+= is_priv_insn
.eq(1)
60 with m
.Case(MicrOp
.OP_TLBIE
):
61 comb
+= is_priv_insn
.eq(1)
62 with m
.Case(MicrOp
.OP_MFSPR
, MicrOp
.OP_MTSPR
):
63 with m
.If(insn
[20]): # field XFX.spr[-1] i think
64 comb
+= is_priv_insn
.eq(1)
68 class SPRMap(Elaboratable
):
69 """SPRMap: maps POWER9 SPR numbers to internal enum values, fast and slow
72 def __init__(self
, regreduce_en
):
73 self
.regreduce_en
= regreduce_en
79 self
.spr_i
= Signal(10, reset_less
=True)
80 self
.spr_o
= Data(SPR
, name
="spr_o")
81 self
.fast_o
= Data(4, name
="fast_o")
82 self
.state_o
= Data(3, name
="state_o")
84 def elaborate(self
, platform
):
90 with m
.Switch(self
.spr_i
):
91 for i
, x
in enumerate(SPR
):
93 m
.d
.comb
+= self
.spr_o
.data
.eq(i
)
94 m
.d
.comb
+= self
.spr_o
.ok
.eq(1)
95 for x
, v
in spr_to_fast
.items():
97 m
.d
.comb
+= self
.fast_o
.data
.eq(v
)
98 m
.d
.comb
+= self
.fast_o
.ok
.eq(1)
99 for x
, v
in spr_to_state
.items():
100 with m
.Case(x
.value
):
101 m
.d
.comb
+= self
.state_o
.data
.eq(v
)
102 m
.d
.comb
+= self
.state_o
.ok
.eq(1)
106 class DecodeA(Elaboratable
):
107 """DecodeA from instruction
109 decodes register RA, implicit and explicit CSRs
112 def __init__(self
, dec
, op
, regreduce_en
):
113 self
.regreduce_en
= regreduce_en
114 if self
.regreduce_en
:
120 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
121 self
.insn_in
= Signal(32, reset_less
=True)
122 self
.reg_out
= Data(5, name
="reg_a")
123 self
.spr_out
= Data(SPR
, "spr_a")
124 self
.fast_out
= Data(4, "fast_a")
125 self
.state_out
= Data(3, "state_a")
126 self
.sv_nz
= Signal(1)
128 def elaborate(self
, platform
):
133 m
.submodules
.sprmap
= sprmap
= SPRMap(self
.regreduce_en
)
135 # select Register A field, if *full 7 bits* are zero (2 more from SVP64)
136 ra
= Signal(5, reset_less
=True)
137 comb
+= ra
.eq(self
.dec
.RA
)
138 with m
.If((self
.sel_in
== In1Sel
.RA
) |
139 ((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
140 ((ra
!= Const(0, 5)) |
(self
.sv_nz
!= Const(0, 1))))):
141 comb
+= reg
.data
.eq(ra
)
144 # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
145 # moved it to 1st position (in1_sel)... because
146 rs
= Signal(5, reset_less
=True)
147 comb
+= rs
.eq(self
.dec
.RS
)
148 with m
.If(self
.sel_in
== In1Sel
.RS
):
149 comb
+= reg
.data
.eq(rs
)
152 # select Register FRA field,
153 fra
= Signal(5, reset_less
=True)
154 comb
+= fra
.eq(self
.dec
.FRA
)
155 with m
.If(self
.sel_in
== In1Sel
.FRA
):
156 comb
+= reg
.data
.eq(fra
)
159 # select Register FRS field,
160 frs
= Signal(5, reset_less
=True)
161 comb
+= frs
.eq(self
.dec
.FRS
)
162 with m
.If(self
.sel_in
== In1Sel
.FRS
):
163 comb
+= reg
.data
.eq(frs
)
166 # decode Fast-SPR based on instruction type
167 with m
.Switch(op
.internal_op
):
169 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
170 with m
.Case(MicrOp
.OP_BC
):
171 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
173 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.CTR
)
174 comb
+= self
.fast_out
.ok
.eq(1)
175 with m
.Case(MicrOp
.OP_BCREG
):
176 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
177 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
178 with m
.If(xo9
& ~xo5
):
180 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.CTR
)
181 comb
+= self
.fast_out
.ok
.eq(1)
183 # MFSPR move from SPRs
184 with m
.Case(MicrOp
.OP_MFSPR
):
185 spr
= Signal(10, reset_less
=True)
186 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
187 comb
+= sprmap
.spr_i
.eq(spr
)
188 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
189 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
190 comb
+= self
.state_out
.eq(sprmap
.state_o
)
195 class DecodeAImm(Elaboratable
):
196 """DecodeA immediate from instruction
198 decodes register RA, whether immediate-zero, implicit and
199 explicit CSRs. SVP64 mode requires 2 extra bits
202 def __init__(self
, dec
):
204 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
205 self
.immz_out
= Signal(reset_less
=True)
206 self
.sv_nz
= Signal(1) # EXTRA bits from SVP64
208 def elaborate(self
, platform
):
212 # zero immediate requested
213 ra
= Signal(5, reset_less
=True)
214 comb
+= ra
.eq(self
.dec
.RA
)
215 with m
.If((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
216 (ra
== Const(0, 5)) &
217 (self
.sv_nz
== Const(0, 1))):
218 comb
+= self
.immz_out
.eq(1)
223 class DecodeB(Elaboratable
):
224 """DecodeB from instruction
226 decodes register RB, different forms of immediate (signed, unsigned),
227 and implicit SPRs. register B is basically "lane 2" into the CompUnits.
228 by industry-standard convention, "lane 2" is where fully-decoded
229 immediates are muxed in.
232 def __init__(self
, dec
, op
):
235 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
236 self
.insn_in
= Signal(32, reset_less
=True)
237 self
.reg_out
= Data(7, "reg_b")
238 self
.reg_isvec
= Signal(1, name
="reg_b_isvec") # TODO: in reg_out
239 self
.fast_out
= Data(4, "fast_b")
241 def elaborate(self
, platform
):
247 # select Register B field
248 with m
.Switch(self
.sel_in
):
249 with m
.Case(In2Sel
.FRB
):
250 comb
+= reg
.data
.eq(self
.dec
.FRB
)
252 with m
.Case(In2Sel
.RB
):
253 comb
+= reg
.data
.eq(self
.dec
.RB
)
255 with m
.Case(In2Sel
.RS
):
256 # for M-Form shiftrot
257 comb
+= reg
.data
.eq(self
.dec
.RS
)
260 # decode SPR2 based on instruction type
261 # BCREG implicitly uses LR or TAR for 2nd reg
262 # CTR however is already in fast_spr1 *not* 2.
263 with m
.If(op
.internal_op
== MicrOp
.OP_BCREG
):
264 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
265 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
267 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.LR
)
268 comb
+= self
.fast_out
.ok
.eq(1)
270 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.TAR
)
271 comb
+= self
.fast_out
.ok
.eq(1)
276 class DecodeBImm(Elaboratable
):
277 """DecodeB immediate from instruction
280 def __init__(self
, dec
):
282 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
283 self
.imm_out
= Data(64, "imm_b")
285 def elaborate(self
, platform
):
289 # select Register B Immediate
290 with m
.Switch(self
.sel_in
):
291 with m
.Case(In2Sel
.CONST_UI
): # unsigned
292 comb
+= self
.imm_out
.data
.eq(self
.dec
.UI
)
293 comb
+= self
.imm_out
.ok
.eq(1)
294 with m
.Case(In2Sel
.CONST_SI
): # sign-extended 16-bit
295 si
= Signal(16, reset_less
=True)
296 comb
+= si
.eq(self
.dec
.SI
)
297 comb
+= self
.imm_out
.data
.eq(exts(si
, 16, 64))
298 comb
+= self
.imm_out
.ok
.eq(1)
299 with m
.Case(In2Sel
.CONST_SI_HI
): # sign-extended 16+16=32 bit
300 si_hi
= Signal(32, reset_less
=True)
301 comb
+= si_hi
.eq(self
.dec
.SI
<< 16)
302 comb
+= self
.imm_out
.data
.eq(exts(si_hi
, 32, 64))
303 comb
+= self
.imm_out
.ok
.eq(1)
304 with m
.Case(In2Sel
.CONST_UI_HI
): # unsigned
305 ui
= Signal(16, reset_less
=True)
306 comb
+= ui
.eq(self
.dec
.UI
)
307 comb
+= self
.imm_out
.data
.eq(ui
<< 16)
308 comb
+= self
.imm_out
.ok
.eq(1)
309 with m
.Case(In2Sel
.CONST_LI
): # sign-extend 24+2=26 bit
310 li
= Signal(26, reset_less
=True)
311 comb
+= li
.eq(self
.dec
.LI
<< 2)
312 comb
+= self
.imm_out
.data
.eq(exts(li
, 26, 64))
313 comb
+= self
.imm_out
.ok
.eq(1)
314 with m
.Case(In2Sel
.CONST_BD
): # sign-extend (14+2)=16 bit
315 bd
= Signal(16, reset_less
=True)
316 comb
+= bd
.eq(self
.dec
.BD
<< 2)
317 comb
+= self
.imm_out
.data
.eq(exts(bd
, 16, 64))
318 comb
+= self
.imm_out
.ok
.eq(1)
319 with m
.Case(In2Sel
.CONST_DS
): # sign-extended (14+2=16) bit
320 ds
= Signal(16, reset_less
=True)
321 comb
+= ds
.eq(self
.dec
.DS
<< 2)
322 comb
+= self
.imm_out
.data
.eq(exts(ds
, 16, 64))
323 comb
+= self
.imm_out
.ok
.eq(1)
324 with m
.Case(In2Sel
.CONST_M1
): # signed (-1)
325 comb
+= self
.imm_out
.data
.eq(~
Const(0, 64)) # all 1s
326 comb
+= self
.imm_out
.ok
.eq(1)
327 with m
.Case(In2Sel
.CONST_SH
): # unsigned - for shift
328 comb
+= self
.imm_out
.data
.eq(self
.dec
.sh
)
329 comb
+= self
.imm_out
.ok
.eq(1)
330 with m
.Case(In2Sel
.CONST_SH32
): # unsigned - for shift
331 comb
+= self
.imm_out
.data
.eq(self
.dec
.SH32
)
332 comb
+= self
.imm_out
.ok
.eq(1)
333 with m
.Case(In2Sel
.CONST_XBI
): # unsigned - for grevi
334 comb
+= self
.imm_out
.data
.eq(self
.dec
.FormXB
.XBI
)
335 comb
+= self
.imm_out
.ok
.eq(1)
340 class DecodeC(Elaboratable
):
341 """DecodeC from instruction
343 decodes register RC. this is "lane 3" into some CompUnits (not many)
346 def __init__(self
, dec
, op
):
349 self
.sel_in
= Signal(In3Sel
, reset_less
=True)
350 self
.insn_in
= Signal(32, reset_less
=True)
351 self
.reg_out
= Data(5, "reg_c")
353 def elaborate(self
, platform
):
359 # select Register C field
360 with m
.Switch(self
.sel_in
):
361 with m
.Case(In3Sel
.RB
):
362 # for M-Form shiftrot
363 comb
+= reg
.data
.eq(self
.dec
.RB
)
365 with m
.Case(In3Sel
.FRS
):
366 comb
+= reg
.data
.eq(self
.dec
.FRS
)
368 with m
.Case(In3Sel
.FRC
):
369 comb
+= reg
.data
.eq(self
.dec
.FRC
)
371 with m
.Case(In3Sel
.RS
):
372 comb
+= reg
.data
.eq(self
.dec
.RS
)
374 with m
.Case(In3Sel
.RC
):
375 comb
+= reg
.data
.eq(self
.dec
.RC
)
377 with m
.Case(In3Sel
.RT
):
378 # for TLI-form ternlogi
379 comb
+= reg
.data
.eq(self
.dec
.RT
)
385 class DecodeOut(Elaboratable
):
386 """DecodeOut from instruction
388 decodes output register RA, RT, FRS, FRT, or SPR
391 def __init__(self
, dec
, op
, regreduce_en
):
392 self
.regreduce_en
= regreduce_en
393 if self
.regreduce_en
:
399 self
.sel_in
= Signal(OutSel
, reset_less
=True)
400 self
.insn_in
= Signal(32, reset_less
=True)
401 self
.reg_out
= Data(5, "reg_o")
402 self
.spr_out
= Data(SPR
, "spr_o")
403 self
.fast_out
= Data(4, "fast_o")
404 self
.state_out
= Data(3, "state_o")
406 def elaborate(self
, platform
):
409 m
.submodules
.sprmap
= sprmap
= SPRMap(self
.regreduce_en
)
413 # select Register out field
414 with m
.Switch(self
.sel_in
):
415 with m
.Case(OutSel
.FRS
):
416 comb
+= reg
.data
.eq(self
.dec
.FRS
)
418 with m
.Case(OutSel
.FRT
):
419 comb
+= reg
.data
.eq(self
.dec
.FRT
)
421 with m
.Case(OutSel
.RT
):
422 comb
+= reg
.data
.eq(self
.dec
.RT
)
424 with m
.Case(OutSel
.RA
):
425 comb
+= reg
.data
.eq(self
.dec
.RA
)
427 with m
.Case(OutSel
.SPR
):
428 spr
= Signal(10, reset_less
=True)
429 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
430 # MFSPR move to SPRs - needs mapping
431 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
432 comb
+= sprmap
.spr_i
.eq(spr
)
433 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
434 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
435 comb
+= self
.state_out
.eq(sprmap
.state_o
)
438 with m
.Switch(op
.internal_op
):
440 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
441 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_BCREG
):
442 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
444 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.CTR
)
445 comb
+= self
.fast_out
.ok
.eq(1)
447 # RFID 1st spr (fast)
448 with m
.Case(MicrOp
.OP_RFID
):
449 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.SRR0
) # SRR0
450 comb
+= self
.fast_out
.ok
.eq(1)
455 class DecodeOut2(Elaboratable
):
456 """DecodeOut2 from instruction
458 decodes output registers (2nd one). note that RA is *implicit* below,
459 which now causes problems with SVP64
461 TODO: SVP64 is a little more complex, here. svp64 allows extending
462 by one more destination by having one more EXTRA field. RA-as-src
463 is not the same as RA-as-dest. limited in that it's the same first
464 5 bits (from the v3.0B opcode), but still kinda cool. mostly used
465 for operations that have src-as-dest: mostly this is LD/ST-with-update
466 but there are others.
469 def __init__(self
, dec
, op
):
472 self
.sel_in
= Signal(OutSel
, reset_less
=True)
473 self
.svp64_fft_mode
= Signal(reset_less
=True) # SVP64 FFT mode
474 self
.lk
= Signal(reset_less
=True)
475 self
.insn_in
= Signal(32, reset_less
=True)
476 self
.reg_out
= Data(5, "reg_o2")
477 self
.fp_madd_en
= Signal(reset_less
=True) # FFT instruction detected
478 self
.fast_out
= Data(4, "fast_o2")
479 self
.fast_out3
= Data(4, "fast_o3")
481 def elaborate(self
, platform
):
485 #m.submodules.svdec = svdec = SVP64RegExtra()
487 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
488 #reg = Signal(5, reset_less=True)
490 if hasattr(op
, "upd"):
491 # update mode LD/ST uses read-reg A also as an output
492 with m
.If(op
.upd
== LDSTMode
.update
):
493 comb
+= self
.reg_out
.data
.eq(self
.dec
.RA
)
494 comb
+= self
.reg_out
.ok
.eq(1)
496 # B, BC or BCREG: potential implicit register (LR) output
497 # these give bl, bcl, bclrl, etc.
498 with m
.Switch(op
.internal_op
):
500 # BC* implicit register (LR)
501 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_B
, MicrOp
.OP_BCREG
):
502 with m
.If(self
.lk
): # "link" mode
503 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.LR
) # LR
504 comb
+= self
.fast_out
.ok
.eq(1)
506 # RFID 2nd and 3rd spr (fast)
507 with m
.Case(MicrOp
.OP_RFID
):
508 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.SRR1
) # SRR1
509 comb
+= self
.fast_out
.ok
.eq(1)
510 comb
+= self
.fast_out3
.data
.eq(FastRegsEnum
.SVSRR0
) # SVSRR0
511 comb
+= self
.fast_out3
.ok
.eq(1)
513 # SVP64 FFT mode, FP mul-add: 2nd output reg (FRS) same as FRT
514 # will be offset by VL in hardware
515 # with m.Case(MicrOp.OP_FP_MADD):
516 with m
.If(self
.svp64_fft_mode
):
517 comb
+= self
.reg_out
.data
.eq(self
.dec
.FRT
)
518 comb
+= self
.reg_out
.ok
.eq(1)
519 comb
+= self
.fp_madd_en
.eq(1)
524 class DecodeRC(Elaboratable
):
525 """DecodeRc from instruction
527 decodes Record bit Rc
530 def __init__(self
, dec
):
532 self
.sel_in
= Signal(RC
, reset_less
=True)
533 self
.insn_in
= Signal(32, reset_less
=True)
534 self
.rc_out
= Data(1, "rc")
536 def elaborate(self
, platform
):
540 # select Record bit out field
541 with m
.Switch(self
.sel_in
):
543 comb
+= self
.rc_out
.data
.eq(self
.dec
.Rc
)
544 comb
+= self
.rc_out
.ok
.eq(1)
546 comb
+= self
.rc_out
.data
.eq(1)
547 comb
+= self
.rc_out
.ok
.eq(1)
548 with m
.Case(RC
.NONE
):
549 comb
+= self
.rc_out
.data
.eq(0)
550 comb
+= self
.rc_out
.ok
.eq(1)
555 class DecodeOE(Elaboratable
):
556 """DecodeOE from instruction
558 decodes OE field: uses RC decode detection which might not be good
560 -- For now, use "rc" in the decode table to decide whether oe exists.
561 -- This is not entirely correct architecturally: For mulhd and
562 -- mulhdu, the OE field is reserved. It remains to be seen what an
563 -- actual POWER9 does if we set it on those instructions, for now we
564 -- test that further down when assigning to the multiplier oe input.
567 def __init__(self
, dec
, op
):
570 self
.sel_in
= Signal(RC
, reset_less
=True)
571 self
.insn_in
= Signal(32, reset_less
=True)
572 self
.oe_out
= Data(1, "oe")
574 def elaborate(self
, platform
):
580 comb
+= self
.oe_out
.data
.eq(0)
581 comb
+= self
.oe_out
.ok
.eq(0)
583 with m
.Switch(op
.internal_op
):
585 # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE
586 # also rotate. and setvl and all other sv* management
587 # basically the HDL below bypasses normal decode and
588 # goes directly and explicitly to bit 30 (self.dec.OE).
589 # on the list of instructions below (really this should
590 # be in the CSV files) they must be told *not* to do that.
591 # XXX ARGH! ignoring OE causes incompatibility with microwatt
592 # http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-August/000302.html
593 with m
.Case(MicrOp
.OP_MUL_H64
, MicrOp
.OP_MUL_H32
,
594 MicrOp
.OP_EXTS
, MicrOp
.OP_CNTZ
,
595 MicrOp
.OP_SHL
, MicrOp
.OP_SHR
, MicrOp
.OP_RLC
,
596 MicrOp
.OP_LOAD
, MicrOp
.OP_STORE
,
597 MicrOp
.OP_RLCL
, MicrOp
.OP_RLCR
,
598 MicrOp
.OP_SETVL
, MicrOp
.OP_SVSHAPE
,
599 MicrOp
.OP_SVINDEX
, MicrOp
.OP_SVREMAP
,
601 MicrOp
.OP_EXTSWSLI
, MicrOp
.OP_GREV
, MicrOp
.OP_TERNLOG
):
604 # all other ops decode OE field
606 # select OE bit out field
607 with m
.Switch(self
.sel_in
):
609 comb
+= self
.oe_out
.data
.eq(self
.dec
.OE
)
610 comb
+= self
.oe_out
.ok
.eq(1)
615 class DecodeCRIn(Elaboratable
):
616 """Decodes input CR from instruction
618 CR indices - insn fields - (not the data *in* the CR) require only 3
619 bits because they refer to CR0-CR7
622 def __init__(self
, dec
, op
):
625 self
.sel_in
= Signal(CRInSel
, reset_less
=True)
626 self
.insn_in
= Signal(32, reset_less
=True)
627 self
.cr_bitfield
= Data(3, "cr_bitfield")
628 self
.cr_bitfield_b
= Data(3, "cr_bitfield_b")
629 self
.cr_bitfield_o
= Data(3, "cr_bitfield_o")
630 self
.whole_reg
= Data(8, "cr_fxm")
631 self
.sv_override
= Signal(2, reset_less
=True) # do not do EXTRA spec
633 def elaborate(self
, platform
):
637 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
640 # zero-initialisation
641 comb
+= self
.cr_bitfield
.ok
.eq(0)
642 comb
+= self
.cr_bitfield_b
.ok
.eq(0)
643 comb
+= self
.cr_bitfield_o
.ok
.eq(0)
644 comb
+= self
.whole_reg
.ok
.eq(0)
645 comb
+= self
.sv_override
.eq(0)
647 # select the relevant CR bitfields
648 with m
.Switch(self
.sel_in
):
649 with m
.Case(CRInSel
.NONE
):
650 pass # No bitfield activated
651 with m
.Case(CRInSel
.CR0
):
652 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
653 comb
+= self
.cr_bitfield
.ok
.eq(1)
654 comb
+= self
.sv_override
.eq(1)
655 with m
.Case(CRInSel
.CR1
):
656 comb
+= self
.cr_bitfield
.data
.eq(1) # CR1 (MSB0 numbering)
657 comb
+= self
.cr_bitfield
.ok
.eq(1)
658 comb
+= self
.sv_override
.eq(2)
659 with m
.Case(CRInSel
.BI
):
660 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BI
[2:5])
661 comb
+= self
.cr_bitfield
.ok
.eq(1)
662 with m
.Case(CRInSel
.BFA
):
663 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BFA
)
664 comb
+= self
.cr_bitfield
.ok
.eq(1)
665 with m
.Case(CRInSel
.BA_BB
):
666 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BA
[2:5])
667 comb
+= self
.cr_bitfield
.ok
.eq(1)
668 comb
+= self
.cr_bitfield_b
.data
.eq(self
.dec
.BB
[2:5])
669 comb
+= self
.cr_bitfield_b
.ok
.eq(1)
670 comb
+= self
.cr_bitfield_o
.data
.eq(self
.dec
.BT
[2:5])
671 comb
+= self
.cr_bitfield_o
.ok
.eq(1)
672 with m
.Case(CRInSel
.BC
):
673 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BC
[2:5])
674 comb
+= self
.cr_bitfield
.ok
.eq(1)
675 with m
.Case(CRInSel
.WHOLE_REG
):
676 comb
+= self
.whole_reg
.ok
.eq(1)
677 move_one
= Signal(reset_less
=True)
678 comb
+= move_one
.eq(self
.insn_in
[20]) # MSB0 bit 11
679 with m
.If((op
.internal_op
== MicrOp
.OP_MFCR
) & move_one
):
680 # must one-hot the FXM field
681 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
682 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
684 # otherwise use all of it
685 comb
+= self
.whole_reg
.data
.eq(0xff)
690 class DecodeCROut(Elaboratable
):
691 """Decodes input CR from instruction
693 CR indices - insn fields - (not the data *in* the CR) require only 3
694 bits because they refer to CR0-CR7
697 def __init__(self
, dec
, op
):
700 self
.rc_in
= Signal(reset_less
=True)
701 self
.sel_in
= Signal(CROutSel
, reset_less
=True)
702 self
.insn_in
= Signal(32, reset_less
=True)
703 self
.cr_bitfield
= Data(3, "cr_bitfield")
704 self
.whole_reg
= Data(8, "cr_fxm")
705 self
.sv_override
= Signal(2, reset_less
=True) # do not do EXTRA spec
707 def elaborate(self
, platform
):
711 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
714 comb
+= self
.cr_bitfield
.ok
.eq(0)
715 comb
+= self
.whole_reg
.ok
.eq(0)
716 comb
+= self
.sv_override
.eq(0)
718 # please note these MUST match (setting of cr_bitfield.ok) exactly
719 # with write_cr0 below in PowerDecoder2. the reason it's separated
720 # is to avoid having duplicate copies of DecodeCROut in multiple
721 # PowerDecoderSubsets. register decoding should be a one-off in
722 # PowerDecoder2. see https://bugs.libre-soc.org/show_bug.cgi?id=606
724 with m
.Switch(self
.sel_in
):
725 with m
.Case(CROutSel
.NONE
):
726 pass # No bitfield activated
727 with m
.Case(CROutSel
.CR0
):
728 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
729 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
730 comb
+= self
.sv_override
.eq(1)
731 with m
.Case(CROutSel
.CR1
):
732 comb
+= self
.cr_bitfield
.data
.eq(1) # CR1 (MSB0 numbering)
733 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
734 comb
+= self
.sv_override
.eq(2)
735 with m
.Case(CROutSel
.BF
):
736 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BF
)
737 comb
+= self
.cr_bitfield
.ok
.eq(1)
738 with m
.Case(CROutSel
.BT
):
739 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormXL
.BT
[2:5])
740 comb
+= self
.cr_bitfield
.ok
.eq(1)
741 with m
.Case(CROutSel
.WHOLE_REG
):
742 comb
+= self
.whole_reg
.ok
.eq(1)
743 move_one
= Signal(reset_less
=True)
744 comb
+= move_one
.eq(self
.insn_in
[20])
745 with m
.If((op
.internal_op
== MicrOp
.OP_MTCRF
)):
747 # must one-hot the FXM field
748 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
749 with m
.If(ppick
.en_o
):
750 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
752 comb
+= self
.whole_reg
.data
.eq(0b00000001) # CR7
754 comb
+= self
.whole_reg
.data
.eq(self
.dec
.FXM
)
756 # otherwise use all of it
757 comb
+= self
.whole_reg
.data
.eq(0xff)
762 # dictionary of Input Record field names that, if they exist,
763 # will need a corresponding CSV Decoder file column (actually, PowerOp)
764 # to be decoded (this includes the single bit names)
765 record_names
= {'insn_type': 'internal_op',
766 'fn_unit': 'function_unit',
767 'SV_Ptype': 'SV_Ptype',
771 'imm_data': 'in2_sel',
772 'invert_in': 'inv_a',
773 'invert_out': 'inv_out',
776 'output_carry': 'cry_out',
777 'input_carry': 'cry_in',
778 'is_32bit': 'is_32b',
781 'data_len': 'ldst_len',
783 'byte_reverse': 'br',
784 'sign_extend': 'sgn_ext',
789 class PowerDecodeSubset(Elaboratable
):
790 """PowerDecodeSubset: dynamic subset decoder
792 only fields actually requested are copied over. hence, "subset" (duh).
795 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False, state
=None,
796 svp64_en
=True, regreduce_en
=False):
798 self
.svp64_en
= svp64_en
799 self
.regreduce_en
= regreduce_en
801 self
.is_svp64_mode
= Signal() # mark decoding as SVP64 Mode
802 self
.use_svp64_fft
= Signal() # FFT Mode
803 self
.sv_rm
= SVP64Rec(name
="dec_svp64") # SVP64 RM field
804 self
.rm_dec
= SVP64RMModeDecode("svp64_rm_dec")
805 # set these to the predicate mask bits needed for the ALU
806 self
.pred_sm
= Signal() # TODO expand to SIMD mask width
807 self
.pred_dm
= Signal() # TODO expand to SIMD mask width
808 self
.sv_a_nz
= Signal(1)
811 self
.fn_name
= fn_name
813 opkls
= Decode2ToOperand
814 self
.do
= opkls(fn_name
)
816 col_subset
= self
.get_col_subset(self
.do
)
817 row_subset
= self
.rowsubsetfn
822 # "conditions" for Decoders, to enable some weird and wonderful
823 # alternatives. useful for PCR (Program Compatibility Register)
824 # amongst other things
827 'SVP64FFT': self
.use_svp64_fft
,
832 # only needed for "main" PowerDecode2
834 self
.e
= Decode2ToExecute1Type(name
=self
.fn_name
, do
=self
.do
,
835 regreduce_en
=regreduce_en
)
837 # create decoder if one not already given
839 dec
= create_pdecode(name
=fn_name
, col_subset
=col_subset
,
840 row_subset
=row_subset
,
841 conditions
=conditions
)
844 # set up a copy of the PowerOp
845 self
.op
= PowerOp
.like(self
.dec
.op
)
847 # state information needed by the Decoder
849 state
= CoreState("dec2")
852 def get_col_subset(self
, do
):
853 subset
= {'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
854 for k
, v
in record_names
.items():
857 log("get_col_subset", self
.fn_name
, do
.fields
, subset
)
860 def rowsubsetfn(self
, opcode
, row
):
861 """select per-Function-Unit subset of opcodes to be processed
863 normally this just looks at the "unit" column. MMU is different
864 in that it processes specific SPR set/get operations that the SPR
867 return (row
['unit'] == self
.fn_name
or
868 # sigh a dreadful hack: MTSPR and MFSPR need to be processed
869 # by the MMU pipeline so we direct those opcodes to MMU **AND**
870 # SPR pipelines, then selectively weed out the SPRs that should
871 # or should not not go to each pipeline, further down.
872 # really this should be done by modifying the CSV syntax
873 # to support multiple tasks (unit column multiple entries)
874 # see https://bugs.libre-soc.org/show_bug.cgi?id=310
875 (self
.fn_name
== 'MMU' and row
['unit'] == 'SPR' and
876 row
['internal op'] in ['OP_MTSPR', 'OP_MFSPR']) or
877 # urrr... and the KAIVB SPR, which must also be redirected
878 # (to the TRAP pipeline)
879 # see https://bugs.libre-soc.org/show_bug.cgi?id=859
880 (self
.fn_name
== 'TRAP' and row
['unit'] == 'SPR' and
881 row
['internal op'] in ['OP_MTSPR', 'OP_MFSPR'])
885 ports
= self
.dec
.ports() + self
.e
.ports()
887 ports
+= self
.sv_rm
.ports()
888 ports
.append(self
.is_svp64_mode
)
889 ports
.append(self
.use_svp64_fft
)
892 def needs_field(self
, field
, op_field
):
897 return hasattr(do
, field
) and self
.op_get(op_field
) is not None
899 def do_get(self
, field
, final
=False):
900 if final
or self
.final
:
904 return getattr(do
, field
, None)
906 def do_copy(self
, field
, val
, final
=False):
907 df
= self
.do_get(field
, final
)
908 if df
is not None and val
is not None:
912 def op_get(self
, op_field
):
913 return getattr(self
.op
, op_field
, None)
915 def elaborate(self
, platform
):
916 if self
.regreduce_en
:
923 op
, do
= self
.dec
.op
, self
.do
924 msr
, cia
, svstate
= state
.msr
, state
.pc
, state
.svstate
925 # fill in for a normal instruction (not an exception)
926 # copy over if non-exception, non-privileged etc. is detected
928 if self
.fn_name
is None:
931 name
= self
.fn_name
+ "tmp"
932 self
.e_tmp
= Decode2ToExecute1Type(name
=name
, opkls
=self
.opkls
,
933 regreduce_en
=self
.regreduce_en
)
935 # set up submodule decoders
936 m
.submodules
.dec
= dec
= self
.dec
937 m
.submodules
.dec_rc
= self
.dec_rc
= dec_rc
= DecodeRC(self
.dec
)
938 m
.submodules
.dec_oe
= dec_oe
= DecodeOE(self
.dec
, op
)
941 # and SVP64 RM mode decoder
942 m
.submodules
.sv_rm_dec
= rm_dec
= self
.rm_dec
944 # copy op from decoder
945 comb
+= self
.op
.eq(self
.dec
.op
)
947 # copy instruction through...
948 for i
in [do
.insn
, dec_rc
.insn_in
, dec_oe
.insn_in
, ]:
949 comb
+= i
.eq(self
.dec
.opcode_in
)
951 # ...and subdecoders' input fields
952 comb
+= dec_rc
.sel_in
.eq(self
.op_get("rc_sel"))
953 comb
+= dec_oe
.sel_in
.eq(self
.op_get("rc_sel")) # XXX should be OE sel
956 comb
+= self
.do_copy("msr", msr
)
957 comb
+= self
.do_copy("cia", cia
)
958 comb
+= self
.do_copy("svstate", svstate
)
960 # set up instruction type
961 # no op: defaults to OP_ILLEGAL
962 internal_op
= self
.op_get("internal_op")
963 comb
+= self
.do_copy("insn_type", internal_op
)
965 # function unit for decoded instruction: requires minor redirect
967 fn
= self
.op_get("function_unit")
968 spr
= Signal(10, reset_less
=True)
969 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
971 # Microwatt doesn't implement the partition table
972 # instead has PRTBL register (SPR) to point to process table
973 # Kestrel has a KAIVB SPR to "rebase" exceptions. rebasing is normally
974 # done with Hypervisor Mode which is not implemented (yet)
976 is_mmu_spr
= Signal()
977 is_trap_spr
= Signal()
978 comb
+= is_spr_mv
.eq((internal_op
== MicrOp
.OP_MTSPR
) |
979 (internal_op
== MicrOp
.OP_MFSPR
))
980 comb
+= is_mmu_spr
.eq((spr
== SPR
.DSISR
.value
) |
981 (spr
== SPR
.DAR
.value
) |
982 (spr
== SPR
.PRTBL
.value
) |
983 (spr
== SPR
.PIDR
.value
))
984 comb
+= is_trap_spr
.eq((spr
== SPR
.KAIVB
.value
)
986 # MMU must receive MMU SPRs
987 with m
.If(is_spr_mv
& (fn
== Function
.SPR
) & is_mmu_spr
):
988 comb
+= self
.do_copy("fn_unit", Function
.MMU
)
989 comb
+= self
.do_copy("insn_type", internal_op
)
990 # TRAP must receive TRAP SPR KAIVB
991 with m
.If(is_spr_mv
& (fn
== Function
.SPR
) & is_trap_spr
):
992 comb
+= self
.do_copy("fn_unit", Function
.TRAP
)
993 comb
+= self
.do_copy("insn_type", internal_op
)
994 # SPR pipe must *not* receive MMU or TRAP SPRs
995 with m
.Elif(is_spr_mv
& ((fn
== Function
.MMU
) & ~is_mmu_spr
) &
996 ((fn
== Function
.TRAP
) & ~is_trap_spr
)):
997 comb
+= self
.do_copy("fn_unit", Function
.NONE
)
998 comb
+= self
.do_copy("insn_type", MicrOp
.OP_ILLEGAL
)
1001 comb
+= self
.do_copy("fn_unit", fn
)
1004 if self
.needs_field("zero_a", "in1_sel"):
1005 m
.submodules
.dec_ai
= dec_ai
= DecodeAImm(self
.dec
)
1006 comb
+= dec_ai
.sv_nz
.eq(self
.sv_a_nz
)
1007 comb
+= dec_ai
.sel_in
.eq(self
.op_get("in1_sel"))
1008 comb
+= self
.do_copy("zero_a", dec_ai
.immz_out
) # RA==0 detected
1009 if self
.needs_field("imm_data", "in2_sel"):
1010 m
.submodules
.dec_bi
= dec_bi
= DecodeBImm(self
.dec
)
1011 comb
+= dec_bi
.sel_in
.eq(self
.op_get("in2_sel"))
1012 comb
+= self
.do_copy("imm_data", dec_bi
.imm_out
) # imm in RB
1015 comb
+= self
.do_copy("rc", dec_rc
.rc_out
)
1017 # OE only enabled when SVP64 not active
1018 with m
.If(~self
.is_svp64_mode
):
1019 comb
+= self
.do_copy("oe", dec_oe
.oe_out
)
1021 comb
+= self
.do_copy("oe", dec_oe
.oe_out
)
1023 # CR in/out - note: these MUST match with what happens in
1025 rc_out
= self
.dec_rc
.rc_out
.data
1026 with m
.Switch(self
.op_get("cr_out")):
1027 with m
.Case(CROutSel
.CR0
, CROutSel
.CR1
):
1028 comb
+= self
.do_copy("write_cr0", rc_out
) # only when RC=1
1029 with m
.Case(CROutSel
.BF
, CROutSel
.BT
):
1030 comb
+= self
.do_copy("write_cr0", 1)
1032 comb
+= self
.do_copy("input_cr", self
.op_get("cr_in")) # CR in
1033 comb
+= self
.do_copy("output_cr", self
.op_get("cr_out")) # CR out
1036 # connect up SVP64 RM Mode decoding. however... we need a shorter
1037 # path, for the LDST bit-reverse detection. so perform partial
1038 # decode when SVP64 is detected. then, bit-reverse mode can be
1039 # quickly determined, and the Decoder result MUXed over to
1040 # the alternative decoder, svdecldst. what a mess... *sigh*
1041 sv_ptype
= self
.op_get("SV_Ptype")
1042 fn
= self
.op_get("function_unit")
1043 comb
+= rm_dec
.fn_in
.eq(fn
) # decode needs to know Fn type
1044 comb
+= rm_dec
.ptype_in
.eq(sv_ptype
) # Single/Twin predicated
1045 comb
+= rm_dec
.rc_in
.eq(rc_out
) # Rc=1
1046 comb
+= rm_dec
.rm_in
.eq(self
.sv_rm
) # SVP64 RM mode
1047 if self
.needs_field("imm_data", "in2_sel"):
1048 bzero
= dec_bi
.imm_out
.ok
& ~dec_bi
.imm_out
.data
.bool()
1049 comb
+= rm_dec
.ldst_imz_in
.eq(bzero
) # B immediate is zero
1051 # main PowerDecoder2 determines if different SVP64 modes enabled
1052 # detect if SVP64 FFT mode enabled (really bad hack),
1053 # exclude fcfids and others
1054 # XXX this is a REALLY bad hack, REALLY has to be done better.
1055 # likely with a sub-decoder.
1057 comb
+= major
.eq(self
.dec
.opcode_in
[26:32])
1058 xo5
= Signal(1) # 1 bit from Minor 59 XO field == 0b0XXXX
1059 comb
+= xo5
.eq(self
.dec
.opcode_in
[5])
1060 xo
= Signal(5) # 5 bits from Minor 59 fcfids == 0b01110
1061 comb
+= xo
.eq(self
.dec
.opcode_in
[1:6])
1062 comb
+= self
.use_svp64_fft
.eq((major
== 59) & (xo5
== 0b0) &
1065 # decoded/selected instruction flags
1066 comb
+= self
.do_copy("data_len", self
.op_get("ldst_len"))
1067 comb
+= self
.do_copy("invert_in", self
.op_get("inv_a"))
1068 comb
+= self
.do_copy("invert_out", self
.op_get("inv_out"))
1069 comb
+= self
.do_copy("input_carry", self
.op_get("cry_in"))
1070 comb
+= self
.do_copy("output_carry", self
.op_get("cry_out"))
1071 comb
+= self
.do_copy("is_32bit", self
.op_get("is_32b"))
1072 comb
+= self
.do_copy("is_signed", self
.op_get("sgn"))
1073 lk
= self
.op_get("lk")
1076 comb
+= self
.do_copy("lk", self
.dec
.LK
) # XXX TODO: accessor
1078 comb
+= self
.do_copy("byte_reverse", self
.op_get("br"))
1079 comb
+= self
.do_copy("sign_extend", self
.op_get("sgn_ext"))
1080 comb
+= self
.do_copy("ldst_mode", self
.op_get("upd")) # LD/ST mode
1081 comb
+= self
.do_copy("reserve", self
.op_get("rsrv")) # atomic
1083 # copy over SVP64 input record fields (if they exist)
1085 # TODO, really do we have to do these explicitly?? sigh
1086 # for (field, _) in sv_input_record_layout:
1087 # comb += self.do_copy(field, self.rm_dec.op_get(field))
1088 comb
+= self
.do_copy("sv_saturate", self
.rm_dec
.saturate
)
1089 comb
+= self
.do_copy("sv_Ptype", self
.rm_dec
.ptype_in
)
1090 comb
+= self
.do_copy("sv_ldstmode", self
.rm_dec
.ldstmode
)
1091 # these get set up based on incoming mask bits. TODO:
1092 # pass in multiple bits (later, when SIMD backends are enabled)
1093 with m
.If(self
.rm_dec
.pred_sz
):
1094 comb
+= self
.do_copy("sv_pred_sz", ~self
.pred_sm
)
1095 with m
.If(self
.rm_dec
.pred_dz
):
1096 comb
+= self
.do_copy("sv_pred_dz", ~self
.pred_dm
)
1101 class PowerDecode2(PowerDecodeSubset
):
1102 """PowerDecode2: the main instruction decoder.
1104 whilst PowerDecode is responsible for decoding the actual opcode, this
1105 module encapsulates further specialist, sparse information and
1106 expansion of fields that is inconvenient to have in the CSV files.
1107 for example: the encoding of the immediates, which are detected
1108 and expanded out to their full value from an annotated (enum)
1111 implicit register usage is also set up, here. for example: OP_BC
1112 requires implicitly reading CTR, OP_RFID requires implicitly writing
1115 in addition, PowerDecoder2 is responsible for detecting whether
1116 instructions are illegal (or privileged) or not, and instead of
1117 just leaving at that, *replacing* the instruction to execute with
1118 a suitable alternative (trap).
1120 LDSTExceptions are done the cycle _after_ they're detected (after
1121 they come out of LDSTCompUnit). basically despite the instruction
1122 being decoded, the results of the decode are completely ignored
1123 and "exception.happened" used to set the "actual" instruction to
1124 "OP_TRAP". the LDSTException data structure gets filled in,
1125 in the CompTrapOpSubset and that's what it fills in SRR.
1127 to make this work, TestIssuer must notice "exception.happened"
1128 after the (failed) LD/ST and copies the LDSTException info from
1129 the output, into here (PowerDecoder2). without incrementing PC.
1131 also instr_fault works the same way: the instruction is "rewritten"
1132 so that the "fake" op that gets created is OP_FETCH_FAILED
1135 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False,
1136 state
=None, svp64_en
=True, regreduce_en
=False):
1137 super().__init
__(dec
, opkls
, fn_name
, final
, state
, svp64_en
,
1139 self
.ldst_exc
= LDSTException("dec2_exc") # rewrites as OP_TRAP
1140 self
.instr_fault
= Signal() # rewrites instruction as OP_FETCH_FAILED
1143 self
.cr_out_isvec
= Signal(1, name
="cr_out_isvec")
1144 self
.cr_in_isvec
= Signal(1, name
="cr_in_isvec")
1145 self
.cr_in_b_isvec
= Signal(1, name
="cr_in_b_isvec")
1146 self
.cr_in_o_isvec
= Signal(1, name
="cr_in_o_isvec")
1147 self
.in1_isvec
= Signal(1, name
="reg_a_isvec")
1148 self
.in2_isvec
= Signal(1, name
="reg_b_isvec")
1149 self
.in3_isvec
= Signal(1, name
="reg_c_isvec")
1150 self
.o_isvec
= Signal(7, name
="reg_o_isvec")
1151 self
.o2_isvec
= Signal(7, name
="reg_o2_isvec")
1152 self
.in1_step
= Signal(7, name
="reg_a_step")
1153 self
.in2_step
= Signal(7, name
="reg_b_step")
1154 self
.in3_step
= Signal(7, name
="reg_c_step")
1155 self
.o_step
= Signal(7, name
="reg_o_step")
1156 self
.o2_step
= Signal(7, name
="reg_o2_step")
1157 self
.remap_active
= Signal(5, name
="remap_active") # per reg
1158 self
.no_in_vec
= Signal(1, name
="no_in_vec") # no inputs vector
1159 self
.no_out_vec
= Signal(1, name
="no_out_vec") # no outputs vector
1160 self
.loop_continue
= Signal(1, name
="loop_continue")
1162 self
.no_in_vec
= Const(1, 1)
1163 self
.no_out_vec
= Const(1, 1)
1164 self
.loop_continue
= Const(0, 1)
1166 def get_col_subset(self
, opkls
):
1167 subset
= super().get_col_subset(opkls
)
1168 subset
.add("asmcode")
1169 subset
.add("in1_sel")
1170 subset
.add("in2_sel")
1171 subset
.add("in3_sel")
1172 subset
.add("out_sel")
1174 subset
.add("sv_in1")
1175 subset
.add("sv_in2")
1176 subset
.add("sv_in3")
1177 subset
.add("sv_out")
1178 subset
.add("sv_out2")
1179 subset
.add("sv_cr_in")
1180 subset
.add("sv_cr_out")
1181 subset
.add("SV_Etype")
1182 subset
.add("SV_Ptype")
1183 # from SVP64RMModeDecode
1184 for (field
, _
) in sv_input_record_layout
:
1187 subset
.add("internal_op")
1191 def elaborate(self
, platform
):
1192 m
= super().elaborate(platform
)
1195 op
, e_out
, do_out
= self
.op
, self
.e
, self
.e
.do
1196 dec_spr
, msr
, cia
, ext_irq
= state
.dec
, state
.msr
, state
.pc
, state
.eint
1197 rc_out
= self
.dec_rc
.rc_out
.data
1201 # fill in for a normal instruction (not an exception)
1202 # copy over if non-exception, non-privileged etc. is detected
1204 # set up submodule decoders
1205 m
.submodules
.dec_a
= dec_a
= DecodeA(self
.dec
, op
, self
.regreduce_en
)
1206 m
.submodules
.dec_b
= dec_b
= DecodeB(self
.dec
, op
)
1207 m
.submodules
.dec_c
= dec_c
= DecodeC(self
.dec
, op
)
1208 m
.submodules
.dec_o
= dec_o
= DecodeOut(self
.dec
, op
, self
.regreduce_en
)
1209 m
.submodules
.dec_o2
= dec_o2
= DecodeOut2(self
.dec
, op
)
1210 m
.submodules
.dec_cr_in
= self
.dec_cr_in
= DecodeCRIn(self
.dec
, op
)
1211 m
.submodules
.dec_cr_out
= self
.dec_cr_out
= DecodeCROut(self
.dec
, op
)
1212 comb
+= dec_a
.sv_nz
.eq(self
.sv_a_nz
)
1215 # and SVP64 Extra decoders
1216 m
.submodules
.crout_svdec
= crout_svdec
= SVP64CRExtra()
1217 m
.submodules
.crin_svdec
= crin_svdec
= SVP64CRExtra()
1218 m
.submodules
.crin_svdec_b
= crin_svdec_b
= SVP64CRExtra()
1219 m
.submodules
.crin_svdec_o
= crin_svdec_o
= SVP64CRExtra()
1220 m
.submodules
.in1_svdec
= in1_svdec
= SVP64RegExtra()
1221 m
.submodules
.in2_svdec
= in2_svdec
= SVP64RegExtra()
1222 m
.submodules
.in3_svdec
= in3_svdec
= SVP64RegExtra()
1223 m
.submodules
.o_svdec
= o_svdec
= SVP64RegExtra()
1224 m
.submodules
.o2_svdec
= o2_svdec
= SVP64RegExtra()
1226 # debug access to cr svdec (used in get_pdecode_cr_in/out)
1227 self
.crout_svdec
= crout_svdec
1228 self
.crin_svdec
= crin_svdec
1230 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
1231 reg
= Signal(5, reset_less
=True)
1233 # copy instruction through...
1234 for i
in [do
.insn
, dec_a
.insn_in
, dec_b
.insn_in
,
1235 self
.dec_cr_in
.insn_in
, self
.dec_cr_out
.insn_in
,
1236 dec_c
.insn_in
, dec_o
.insn_in
, dec_o2
.insn_in
]:
1237 comb
+= i
.eq(self
.dec
.opcode_in
)
1240 comb
+= self
.dec_cr_in
.sel_in
.eq(self
.op_get("cr_in"))
1241 comb
+= self
.dec_cr_out
.sel_in
.eq(self
.op_get("cr_out"))
1242 comb
+= self
.dec_cr_out
.rc_in
.eq(rc_out
)
1245 comb
+= self
.do_copy("read_cr_whole", self
.dec_cr_in
.whole_reg
)
1246 comb
+= self
.do_copy("write_cr_whole", self
.dec_cr_out
.whole_reg
)
1248 # ...and subdecoders' input fields
1249 comb
+= dec_a
.sel_in
.eq(self
.op_get("in1_sel"))
1250 comb
+= dec_b
.sel_in
.eq(self
.op_get("in2_sel"))
1251 comb
+= dec_c
.sel_in
.eq(self
.op_get("in3_sel"))
1252 comb
+= dec_o
.sel_in
.eq(self
.op_get("out_sel"))
1253 comb
+= dec_o2
.sel_in
.eq(self
.op_get("out_sel"))
1255 comb
+= dec_o2
.svp64_fft_mode
.eq(self
.use_svp64_fft
)
1256 if hasattr(do
, "lk"):
1257 comb
+= dec_o2
.lk
.eq(do
.lk
)
1260 # now do the SVP64 munging. op.SV_Etype and op.sv_in1 comes from
1261 # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
1262 # which in turn were auto-generated by sv_analysis.py
1263 extra
= self
.sv_rm
.extra
# SVP64 extra bits 10:18
1268 comb
+= crout_svdec
.idx
.eq(self
.op_get("sv_cr_out"))
1269 comb
+= self
.cr_out_isvec
.eq(crout_svdec
.isvec
)
1272 # CR in - selection slightly different due to shared CR field sigh
1273 cr_a_idx
= Signal(SVEXTRA
)
1274 cr_b_idx
= Signal(SVEXTRA
)
1276 # these change slightly, when decoding BA/BB. really should have
1277 # their own separate CSV column: sv_cr_in1 and sv_cr_in2, but hey
1278 comb
+= cr_a_idx
.eq(self
.op_get("sv_cr_in"))
1279 comb
+= cr_b_idx
.eq(SVEXTRA
.NONE
)
1280 with m
.If(self
.op_get("sv_cr_in") == SVEXTRA
.Idx_1_2
.value
):
1281 comb
+= cr_a_idx
.eq(SVEXTRA
.Idx1
)
1282 comb
+= cr_b_idx
.eq(SVEXTRA
.Idx2
)
1284 comb
+= self
.cr_in_isvec
.eq(crin_svdec
.isvec
)
1285 comb
+= self
.cr_in_b_isvec
.eq(crin_svdec_b
.isvec
)
1286 comb
+= self
.cr_in_o_isvec
.eq(crin_svdec_o
.isvec
)
1288 # indices are slightly different, BA/BB mess sorted above
1289 comb
+= crin_svdec
.idx
.eq(cr_a_idx
) # SVP64 CR in A
1290 comb
+= crin_svdec_b
.idx
.eq(cr_b_idx
) # SVP64 CR in B
1292 comb
+= crin_svdec_o
.idx
.eq(self
.op_get("sv_cr_out"))
1294 # get SVSTATE srcstep (TODO: elwidth etc.) needed below
1295 vl
= Signal
.like(self
.state
.svstate
.vl
)
1296 subvl
= Signal
.like(self
.rm_dec
.rm_in
.subvl
)
1297 srcstep
= Signal
.like(self
.state
.svstate
.srcstep
)
1298 dststep
= Signal
.like(self
.state
.svstate
.dststep
)
1299 ssubstep
= Signal
.like(self
.state
.svstate
.ssubstep
)
1300 dsubstep
= Signal
.like(self
.state
.svstate
.ssubstep
)
1301 comb
+= vl
.eq(self
.state
.svstate
.vl
)
1302 comb
+= subvl
.eq(self
.rm_dec
.rm_in
.subvl
)
1303 comb
+= srcstep
.eq(self
.state
.svstate
.srcstep
)
1304 comb
+= dststep
.eq(self
.state
.svstate
.dststep
)
1305 comb
+= ssubstep
.eq(self
.state
.svstate
.ssubstep
)
1306 comb
+= dsubstep
.eq(self
.state
.svstate
.dsubstep
)
1308 in1_step
, in2_step
= self
.in1_step
, self
.in2_step
1309 in3_step
= self
.in3_step
1310 o_step
, o2_step
= self
.o_step
, self
.o2_step
1312 # multiply vl by subvl - note that this is only 7 bit!
1313 # when elwidth overrides get involved this will have to go up
1315 comb
+= vmax
.eq(vl
*(subvl
+1))
1317 # registers a, b, c and out and out2 (LD/ST EA)
1318 sv_etype
= self
.op_get("SV_Etype")
1319 for i
, stuff
in enumerate((
1320 ("RA", e
.read_reg1
, dec_a
.reg_out
, in1_svdec
, in1_step
, False),
1321 ("RB", e
.read_reg2
, dec_b
.reg_out
, in2_svdec
, in2_step
, False),
1322 ("RC", e
.read_reg3
, dec_c
.reg_out
, in3_svdec
, in3_step
, False),
1323 ("RT", e
.write_reg
, dec_o
.reg_out
, o_svdec
, o_step
, True),
1324 ("EA", e
.write_ea
, dec_o2
.reg_out
, o2_svdec
, o2_step
, True))):
1325 rname
, to_reg
, fromreg
, svdec
, remapstep
, out
= stuff
1326 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1327 comb
+= svdec
.etype
.eq(sv_etype
) # EXTRA2/3 for this insn
1328 comb
+= svdec
.reg_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1329 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1330 # *screaam* FFT mode needs an extra offset for RB
1331 # similar to FRS/FRT (below). all of this needs cleanup
1332 offs
= Signal(7, name
="offs_"+rname
, reset_less
=True)
1335 # when FFT sv.ffmadd detected, and REMAP not in use,
1336 # automagically add on an extra offset to RB.
1337 # however when REMAP is active, the FFT REMAP
1338 # schedule takes care of this offset.
1339 with m
.If(dec_o2
.reg_out
.ok
& dec_o2
.fp_madd_en
):
1340 with m
.If(~self
.remap_active
[i
]):
1341 with m
.If(svdec
.isvec
):
1342 comb
+= offs
.eq(vl
) # VL for Vectors
1343 # detect if Vectorised: add srcstep/dststep if yes.
1344 # to_reg is 7-bits, outs get dststep added, ins get srcstep
1345 with m
.If(svdec
.isvec
):
1346 selectstep
= dststep
if out
else srcstep
1347 subselect
= dsubstep
if out
else ssubstep
1348 step
= Signal(7, name
="step_%s" % rname
.lower())
1349 with m
.If(self
.remap_active
[i
]):
1350 comb
+= step
.eq((remapstep
*(subvl
+1))+subselect
)
1352 comb
+= step
.eq((selectstep
*(subvl
+1))+subselect
)
1353 # reverse gear goes the opposite way
1354 with m
.If(self
.rm_dec
.reverse_gear
):
1355 comb
+= to_reg
.data
.eq(offs
+svdec
.reg_out
+(vmax
-1-step
))
1357 comb
+= to_reg
.data
.eq(offs
+step
+svdec
.reg_out
)
1359 comb
+= to_reg
.data
.eq(offs
+svdec
.reg_out
)
1361 # SVP64 in/out fields
1362 comb
+= in1_svdec
.idx
.eq(self
.op_get("sv_in1")) # reg #1 (in1_sel)
1363 comb
+= in2_svdec
.idx
.eq(self
.op_get("sv_in2")) # reg #2 (in2_sel)
1364 comb
+= in3_svdec
.idx
.eq(self
.op_get("sv_in3")) # reg #3 (in3_sel)
1365 comb
+= o_svdec
.idx
.eq(self
.op_get("sv_out")) # output (out_sel)
1367 comb
+= o2_svdec
.idx
.eq(self
.op_get("sv_out2"))
1368 # XXX TODO - work out where this should come from. the problem is
1369 # that LD-with-update is implied (computed from "is instruction in
1370 # "update mode" rather than specified cleanly as its own CSV column
1372 # output reg-is-vectorised (and when no in/out is vectorised)
1373 comb
+= self
.in1_isvec
.eq(in1_svdec
.isvec
)
1374 comb
+= self
.in2_isvec
.eq(in2_svdec
.isvec
)
1375 comb
+= self
.in3_isvec
.eq(in3_svdec
.isvec
)
1376 comb
+= self
.o_isvec
.eq(o_svdec
.isvec
)
1377 comb
+= self
.o2_isvec
.eq(o2_svdec
.isvec
)
1379 # urrr... don't ask... the implicit register FRS in FFT mode
1380 # "tracks" FRT exactly except it's offset by VL. rather than
1381 # mess up the above with if-statements, override it here.
1382 # same trick is applied to FRA, above, but it's a lot cleaner, there
1383 with m
.If(dec_o2
.reg_out
.ok
& dec_o2
.fp_madd_en
):
1385 with m
.If(~self
.remap_active
[4]):
1386 with m
.If(o2_svdec
.isvec
):
1387 comb
+= offs
.eq(vl
) # VL for Vectors
1389 comb
+= offs
.eq(1) # add 1 if scalar
1390 svdec
= o_svdec
# yes take source as o_svdec...
1391 with m
.If(svdec
.isvec
):
1392 step
= Signal(7, name
="step_%s" % rname
.lower())
1393 with m
.If(self
.remap_active
[4]):
1394 comb
+= step
.eq(o2_step
)
1396 comb
+= step
.eq(dststep
)
1397 # reverse gear goes the opposite way
1398 with m
.If(self
.rm_dec
.reverse_gear
):
1399 roffs
= offs
+(vl
-1-step
)
1400 comb
+= to_reg
.data
.eq(roffs
+svdec
.reg_out
)
1402 comb
+= to_reg
.data
.eq(offs
+step
+svdec
.reg_out
)
1404 comb
+= to_reg
.data
.eq(offs
+svdec
.reg_out
)
1405 # ... but write to *second* output
1406 comb
+= self
.o2_isvec
.eq(svdec
.isvec
)
1407 comb
+= o2_svdec
.idx
.eq(self
.op_get("sv_out"))
1409 # TODO add SPRs here. must be True when *all* are scalar
1410 l
= map(lambda svdec
: svdec
.isvec
, [in1_svdec
, in2_svdec
, in3_svdec
,
1411 crin_svdec
, crin_svdec_b
,
1413 comb
+= self
.no_in_vec
.eq(~
Cat(*l
).bool()) # all input scalar
1414 l
= map(lambda svdec
: svdec
.isvec
, [
1415 o2_svdec
, o_svdec
, crout_svdec
])
1416 # in mapreduce mode, scalar out is *allowed*
1417 with m
.If(self
.rm_dec
.mode
== SVP64RMMode
.MAPREDUCE
.value
):
1418 comb
+= self
.no_out_vec
.eq(0)
1421 comb
+= self
.no_out_vec
.eq(~
Cat(*l
).bool())
1422 # now create a general-purpose "test" as to whether looping
1423 # should continue. this doesn't include predication bit-tests
1424 loop
= self
.loop_continue
1425 with m
.Switch(self
.op_get("SV_Ptype")):
1426 with m
.Case(SVPtype
.P2
.value
):
1428 # TODO: *and cache-inhibited LD/ST!*
1429 comb
+= loop
.eq(~
(self
.no_in_vec | self
.no_out_vec
))
1430 with m
.Case(SVPtype
.P1
.value
):
1431 # single-predication, test relies on dest only
1432 comb
+= loop
.eq(~self
.no_out_vec
)
1434 # not an SV operation, no looping
1437 # condition registers (CR)
1438 for to_reg
, cr
, name
, svdec
, out
in (
1439 (e
.read_cr1
, self
.dec_cr_in
, "cr_bitfield", crin_svdec
, 0),
1440 (e
.read_cr2
, self
.dec_cr_in
, "cr_bitfield_b", crin_svdec_b
, 0),
1441 (e
.read_cr3
, self
.dec_cr_in
, "cr_bitfield_o", crin_svdec_o
, 0),
1442 (e
.write_cr
, self
.dec_cr_out
, "cr_bitfield", crout_svdec
, 1)):
1443 fromreg
= getattr(cr
, name
)
1444 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1445 comb
+= svdec
.etype
.eq(sv_etype
) # EXTRA2/3 for this insn
1446 comb
+= svdec
.cr_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1447 with m
.If(svdec
.isvec
):
1448 # check if this is CR0 or CR1: treated differently
1449 # (does not "listen" to EXTRA2/3 spec for a start)
1450 # also: the CRs start from completely different locations
1451 step
= dststep
if out
else srcstep
1452 with m
.If(cr
.sv_override
== 1): # CR0
1453 offs
= SVP64CROffs
.CR0
1454 comb
+= to_reg
.data
.eq(step
+offs
)
1455 with m
.Elif(cr
.sv_override
== 2): # CR1
1456 offs
= SVP64CROffs
.CR1
1457 comb
+= to_reg
.data
.eq(step
+1)
1459 comb
+= to_reg
.data
.eq(step
+svdec
.cr_out
) # 7-bit out
1461 comb
+= to_reg
.data
.eq(svdec
.cr_out
) # 7-bit output
1462 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1464 # sigh must determine if RA is nonzero (7 bit)
1465 comb
+= self
.sv_a_nz
.eq(e
.read_reg1
.data
!= Const(0, 7))
1467 # connect up to/from read/write GPRs
1468 for to_reg
, fromreg
in ((e
.read_reg1
, dec_a
.reg_out
),
1469 (e
.read_reg2
, dec_b
.reg_out
),
1470 (e
.read_reg3
, dec_c
.reg_out
),
1471 (e
.write_reg
, dec_o
.reg_out
),
1472 (e
.write_ea
, dec_o2
.reg_out
)):
1473 comb
+= to_reg
.data
.eq(fromreg
.data
)
1474 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1476 # connect up to/from read/write CRs
1477 for to_reg
, cr
, name
in (
1478 (e
.read_cr1
, self
.dec_cr_in
, "cr_bitfield", ),
1479 (e
.read_cr2
, self
.dec_cr_in
, "cr_bitfield_b", ),
1480 (e
.read_cr3
, self
.dec_cr_in
, "cr_bitfield_o", ),
1481 (e
.write_cr
, self
.dec_cr_out
, "cr_bitfield", )):
1482 fromreg
= getattr(cr
, name
)
1483 comb
+= to_reg
.data
.eq(fromreg
.data
)
1484 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1487 comb
+= self
.rm_dec
.ldst_ra_vec
.eq(self
.in1_isvec
) # RA is vector
1490 comb
+= e
.read_spr1
.eq(dec_a
.spr_out
)
1491 comb
+= e
.write_spr
.eq(dec_o
.spr_out
)
1493 # Fast regs out including SRR0/1/SVSRR0
1494 comb
+= e
.read_fast1
.eq(dec_a
.fast_out
)
1495 comb
+= e
.read_fast2
.eq(dec_b
.fast_out
)
1496 comb
+= e
.write_fast1
.eq(dec_o
.fast_out
) # SRR0 (OP_RFID)
1497 comb
+= e
.write_fast2
.eq(dec_o2
.fast_out
) # SRR1 (ditto)
1498 comb
+= e
.write_fast3
.eq(dec_o2
.fast_out3
) # SVSRR0 (ditto)
1499 # and State regs (DEC, TB)
1500 comb
+= e
.read_state1
.eq(dec_a
.state_out
) # DEC/TB
1501 comb
+= e
.write_state1
.eq(dec_o
.state_out
) # DEC/TB
1503 # sigh this is exactly the sort of thing for which the
1504 # decoder is designed to not need. MTSPR, MFSPR and others need
1505 # access to the XER bits. however setting e.oe is not appropriate
1506 internal_op
= self
.op_get("internal_op")
1507 with m
.If(internal_op
== MicrOp
.OP_MFSPR
):
1508 comb
+= e
.xer_in
.eq(0b111) # SO, CA, OV
1509 with m
.If(internal_op
== MicrOp
.OP_CMP
):
1510 comb
+= e
.xer_in
.eq(1 << XERRegsEnum
.SO
) # SO
1511 with m
.If(internal_op
== MicrOp
.OP_MTSPR
):
1512 comb
+= e
.xer_out
.eq(1)
1514 # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
1515 with m
.If(op
.internal_op
== MicrOp
.OP_TRAP
):
1516 # *DO NOT* call self.trap here. that would reset absolutely
1517 # everything including destroying read of RA and RB.
1518 comb
+= self
.do_copy("trapaddr", 0x70) # strip first nibble
1520 ####################
1521 # ok so the instruction's been decoded, blah blah, however
1522 # now we need to determine if it's actually going to go ahead...
1523 # *or* if in fact it's a privileged operation, whether there's
1524 # an external interrupt, etc. etc. this is a simple priority
1525 # if-elif-elif sequence. decrement takes highest priority,
1526 # EINT next highest, privileged operation third.
1528 # check if instruction is privileged
1529 is_priv_insn
= instr_is_priv(m
, op
.internal_op
, e
.do
.insn
)
1531 # different IRQ conditions
1532 ext_irq_ok
= Signal()
1533 dec_irq_ok
= Signal()
1536 ldst_exc
= self
.ldst_exc
1538 comb
+= ext_irq_ok
.eq(ext_irq
& msr
[MSR
.EE
]) # v3.0B p944 (MSR.EE)
1539 comb
+= dec_irq_ok
.eq(dec_spr
[63] & msr
[MSR
.EE
]) # 6.5.11 p1076
1540 comb
+= priv_ok
.eq(is_priv_insn
& msr
[MSR
.PR
])
1541 comb
+= illeg_ok
.eq(op
.internal_op
== MicrOp
.OP_ILLEGAL
)
1543 # absolute top priority: check for an instruction failed
1544 with m
.If(self
.instr_fault
):
1545 comb
+= self
.e
.eq(0) # reset eeeeeverything
1546 comb
+= self
.do_copy("insn", self
.dec
.opcode_in
, True)
1547 comb
+= self
.do_copy("insn_type", MicrOp
.OP_FETCH_FAILED
, True)
1548 comb
+= self
.do_copy("fn_unit", Function
.MMU
, True)
1549 comb
+= self
.do_copy("cia", self
.state
.pc
, True) # PC
1550 comb
+= self
.do_copy("msr", self
.state
.msr
, True) # MSR
1551 # special override on internal_op, due to being a "fake" op
1552 comb
+= self
.dec
.op
.internal_op
.eq(MicrOp
.OP_FETCH_FAILED
)
1554 # LD/ST exceptions. TestIssuer copies the exception info at us
1555 # after a failed LD/ST.
1556 with m
.Elif(ldst_exc
.happened
):
1557 with m
.If(ldst_exc
.alignment
):
1558 self
.trap(m
, TT
.MEMEXC
, 0x600)
1559 with m
.Elif(ldst_exc
.instr_fault
):
1560 with m
.If(ldst_exc
.segment_fault
):
1561 self
.trap(m
, TT
.MEMEXC
, 0x480)
1563 # pass exception info to trap to create SRR1
1564 self
.trap(m
, TT
.MEMEXC
, 0x400, ldst_exc
)
1566 with m
.If(ldst_exc
.segment_fault
):
1567 self
.trap(m
, TT
.MEMEXC
, 0x380)
1569 self
.trap(m
, TT
.MEMEXC
, 0x300)
1571 # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
1572 with m
.Elif(dec_irq_ok
):
1573 self
.trap(m
, TT
.DEC
, 0x900) # v3.0B 6.5 p1065
1575 # external interrupt? only if MSR.EE set
1576 with m
.Elif(ext_irq_ok
):
1577 self
.trap(m
, TT
.EINT
, 0x500)
1579 # privileged instruction trap
1580 with m
.Elif(priv_ok
):
1581 self
.trap(m
, TT
.PRIV
, 0x700)
1583 # illegal instruction must redirect to trap. this is done by
1584 # *overwriting* the decoded instruction and starting again.
1585 # (note: the same goes for interrupts and for privileged operations,
1586 # just with different trapaddr and traptype)
1587 with m
.Elif(illeg_ok
):
1588 # illegal instruction trap
1589 self
.trap(m
, TT
.ILLEG
, 0x700)
1591 # no exception, just copy things to the output
1595 ####################
1596 # follow-up after trap/irq to set up SRR0/1
1598 # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
1599 # Note: OP_SC could actually be modified to just be a trap
1600 with m
.If((do_out
.insn_type
== MicrOp
.OP_TRAP
) |
1601 (do_out
.insn_type
== MicrOp
.OP_SC
)):
1602 # TRAP write fast1 = SRR0
1603 comb
+= e_out
.write_fast1
.data
.eq(FastRegsEnum
.SRR0
) # SRR0
1604 comb
+= e_out
.write_fast1
.ok
.eq(1)
1605 # TRAP write fast2 = SRR1
1606 comb
+= e_out
.write_fast2
.data
.eq(FastRegsEnum
.SRR1
) # SRR1
1607 comb
+= e_out
.write_fast2
.ok
.eq(1)
1608 # TRAP write fast2 = SRR1
1609 comb
+= e_out
.write_fast3
.data
.eq(FastRegsEnum
.SVSRR0
) # SVSRR0
1610 comb
+= e_out
.write_fast3
.ok
.eq(1)
1612 # RFID: needs to read SRR0/1
1613 with m
.If(do_out
.insn_type
== MicrOp
.OP_RFID
):
1614 # TRAP read fast1 = SRR0
1615 comb
+= e_out
.read_fast1
.data
.eq(FastRegsEnum
.SRR0
) # SRR0
1616 comb
+= e_out
.read_fast1
.ok
.eq(1)
1617 # TRAP read fast2 = SRR1
1618 comb
+= e_out
.read_fast2
.data
.eq(FastRegsEnum
.SRR1
) # SRR1
1619 comb
+= e_out
.read_fast2
.ok
.eq(1)
1620 # TRAP read fast2 = SVSRR0
1621 comb
+= e_out
.read_fast3
.data
.eq(FastRegsEnum
.SVSRR0
) # SVSRR0
1622 comb
+= e_out
.read_fast3
.ok
.eq(1)
1624 # annoying simulator bug.
1625 # asmcode may end up getting used for perfcounters?
1626 asmcode
= self
.op_get("asmcode")
1627 if hasattr(e_out
, "asmcode") and asmcode
is not None:
1628 comb
+= e_out
.asmcode
.eq(asmcode
)
1632 def trap(self
, m
, traptype
, trapaddr
, ldst_exc
=None):
1633 """trap: this basically "rewrites" the decoded instruction as a trap
1637 comb
+= e
.eq(0) # reset eeeeeverything
1640 comb
+= self
.do_copy("insn", self
.dec
.opcode_in
, True)
1641 comb
+= self
.do_copy("insn_type", MicrOp
.OP_TRAP
, True)
1642 comb
+= self
.do_copy("fn_unit", Function
.TRAP
, True)
1643 comb
+= self
.do_copy("trapaddr", trapaddr
>> 4, True) # bottom 4 bits
1644 comb
+= self
.do_copy("traptype", traptype
, True) # request type
1645 comb
+= self
.do_copy("ldst_exc", ldst_exc
, True) # request type
1646 comb
+= self
.do_copy("msr", self
.state
.msr
,
1647 True) # copy of MSR "state"
1648 comb
+= self
.do_copy("cia", self
.state
.pc
, True) # copy of PC "state"
1649 comb
+= self
.do_copy("svstate", self
.state
.svstate
, True) # SVSTATE
1652 def get_rdflags(m
, e
, cu
):
1653 """returns a sequential list of the read "ok" flags for a given FU.
1654 this list is in order of the CompUnit input specs
1657 for idx
in range(cu
.n_src
):
1658 regfile
, regname
, _
= cu
.get_in_spec(idx
)
1659 decinfo
= regspec_decode_read(m
, e
, regfile
, regname
)
1660 rdl
.append(decinfo
.okflag
)
1665 if __name__
== '__main__':
1666 pdecode
= create_pdecode()
1667 dec2
= PowerDecode2(pdecode
, svp64_en
=True)
1668 vl
= rtlil
.convert(dec2
, ports
=dec2
.ports() + pdecode
.ports())
1669 with
open("dec2.il", "w") as f
: