src/openpower/decoder/power_enums.py

   1 # SPDX-License-Identifier: LGPL-3-or-later
   2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3 # Copyright (C) 2020, Michael Nolan
   4
   5 """Enums used in OpenPOWER ISA decoding
   6
   7 Note: for SV, from v3.1B p12:
   8
   9     The designated SPR sandbox consists of non-privileged SPRs 704-719 and
  10     privileged SPRs 720-735.
  11
  12 Note: the option exists to select a much shorter list of SPRs, to reduce
  13 regfile size in HDL.  this is SPRreduced and the supported list is in
  14 get_spr_enum
  15 """
  16
  17 from enum import (
  18     auto,
  19     Enum as _Enum,
  20     unique,
  21 )
  22 import csv
  23 import os
  24 from os.path import dirname, join
  25 from collections import namedtuple
  26 import functools
  27
  28
  29 def find_wiki_dir():
  30     filedir = os.path.dirname(os.path.abspath(__file__))
  31     basedir = dirname(dirname(dirname(filedir)))
  32     tabledir = join(basedir, 'openpower')
  33     isatables = join(tabledir, 'isatables')
  34     #print ("find_wiki_dir", isatables)
  35     return isatables
  36
  37
  38 def find_wiki_file(name):
  39     return join(find_wiki_dir(), name)
  40
  41
  42 def get_csv(name):
  43     """gets a not-entirely-csv-file-formatted database, which allows comments
  44     """
  45     file_path = find_wiki_file(name)
  46     with open(file_path, 'r') as csvfile:
  47         csvfile = filter(lambda row: row[0] !='#', csvfile) # strip "#..."
  48         reader = csv.DictReader(csvfile)
  49         return list(reader)
  50
  51
  52 # names of the fields in the tables that don't correspond to an enum
  53 single_bit_flags = ['inv A', 'inv out',
  54                     'cry out', 'BR', 'sgn ext', 'rsrv', '32b',
  55                     'sgn', 'lk', 'sgl pipe']
  56
  57 # default values for fields in the table
  58 default_values = {'unit': "NONE", 'internal op': "OP_ILLEGAL",
  59                   'in1': "RA", 'in2': 'NONE', 'in3': 'NONE', 'out': 'NONE',
  60                   'CR in': 'NONE',
  61                   'ldst len': 'NONE',
  62                   'upd': '0',
  63                   'rc': 'NONE', 'cry in': 'ZERO', 'form': 'NONE'}
  64
  65
  66 def get_signal_name(name):
  67     if name[0].isdigit():
  68         name = "is_" + name
  69     return name.lower().replace(' ', '_')
  70
  71
  72 class Enum(_Enum):
  73     @classmethod
  74     def _missing_(cls, value):
  75         if isinstance(value, str):
  76             try:
  77                 if value == "":
  78                     value = 0
  79                 else:
  80                     value = int(value, 0)
  81             except ValueError:
  82                 pass
  83         keys = {item.name:item for item in cls}
  84         values = {item.value:item for item in cls}
  85         item = keys.get(value, values.get(value))
  86         if item is None:
  87             raise ValueError(value)
  88         return item
  89
  90
  91 # this corresponds to which Function Unit (pipeline-with-Reservation-Stations)
  92 # is to process and guard the operation.  they are roughly divided by having
  93 # the same register input/output signature (X-Form, etc.)
  94
  95
  96 @unique
  97 class Function(Enum):
  98     NONE = 0
  99     ALU = 1 << 1
 100     LDST = 1 << 2
 101     SHIFT_ROT = 1 << 3
 102     LOGICAL = 1 << 4
 103     BRANCH = 1 << 5
 104     CR = 1 << 6
 105     TRAP = 1 << 7
 106     MUL = 1 << 8
 107     DIV = 1 << 9
 108     SPR = 1 << 10
 109     MMU = 1 << 11
 110     SV = 1 << 12  # Simple-V https://libre-soc.org/openpower/sv
 111     VL = 1 << 13  # setvl
 112     FPU = 1 << 14  # FPU
 113
 114     @functools.lru_cache(maxsize=None)
 115     def __repr__(self):
 116         counter = 0
 117         value = int(self.value)
 118         if value != 0:
 119             while value != 0:
 120                 counter += 1
 121                 value >>= 1
 122             counter -= 1
 123             desc = f"(1 << {counter})"
 124         else:
 125             desc = "0"
 126         return f"<{self.__class__.__name__}.{self.name}: {desc}>"
 127
 128
 129 @unique
 130 class Form(Enum):
 131     NONE = 0
 132     I = 1
 133     B = 2
 134     SC = 3
 135     D = 4
 136     DS = 5
 137     DQ = 6
 138     DX = 7
 139     X = 8
 140     XL = 9
 141     XFX = 10
 142     XFL = 11
 143     XX1 = 12
 144     XX2 = 13
 145     XX3 = 14
 146     XX4 = 15
 147     XS = 16
 148     XO = 17
 149     A = 18
 150     M = 19
 151     MD = 20
 152     MDS = 21
 153     VA = 22
 154     VC = 23
 155     VX = 24
 156     EVX = 25
 157     EVS = 26
 158     Z22 = 27
 159     Z23 = 28
 160     SVL = 29  # Simple-V for setvl instruction
 161     SVD = 30  # Simple-V for LD/ST bit-reverse, variant of D-Form
 162     SVDS = 31  # Simple-V for LD/ST bit-reverse, variant of DS-Form
 163     SVM = 32  # Simple-V SHAPE mode
 164     SVM2 = 33  # Simple-V SHAPE2 mode - fits into SVM
 165     SVRM = 34  # Simple-V REMAP mode
 166     TLI = 35  # ternlogi
 167     XB = 36
 168     BM2 = 37 # bmask
 169     SVI = 38  # Simple-V Index Mode
 170     VA2 = 39
 171     SVC = 40
 172     SVR = 41
 173
 174 # Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/
 175
 176
 177 class SVMode(Enum):
 178     NORMAL = auto()
 179     LDST_IDX = auto()
 180     LDST_IMM = auto()
 181     BRANCH = auto()
 182     CROP = auto()
 183
 184
 185 @unique
 186 class SVPtype(Enum):
 187     NONE = 0
 188     P1 = 1
 189     P2 = 2
 190
 191     @classmethod
 192     def _missing_(cls, value):
 193         return {"1P": SVPtype.P1, "2P": SVPtype.P2}[value]
 194
 195
 196 @unique
 197 class SVEtype(Enum):
 198     NONE = 0
 199     EXTRA2 = 1
 200     EXTRA3 = 2
 201
 202
 203 @unique
 204 class SVExtra(Enum):
 205     NONE = 0
 206     Idx0 = 1
 207     Idx1 = 2
 208     Idx2 = 3
 209     Idx3 = 4
 210     Idx_1_2 = 5  # due to weird BA/BB for crops
 211
 212 # Backward compatibility
 213 SVEXTRA = SVExtra
 214
 215
 216 class SVExtraRegType(Enum):
 217     NONE = None
 218     SRC = 's'
 219     DST = 'd'
 220
 221
 222 class SVExtraReg(Enum):
 223     NONE = auto()
 224     RA = auto()
 225     RA_OR_ZERO = RA
 226     RB = auto()
 227     RC = auto()
 228     RS = auto()
 229     RT = auto()
 230     RT_OR_ZERO = RT
 231     FRA = auto()
 232     FRB = auto()
 233     FRC = auto()
 234     FRS = auto()
 235     FRT = auto()
 236     CR = auto()
 237     CR0 = auto()
 238     CR1 = auto()
 239     BF = auto()
 240     BFA = auto()
 241     BA = auto()
 242     BB = auto()
 243     BC = auto()
 244     BI = auto()
 245     BT = auto()
 246     BFT = auto()
 247     WHOLE_REG = auto()
 248     SPR = auto()
 249
 250     @classmethod
 251     def _missing_(cls, value):
 252         selectors = (
 253             In1Sel, In2Sel, In3Sel, CRInSel,
 254             OutSel, CROutSel,
 255         )
 256         if isinstance(value, selectors):
 257             return cls.__members__.get(value.name, cls.NONE)
 258         return super()._missing_(value)
 259
 260
 261 @unique
 262 class SVP64PredMode(Enum):
 263     ALWAYS = 0
 264     INT = 1
 265     CR = 2
 266
 267
 268 @unique
 269 class SVP64PredInt(Enum):
 270     ALWAYS = 0
 271     R3_UNARY = 1
 272     R3 = 2
 273     R3_N = 3
 274     R10 = 4
 275     R10_N = 5
 276     R30 = 6
 277     R30_N = 7
 278
 279
 280 @unique
 281 class SVP64PredCR(Enum):
 282     LT = 0
 283     GE = 1
 284     GT = 2
 285     LE = 3
 286     EQ = 4
 287     NE = 5
 288     SO = 6
 289     NS = 7
 290
 291
 292 @unique
 293 class SVP64RMMode(Enum):
 294     NORMAL = 0
 295     MAPREDUCE = 1
 296     FFIRST = 2
 297     SATURATE = 3
 298     PREDRES = 4
 299     BRANCH = 5
 300
 301
 302 @unique
 303 class SVP64BCPredMode(Enum):
 304     NONE = 0
 305     MASKZERO = 1
 306     MASKONE = 2
 307
 308
 309 @unique
 310 class SVP64BCVLSETMode(Enum):
 311     NONE = 0
 312     VL_INCL = 1
 313     VL_EXCL = 2
 314
 315
 316 # note that these are chosen to be exactly the same as
 317 # SVP64 RM bit 4.  ALL=1 => bit4=1
 318 @unique
 319 class SVP64BCGate(Enum):
 320     ANY = 0
 321     ALL = 1
 322
 323
 324 class SVP64BCCTRMode(Enum):
 325     NONE = 0
 326     TEST = 1
 327     TEST_INV = 2
 328
 329
 330 @unique
 331 class SVP64width(Enum):
 332     DEFAULT = 0
 333     EW_32 = 1
 334     EW_16 = 2
 335     EW_8 = 3
 336
 337
 338 @unique
 339 class SVP64subvl(Enum):
 340     VEC1 = 0
 341     VEC2 = 1
 342     VEC3 = 2
 343     VEC4 = 3
 344
 345
 346 @unique
 347 class SVP64sat(Enum):
 348     NONE = 0
 349     SIGNED = 1
 350     UNSIGNED = 2
 351
 352
 353 @unique
 354 class SVP64LDSTmode(Enum):
 355     NONE = 0
 356     INDEXED = 1
 357     ELSTRIDE = 2
 358     UNITSTRIDE = 3
 359
 360
 361 class RegType(Enum):
 362     GPR = 0
 363     RA = GPR
 364     RB = GPR
 365     RC = GPR
 366     RS = GPR
 367     RT = GPR
 368
 369     FPR = 1
 370     FRA = FPR
 371     FRB = FPR
 372     FRC = FPR
 373     FRS = FPR
 374     FRT = FPR
 375
 376     CR_REG = 2
 377     BF = CR_REG
 378     BFA = CR_REG
 379
 380     CR_BIT = 3
 381     BA = CR_BIT
 382     BB = CR_BIT
 383     BC = CR_BIT
 384     BI = CR_BIT
 385     BT = CR_BIT
 386     BFT = CR_BIT
 387
 388
 389 # supported instructions: make sure to keep up-to-date with CSV files
 390 # just like everything else
 391 _insns = [
 392     "NONE", "add", "addc", "addco", "adde", "addeo",
 393     "addi", "addic", "addic.", "addis",
 394     "addme", "addmeo", "addo", "addze", "addzeo",
 395     "addg6s",
 396     "and", "andc", "andi.", "andis.",
 397     "attn",
 398     "absdu", "absds",                         # AV bitmanip
 399     "absdacs", "absdacu",                     # AV bitmanip
 400     "avgadd",                                 # AV bitmanip
 401     "b", "bc", "bcctr", "bclr", "bctar",
 402     "bmask",                                  # AV bitmanip
 403     "bpermd",
 404     "cbcdtd",
 405     "cdtbcd",
 406     "cmp", "cmpb", "cmpeqb", "cmpi", "cmpl", "cmpli", "cmprb",
 407     "cntlzd", "cntlzw", "cnttzd", "cnttzw",
 408     "cprop", # AV bitmanip
 409     "crand", "crandc", "creqv",
 410     "crnand", "crnor", "cror", "crorc", "crxor",
 411     "darn",
 412     "dcbf", "dcbst", "dcbt", "dcbtst", "dcbz",
 413     "divd", "divde", "divdeo", "divdeu",
 414     "divdeuo", "divdo", "divdu", "divduo", "divw", "divwe", "divweo",
 415     "divweu", "divweuo", "divwo", "divwu", "divwuo",
 416     "eieio", "eqv",
 417     "extsb", "extsh", "extsw", "extswsli",
 418     "fadd", "fadds", "fsub", "fsubs",                   # FP add / sub
 419     "fcfids", "fcfidus", "fsqrts", "fres", "frsqrtes",  # FP stuff
 420     "fdmadds",                                          # DCT FP 3-arg
 421     "fmsubs", "fmadds", "fnmsubs", "fnmadds",           # FP 3-arg
 422     "ffadds", "ffsubs", "ffmuls", "ffdivs",             # FFT FP 2-arg
 423     "ffmsubs", "ffmadds", "ffnmsubs", "ffnmadds",       # FFT FP 3-arg
 424     "fmul", "fmuls", "fdiv", "fdivs",                   # FP mul / div
 425     "fmr", "fabs", "fnabs", "fneg", "fcpsgn",           # FP move/abs/neg
 426     "fsins", "fcoss",                                   # FP SIN/COS
 427     "fmvis",                                            # FP load immediate
 428     "fishmv",                                           # Float Replace Lower-Half Single, Immediate
 429     'grev', 'grev.', 'grevi', 'grevi.',
 430     'grevw', 'grevw.', 'grevwi', 'grevwi.',
 431     "hrfid", "icbi", "icbt", "isel", "isync",
 432     "lbarx", "lbz", "lbzcix", "lbzu", "lbzux", "lbzx",  # load byte
 433     "ld", "ldarx", "ldbrx", "ldu", "ldux", "ldx",       # load double
 434     # "lbzbr", "lbzubr",  # load byte SVP64 bit-reversed
 435     # "ldbr", "ldubr",    # load double SVP64 bit-reversed
 436     "lfs", "lfsx", "lfsu", "lfsux",                     # FP load single
 437     "lfd", "lfdx", "lfdu", "lfdux", "lfiwzx", "lfiwax",  # FP load double
 438     "lha", "lharx", "lhau", "lhaux", "lhax",            # load half
 439     "lhbrx", "lhz", "lhzu", "lhzux", "lhzx",            # more load half
 440     # "lhabr", "lhaubr",  # load half SVP64 bit-reversed
 441     # "lhzbr", "lhzubr",  # more load half SVP64 bit-reversed
 442     "lwa", "lwarx", "lwaux", "lwax", "lwbrx",           # load word
 443     "lwz", "lwzcix", "lwzu", "lwzux", "lwzx",           # more load word
 444     # "lwabr",           # load word SVP64 bit-reversed
 445     # "lwzbr", "lwzubr", # more load word SVP64 bit-reversed
 446     "maddhd", "maddhdu", "maddld",                      # INT multiply-and-add
 447     "mcrf", "mcrxr", "mcrxrx", "mfcr/mfocrf",           # CR mvs
 448     "mfmsr", "mfspr",
 449     "mins", "maxs", "minu", "maxu",                     # AV bitmanip
 450     "modsd", "modsw", "modud", "moduw",
 451     "mtcrf/mtocrf", "mtmsr", "mtmsrd", "mtspr",
 452     "mulhd", "mulhdu", "mulhw", "mulhwu", "mulld", "mulldo",
 453     "mulli", "mullw", "mullwo",
 454     "nand", "neg", "nego",
 455     "nop",
 456     "nor", "or", "orc", "ori", "oris",
 457     "popcntb", "popcntd", "popcntw",
 458     "prtyd", "prtyw",
 459     "rfid",
 460     "rldcl", "rldcr", "rldic", "rldicl", "rldicr", "rldimi",
 461     "rlwimi", "rlwinm",    "rlwnm",
 462     "setb",
 463     "setvl",  # https://libre-soc.org/openpower/sv/setvl
 464     "svindex",  # https://libre-soc.org/openpower/sv/remap
 465     "svremap",  # https://libre-soc.org/openpower/sv/remap - TEMPORARY
 466     "svshape",  # https://libre-soc.org/openpower/sv/remap/#svshape
 467     "svshape2",  # https://libre-soc.org/openpower/sv/remap/discussion TODO
 468     "svstep",  # https://libre-soc.org/openpower/sv/setvl
 469     "sim_cfg",
 470     "slbia", "sld", "slw", "srad", "sradi",
 471     "sraw", "srawi", "srd", "srw",
 472     "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
 473     "std", "stdbrx", "stdcx", "stdu", "stdux", "stdx",
 474     "stfs", "stfsx", "stfsu", "stfux", "stfsux",        # FP store single
 475     "stfd", "stfdx", "stfdu", "stfdux", "stfiwx",       # FP store double
 476     "sth", "sthbrx", "sthcx", "sthu", "sthux", "sthx",
 477     "stw", "stwbrx", "stwcx", "stwu", "stwux", "stwx",
 478     "subf", "subfc", "subfco", "subfe", "subfeo", "subfic",
 479     "subfme", "subfmeo", "subfo", "subfze", "subfzeo",
 480     "sync",
 481     "ternlogi",
 482     "td", "tdi",
 483     "tlbie", "tlbiel", "tlbsync",
 484     "tw", "twi",
 485     "wait",
 486     "xor", "xori", "xoris",
 487 ]
 488
 489 # two-way lookup of instruction-to-index and vice-versa
 490 insns = {}
 491 asmidx = {}
 492 for i, insn in enumerate(_insns):
 493     insns[i] = insn
 494     asmidx[insn] = i
 495
 496 # must be long enough to cover all instructions
 497 asmlen = len(_insns).bit_length()
 498
 499 # Internal Operation numbering.  Add new opcodes here (FPADD, FPMUL etc.)
 500
 501
 502 @unique
 503 class MicrOp(Enum):
 504     OP_ILLEGAL = 0     # important that this is zero (see power_decoder.py)
 505     OP_NOP = 1
 506     OP_ADD = 2
 507     OP_ADDPCIS = 3
 508     OP_AND = 4
 509     OP_ATTN = 5
 510     OP_B = 6
 511     OP_BC = 7
 512     OP_BCREG = 8
 513     OP_BPERM = 9
 514     OP_CMP = 10
 515     OP_CMPB = 11
 516     OP_CMPEQB = 12
 517     OP_CMPRB = 13
 518     OP_CNTZ = 14
 519     OP_CRAND = 15
 520     OP_CRANDC = 16
 521     OP_CREQV = 17
 522     OP_CRNAND = 18
 523     OP_CRNOR = 19
 524     OP_CROR = 20
 525     OP_CRORC = 21
 526     OP_CRXOR = 22
 527     OP_DARN = 23
 528     OP_DCBF = 24
 529     OP_DCBST = 25
 530     OP_DCBT = 26
 531     OP_DCBTST = 27
 532     OP_DCBZ = 28
 533     OP_DIV = 29
 534     OP_DIVE = 30
 535     OP_EXTS = 31
 536     OP_EXTSWSLI = 32
 537     OP_ICBI = 33
 538     OP_ICBT = 34
 539     OP_ISEL = 35
 540     OP_ISYNC = 36
 541     OP_LOAD = 37
 542     OP_STORE = 38
 543     OP_MADDHD = 39
 544     OP_MADDHDU = 40
 545     OP_MADDLD = 41
 546     OP_MCRF = 42
 547     OP_MCRXR = 43
 548     OP_MCRXRX = 44
 549     OP_MFCR = 45
 550     OP_MFSPR = 46
 551     OP_MOD = 47
 552     OP_MTCRF = 48
 553     OP_MTSPR = 49
 554     OP_MUL_L64 = 50
 555     OP_MUL_H64 = 51
 556     OP_MUL_H32 = 52
 557     OP_OR = 53
 558     OP_POPCNT = 54
 559     OP_PRTY = 55
 560     OP_RLC = 56
 561     OP_RLCL = 57
 562     OP_RLCR = 58
 563     OP_SETB = 59
 564     OP_SHL = 60
 565     OP_SHR = 61
 566     OP_SYNC = 62
 567     OP_TRAP = 63
 568     OP_XOR = 67
 569     OP_SIM_CONFIG = 68
 570     OP_CROP = 69
 571     OP_RFID = 70
 572     OP_MFMSR = 71
 573     OP_MTMSRD = 72
 574     OP_SC = 73
 575     OP_MTMSR = 74
 576     OP_TLBIE = 75
 577     OP_SETVL = 76
 578     OP_FPOP = 77  # temporary: replace with actual ops
 579     OP_FPOP_I = 78  # temporary: replace with actual ops
 580     OP_FP_MADD = 79
 581     OP_SVREMAP = 80
 582     OP_SVSHAPE = 81
 583     OP_SVSTEP = 82
 584     OP_ADDG6S = 83
 585     OP_CDTBCD = 84
 586     OP_CBCDTD = 85
 587     OP_TERNLOG = 86
 588     OP_FETCH_FAILED = 87
 589     OP_GREV = 88
 590     OP_MINMAX = 89
 591     OP_AVGADD = 90
 592     OP_ABSDIFF = 91
 593     OP_ABSADD = 92
 594     OP_CPROP = 93
 595     OP_BMASK = 94
 596     OP_SVINDEX = 95
 597     OP_FMVIS = 96
 598     OP_FISHMV = 97
 599
 600
 601 @unique
 602 class In1Sel(Enum):
 603     NONE = 0
 604     RA = 1
 605     RA_OR_ZERO = 2
 606     SPR = 3
 607     RS = 4  # for some ALU/Logical operations
 608     FRA = 5
 609     FRS = 6
 610
 611
 612 @unique
 613 class In2Sel(Enum):
 614     NONE = 0
 615     RB = 1
 616     CONST_UI = 2
 617     CONST_SI = 3
 618     CONST_UI_HI = 4
 619     CONST_SI_HI = 5
 620     CONST_LI = 6
 621     CONST_BD = 7
 622     CONST_DS = 8
 623     CONST_M1 = 9
 624     CONST_SH = 10
 625     CONST_SH32 = 11
 626     SPR = 12
 627     RS = 13  # for shiftrot (M-Form)
 628     FRB = 14
 629     CONST_SVD = 15  # for SVD-Form
 630     CONST_SVDS = 16  # for SVDS-Form
 631     CONST_XBI = 17
 632
 633
 634 @unique
 635 class In3Sel(Enum):
 636     NONE = 0
 637     RS = 1
 638     RB = 2  # for shiftrot (M-Form)
 639     FRS = 3
 640     FRC = 4
 641     RC = 5  # for SVP64 bit-reverse LD/ST
 642     RT = 6  # for ternlog[i]
 643
 644
 645 @unique
 646 class OutSel(Enum):
 647     NONE = 0
 648     RT = 1
 649     RA = 2
 650     SPR = 3
 651     RT_OR_ZERO = 4
 652     FRT = 5
 653     FRS = 6
 654
 655
 656 @unique
 657 class LDSTLen(Enum):
 658     NONE = 0
 659     is1B = 1
 660     is2B = 2
 661     is4B = 4
 662     is8B = 8
 663
 664 # Backward compatibility
 665 LdstLen = LDSTLen
 666
 667
 668 @unique
 669 class LDSTMode(Enum):
 670     NONE = 0
 671     update = 1
 672     cix = 2
 673     cx = 3
 674
 675
 676 @unique
 677 class RCOE(Enum):
 678     NONE = 0
 679     ONE = 1
 680     RC = 2    # includes OE
 681     RC_ONLY = 3  # does not include OE
 682
 683
 684 @unique
 685 class CryIn(Enum):
 686     ZERO = 0
 687     ONE = 1
 688     CA = 2
 689     # TODO OV = 3
 690
 691
 692 @unique
 693 class CRInSel(Enum):
 694     NONE = 0
 695     CR0 = 1
 696     BI = 2
 697     BFA = 3
 698     BA_BB = 4
 699     BC = 5
 700     WHOLE_REG = 6
 701     CR1 = 7
 702
 703
 704 @unique
 705 class CROutSel(Enum):
 706     NONE = 0
 707     CR0 = 1
 708     BF = 2
 709     BT = 3
 710     WHOLE_REG = 4
 711     CR1 = 5
 712
 713
 714 # SPRs - Special-Purpose Registers.  See V3.0B Figure 18 p971 and
 715 # http://libre-riscv.org/openpower/isatables/sprs.csv
 716 # http://bugs.libre-riscv.org/show_bug.cgi?id=261
 717 # http://bugs.libre-riscv.org/show_bug.cgi?id=859 - KAIVB
 718
 719 def get_spr_enum(full_file):
 720     """get_spr_enum - creates an Enum of SPRs, dynamically
 721     has the option to reduce the enum to a much shorter list.
 722     this saves drastically on the size of the regfile
 723     """
 724     short_list = {'PIDR', 'DAR', 'PRTBL', 'DSISR', 'SVSRR0', 'SVSTATE',
 725                   'SVSTATE0', 'SVSTATE1', 'SVSTATE2', 'SVSTATE3',
 726                   'SPRG0_priv', 'SPRG1_priv', 'SPRG2_priv', 'SPRG3_priv',
 727                   'SPRG0', 'SPRG1', 'SPRG2', 'SPRG3', 'KAIVB',
 728                   # hmmm should not be including these, they are FAST regs
 729                   'CTR', 'LR', 'TAR', 'SRR0', 'SRR1', 'XER', 'DEC', 'TB', 'TBU',
 730                   'HSRR0', 'HSRR1', 'HSPRG0', 'HSPRG1',
 731                   }
 732     spr_csv = []
 733     for row in get_csv("sprs.csv"):
 734         if full_file or row['SPR'] in short_list:
 735             spr_csv.append(row)
 736
 737     spr_info = namedtuple('spr_info', 'SPR priv_mtspr priv_mfspr length idx')
 738     spr_dict = {}
 739     spr_byname = {}
 740     for row in spr_csv:
 741         info = spr_info(SPR=row['SPR'], priv_mtspr=row['priv_mtspr'],
 742                         priv_mfspr=row['priv_mfspr'], length=int(row['len']),
 743                         idx=int(row['Idx']))
 744         spr_dict[int(row['Idx'])] = info
 745         spr_byname[row['SPR']] = info
 746     fields = [(row['SPR'], int(row['Idx'])) for row in spr_csv]
 747     SPR = Enum('SPR', fields)
 748     return SPR, spr_dict, spr_byname
 749
 750
 751 SPRfull, spr_dict, spr_byname = get_spr_enum(full_file=True)
 752 SPRreduced, _, _ = get_spr_enum(full_file=False)
 753
 754 XER_bits = {
 755     'SO': 32,
 756     'OV': 33,
 757     'CA': 34,
 758     'OV32': 44,
 759     'CA32': 45
 760 }
 761
 762 MSRSpec = namedtuple("MSRSpec", ["dr", "pr", "sf"])
 763
 764 if __name__ == '__main__':
 765     # find out what the heck is in SPR enum :)
 766     print("sprs full", len(SPRfull))
 767     print(dir(SPRfull))
 768     print("sprs reduced", len(SPRreduced))
 769     print(dir(SPRreduced))
 770     print(dir(Enum))
 771     print(SPRfull.__members__['TAR'])
 772     for x in SPRfull:
 773         print("full", x, x.value, str(x), x.name)
 774     for x in SPRreduced:
 775         print("reduced", x, x.value, str(x), x.name)
 776
 777     print("function", Function.ALU.name)