1 # SPDX-License-Identifier: LGPL-3-or-later
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2020, Michael Nolan
5 """Enums used in OpenPOWER ISA decoding
7 Note: for SV, from v3.1B p12:
9 The designated SPR sandbox consists of non-privileged SPRs 704-719 and
10 privileged SPRs 720-735.
12 Note: the option exists to select a much shorter list of SPRs, to reduce
13 regfile size in HDL. this is SPRreduced and the supported list is in
17 from enum
import Enum
, unique
20 from os
.path
import dirname
, join
21 from collections
import namedtuple
25 filedir
= os
.path
.dirname(os
.path
.abspath(__file__
))
26 basedir
= dirname(dirname(dirname(filedir
)))
27 tabledir
= join(basedir
, 'openpower')
28 isatables
= join(tabledir
, 'isatables')
29 #print ("find_wiki_dir", isatables)
33 def find_wiki_file(name
):
34 return join(find_wiki_dir(), name
)
38 file_path
= find_wiki_file(name
)
39 with
open(file_path
, 'r') as csvfile
:
40 reader
= csv
.DictReader(csvfile
)
44 # names of the fields in the tables that don't correspond to an enum
45 single_bit_flags
= ['inv A', 'inv out',
46 'cry out', 'BR', 'sgn ext', 'rsrv', '32b',
47 'sgn', 'lk', 'sgl pipe']
49 # default values for fields in the table
50 default_values
= {'unit': "NONE", 'internal op': "OP_ILLEGAL",
51 'in1': "RA", 'in2': 'NONE', 'in3': 'NONE', 'out': 'NONE',
55 'rc': 'NONE', 'cry in': 'ZERO', 'form': 'NONE'}
58 def get_signal_name(name
):
61 return name
.lower().replace(' ', '_')
63 # this corresponds to which Function Unit (pipeline-with-Reservation-Stations)
64 # is to process and guard the operation. they are roughly divided by having
65 # the same register input/output signature (X-Form, etc.)
82 SV
= 1 << 12 # Simple-V https://libre-soc.org/openpower/sv
118 SVL
= 29 # Simple-V for setvl instruction
119 SVD
= 30 # Simple-V for LD/ST bit-reverse, variant of D-Form
120 SVDS
= 31 # Simple-V for LD/ST bit-reverse, variant of DS-Form
121 SVM
= 32 # Simple-V SHAPE mode - TEMPORARY TEMPORARY TEMPORARY
122 SVRM
= 33 # Simple-V REMAP mode - TEMPORARY TEMPORARY TEMPORARY
126 # Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/
150 Idx_1_2
= 5 # due to weird BA/BB for crops
154 class SVP64PredMode(Enum
):
161 class SVP64PredInt(Enum
):
173 class SVP64PredCR(Enum
):
185 class SVP64RMMode(Enum
):
195 class SVP64BCPredMode(Enum
):
202 class SVP64BCVLSETMode(Enum
):
208 # note that these are chosen to be exactly the same as
209 # SVP64 RM bit 4. ALL=1 => bit4=1
211 class SVP64BCGate(Enum
):
216 class SVP64BCCTRMode(Enum
):
223 class SVP64width(Enum
):
231 class SVP64subvl(Enum
):
239 class SVP64sat(Enum
):
246 class SVP64LDSTmode(Enum
):
254 # supported instructions: make sure to keep up-to-date with CSV files
255 # just like everything else
257 "NONE", "add", "addc", "addco", "adde", "addeo",
258 "addi", "addic", "addic.", "addis",
259 "addme", "addmeo", "addo", "addze", "addzeo",
261 "and", "andc", "andi.", "andis.",
263 "absdu", # AV bitmanip
264 "avgadd", # AV bitmanip
265 "b", "bc", "bcctr", "bclr", "bctar",
269 "cmp", "cmpb", "cmpeqb", "cmpi", "cmpl", "cmpli", "cmprb",
270 "cntlzd", "cntlzw", "cnttzd", "cnttzw",
271 "crand", "crandc", "creqv",
272 "crnand", "crnor", "cror", "crorc", "crxor",
274 "dcbf", "dcbst", "dcbt", "dcbtst", "dcbz",
275 "divd", "divde", "divdeo", "divdeu",
276 "divdeuo", "divdo", "divdu", "divduo", "divw", "divwe", "divweo",
277 "divweu", "divweuo", "divwo", "divwu", "divwuo",
279 "extsb", "extsh", "extsw", "extswsli",
280 "fadd", "fadds", "fsub", "fsubs", # FP add / sub
281 "fcfids", "fcfidus", "fsqrts", "fres", "frsqrtes", # FP stuff
282 "fdmadds", # DCT FP 3-arg
283 "fmsubs", "fmadds", "fnmsubs", "fnmadds", # FP 3-arg
284 "ffadds", "ffsubs", "ffmuls", "ffdivs", # FFT FP 2-arg
285 "ffmsubs", "ffmadds", "ffnmsubs", "ffnmadds", # FFT FP 3-arg
286 "fmul", "fmuls", "fdiv", "fdivs", # FP mul / div
287 "fmr", "fabs", "fnabs", "fneg", "fcpsgn", # FP move/abs/neg
288 "fsins", "fcoss", # FP SIN/COS
289 'grev', 'grev.', 'grevi', 'grevi.',
290 'grevw', 'grevw.', 'grevwi', 'grevwi.',
291 "hrfid", "icbi", "icbt", "isel", "isync",
292 "lbarx", "lbz", "lbzcix", "lbzu", "lbzux", "lbzx", # load byte
293 "ld", "ldarx", "ldbrx", "ldu", "ldux", "ldx", # load double
294 # "lbzbr", "lbzubr", # load byte SVP64 bit-reversed
295 # "ldbr", "ldubr", # load double SVP64 bit-reversed
296 "lfs", "lfsx", "lfsu", "lfsux", # FP load single
297 "lfd", "lfdx", "lfdu", "lfdux", "lfiwzx", "lfiwax", # FP load double
298 "lha", "lharx", "lhau", "lhaux", "lhax", # load half
299 "lhbrx", "lhz", "lhzu", "lhzux", "lhzx", # more load half
300 # "lhabr", "lhaubr", # load half SVP64 bit-reversed
301 # "lhzbr", "lhzubr", # more load half SVP64 bit-reversed
302 "lwa", "lwarx", "lwaux", "lwax", "lwbrx", # load word
303 "lwz", "lwzcix", "lwzu", "lwzux", "lwzx", # more load word
304 # "lwabr", # load word SVP64 bit-reversed
305 # "lwzbr", "lwzubr", # more load word SVP64 bit-reversed
306 "maddhd", "maddhdu", "maddld", # INT multiply-and-add
307 "mcrf", "mcrxr", "mcrxrx", "mfcr/mfocrf", # CR mvs
309 "mins", "maxs", "minu", "maxu", # AV bitmanip
310 "modsd", "modsw", "modud", "moduw",
311 "mtcrf/mtocrf", "mtmsr", "mtmsrd", "mtspr",
312 "mulhd", "mulhdu", "mulhw", "mulhwu", "mulld", "mulldo",
313 "mulli", "mullw", "mullwo",
314 "nand", "neg", "nego",
316 "nor", "or", "orc", "ori", "oris",
317 "popcntb", "popcntd", "popcntw",
320 "rldcl", "rldcr", "rldic", "rldicl", "rldicr", "rldimi",
321 "rlwimi", "rlwinm", "rlwnm",
323 "setvl", # https://libre-soc.org/openpower/sv/setvl
324 "svremap", # https://libre-soc.org/openpower/sv/remap - TEMPORARY
325 "svshape", # https://libre-soc.org/openpower/sv/remap
326 "svstep", # https://libre-soc.org/openpower/sv/setvl
328 "slbia", "sld", "slw", "srad", "sradi",
329 "sraw", "srawi", "srd", "srw",
330 "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
331 "std", "stdbrx", "stdcx", "stdu", "stdux", "stdx",
332 "stfs", "stfsx", "stfsu", "stfux", "stfsux", # FP store single
333 "stfd", "stfdx", "stfdu", "stfdux", "stfiwx", # FP store double
334 "sth", "sthbrx", "sthcx", "sthu", "sthux", "sthx",
335 "stw", "stwbrx", "stwcx", "stwu", "stwux", "stwx",
336 "subf", "subfc", "subfco", "subfe", "subfeo", "subfic",
337 "subfme", "subfmeo", "subfo", "subfze", "subfzeo",
341 "tlbie", "tlbiel", "tlbsync",
344 "xor", "xori", "xoris",
347 # two-way lookup of instruction-to-index and vice-versa
350 for i
, insn
in enumerate(_insns
):
354 # must be long enough to cover all instructions
355 asmlen
= len(_insns
).bit_length()
357 # Internal Operation numbering. Add new opcodes here (FPADD, FPMUL etc.)
362 OP_ILLEGAL
= 0 # important that this is zero (see power_decoder.py)
436 OP_FPOP
= 77 # temporary: replace with actual ops
437 OP_FPOP_I
= 78 # temporary: replace with actual ops
459 RS
= 4 # for some ALU/Logical operations
479 RS
= 13 # for shiftrot (M-Form)
481 CONST_SVD
= 15 # for SVD-Form
482 CONST_SVDS
= 16 # for SVDS-Form
490 RB
= 2 # for shiftrot (M-Form)
493 RC
= 5 # for SVP64 bit-reverse LD/ST
494 RT
= 6 # for ternlog[i]
518 class LDSTMode(Enum
):
553 class CROutSel(Enum
):
562 # SPRs - Special-Purpose Registers. See V3.0B Figure 18 p971 and
563 # http://libre-riscv.org/openpower/isatables/sprs.csv
564 # http://bugs.libre-riscv.org/show_bug.cgi?id=261
565 # http://bugs.libre-riscv.org/show_bug.cgi?id=859 - KAIVB
567 def get_spr_enum(full_file
):
568 """get_spr_enum - creates an Enum of SPRs, dynamically
569 has the option to reduce the enum to a much shorter list.
570 this saves drastically on the size of the regfile
572 short_list
= {'PIDR', 'DAR', 'PRTBL', 'DSISR', 'SVSRR0', 'SVSTATE',
573 'SVSTATE0', 'SVSTATE1', 'SVSTATE2', 'SVSTATE3',
574 'SPRG0_priv', 'SPRG1_priv', 'SPRG2_priv', 'SPRG3_priv',
575 'SPRG0', 'SPRG1', 'SPRG2', 'SPRG3', 'KAIVB',
576 # hmmm should not be including these, they are FAST regs
577 'CTR', 'LR', 'TAR', 'SRR0', 'SRR1', 'XER', 'DEC', 'TB', 'TBU',
578 'HSRR0', 'HSRR1', 'HSPRG0', 'HSPRG1',
581 for row
in get_csv("sprs.csv"):
582 if full_file
or row
['SPR'] in short_list
:
585 spr_info
= namedtuple('spr_info', 'SPR priv_mtspr priv_mfspr length idx')
589 info
= spr_info(SPR
=row
['SPR'], priv_mtspr
=row
['priv_mtspr'],
590 priv_mfspr
=row
['priv_mfspr'], length
=int(row
['len']),
592 spr_dict
[int(row
['Idx'])] = info
593 spr_byname
[row
['SPR']] = info
594 fields
= [(row
['SPR'], int(row
['Idx'])) for row
in spr_csv
]
595 SPR
= Enum('SPR', fields
)
596 return SPR
, spr_dict
, spr_byname
599 SPRfull
, spr_dict
, spr_byname
= get_spr_enum(full_file
=True)
600 SPRreduced
, _
, _
= get_spr_enum(full_file
=False)
610 MSRSpec
= namedtuple("MSRSpec", ["dr", "pr", "sf"])
612 if __name__
== '__main__':
613 # find out what the heck is in SPR enum :)
614 print("sprs full", len(SPRfull
))
616 print("sprs reduced", len(SPRreduced
))
617 print(dir(SPRreduced
))
619 print(SPRfull
.__members
__['TAR'])
621 print("full", x
, x
.value
, str(x
), x
.name
)
623 print("reduced", x
, x
.value
, str(x
), x
.name
)
625 print("function", Function
.ALU
.name
)