src/openpower/decoder/power_enums.py

   1 # SPDX-License-Identifier: LGPL-3-or-later
   2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3 # Copyright (C) 2020, Michael Nolan
   4
   5 """Enums used in OpenPOWER ISA decoding
   6
   7 Note: for SV, from v3.1B p12:
   8
   9     The designated SPR sandbox consists of non-privileged SPRs 704-719 and
  10     privileged SPRs 720-735.
  11
  12 Note: the option exists to select a much shorter list of SPRs, to reduce
  13 regfile size in HDL.  this is SPRreduced and the supported list is in
  14 get_spr_enum
  15 """
  16
  17 from enum import (
  18     auto,
  19     Enum as _Enum,
  20     unique,
  21 )
  22 import csv
  23 import os
  24 from os.path import dirname, join
  25 from collections import namedtuple
  26 import functools
  27
  28
  29 def find_wiki_dir():
  30     filedir = os.path.dirname(os.path.abspath(__file__))
  31     basedir = dirname(dirname(dirname(filedir)))
  32     tabledir = join(basedir, 'openpower')
  33     isatables = join(tabledir, 'isatables')
  34     #print ("find_wiki_dir", isatables)
  35     return isatables
  36
  37
  38 def find_wiki_file(name):
  39     return join(find_wiki_dir(), name)
  40
  41
  42 def get_csv(name):
  43     """gets a not-entirely-csv-file-formatted database, which allows comments
  44     """
  45     file_path = find_wiki_file(name)
  46     with open(file_path, 'r') as csvfile:
  47         csvfile = filter(lambda row: row[0] !='#', csvfile) # strip "#..."
  48         reader = csv.DictReader(csvfile)
  49         return list(reader)
  50
  51
  52 # names of the fields in the tables that don't correspond to an enum
  53 single_bit_flags = ['inv A', 'inv out',
  54                     'cry out', 'BR', 'sgn ext', 'rsrv', '32b',
  55                     'sgn', 'lk', 'sgl pipe']
  56
  57 # default values for fields in the table
  58 default_values = {'unit': "NONE", 'internal op': "OP_ILLEGAL",
  59                   'in1': "RA", 'in2': 'NONE', 'in3': 'NONE', 'out': 'NONE',
  60                   'CR in': 'NONE',
  61                   'ldst len': 'NONE',
  62                   'upd': '0',
  63                   'rc': 'NONE', 'cry in': 'ZERO', 'form': 'NONE'}
  64
  65
  66 def get_signal_name(name):
  67     if name[0].isdigit():
  68         name = "is_" + name
  69     return name.lower().replace(' ', '_')
  70
  71
  72 class Enum(_Enum):
  73     @classmethod
  74     def _missing_(cls, value):
  75         if isinstance(value, str):
  76             try:
  77                 if value == "":
  78                     value = 0
  79                 else:
  80                     value = int(value, 0)
  81             except ValueError:
  82                 pass
  83         keys = {item.name:item for item in cls}
  84         values = {item.value:item for item in cls}
  85         item = keys.get(value, values.get(value))
  86         if item is None:
  87             raise ValueError(value)
  88         return item
  89
  90
  91 # this corresponds to which Function Unit (pipeline-with-Reservation-Stations)
  92 # is to process and guard the operation.  they are roughly divided by having
  93 # the same register input/output signature (X-Form, etc.)
  94
  95
  96 @unique
  97 class Function(Enum):
  98     NONE = 0
  99     ALU = 1 << 1
 100     LDST = 1 << 2
 101     SHIFT_ROT = 1 << 3
 102     LOGICAL = 1 << 4
 103     BRANCH = 1 << 5
 104     CR = 1 << 6
 105     TRAP = 1 << 7
 106     MUL = 1 << 8
 107     DIV = 1 << 9
 108     SPR = 1 << 10
 109     MMU = 1 << 11
 110     SV = 1 << 12  # Simple-V https://libre-soc.org/openpower/sv
 111     VL = 1 << 13  # setvl
 112     FPU = 1 << 14  # FPU
 113
 114     @functools.lru_cache(maxsize=None)
 115     def __repr__(self):
 116         counter = 0
 117         value = int(self.value)
 118         if value != 0:
 119             while value != 0:
 120                 counter += 1
 121                 value >>= 1
 122             counter -= 1
 123             desc = f"(1 << {counter})"
 124         else:
 125             desc = "0"
 126         return f"<{self.__class__.__name__}.{self.name}: {desc}>"
 127
 128
 129 @unique
 130 class Form(Enum):
 131     NONE = 0
 132     I = 1
 133     B = 2
 134     SC = 3
 135     D = 4
 136     DS = 5
 137     DQ = 6
 138     DX = 7
 139     X = 8
 140     XL = 9
 141     XFX = 10
 142     XFL = 11
 143     XX1 = 12
 144     XX2 = 13
 145     XX3 = 14
 146     XX4 = 15
 147     XS = 16
 148     XO = 17
 149     A = 18
 150     M = 19
 151     MD = 20
 152     MDS = 21
 153     VA = 22
 154     VC = 23
 155     VX = 24
 156     EVX = 25
 157     EVS = 26
 158     Z22 = 27
 159     Z23 = 28
 160     SVL = 29  # Simple-V for setvl instruction
 161     SVD = 30  # Simple-V for LD/ST bit-reverse, variant of D-Form
 162     SVDS = 31  # Simple-V for LD/ST bit-reverse, variant of DS-Form
 163     SVM = 32  # Simple-V SHAPE mode
 164     SVM2 = 33  # Simple-V SHAPE2 mode - fits into SVM
 165     SVRM = 34  # Simple-V REMAP mode
 166     TLI = 35  # ternlogi
 167     XB = 36
 168     BM2 = 37 # bmask
 169     SVI = 38  # Simple-V Index Mode
 170     VA2 = 39
 171     SVC = 40
 172     SVR = 41
 173
 174 # Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/
 175
 176
 177 class SVMode(Enum):
 178     NONE = 0          # for non-SV instructions only
 179     NORMAL = auto()
 180     LDST_IDX = auto()
 181     LDST_IMM = auto()
 182     BRANCH = auto()
 183     CROP = auto()
 184
 185
 186 @unique
 187 class SVPtype(Enum):
 188     NONE = 0
 189     P1 = 1
 190     P2 = 2
 191
 192     @classmethod
 193     def _missing_(cls, value):
 194         return {"1P": SVPtype.P1, "2P": SVPtype.P2}[value]
 195
 196     def __repr__(self):
 197         return {
 198             SVPtype.NONE: "NONE",
 199             SVPtype.P1: "1P",
 200             SVPtype.P2: "2P",
 201         }[self]
 202
 203
 204 @unique
 205 class SVEtype(Enum):
 206     NONE = 0
 207     EXTRA2 = 1
 208     EXTRA3 = 2
 209
 210     def __repr__(self):
 211         return self.name
 212
 213
 214 @unique
 215 class SVmask_src(Enum):
 216     NO = 0
 217     EN = 1
 218
 219     def __repr__(self):
 220         return self.name
 221
 222
 223 @unique
 224 class SVExtra(Enum):
 225     NONE = 0
 226     Idx0 = 1
 227     Idx1 = 2
 228     Idx2 = 3
 229     Idx3 = 4
 230     Idx_1_2 = 5  # due to weird BA/BB for crops
 231
 232     def __repr__(self):
 233         return {
 234             SVExtra.NONE: "NONE",
 235             SVExtra.Idx0: "[0]",
 236             SVExtra.Idx1: "[1]",
 237             SVExtra.Idx2: "[2]",
 238             SVExtra.Idx3: "[3]",
 239             SVExtra.Idx_1_2: "[1:2]",
 240         }[self]
 241
 242 # Backward compatibility
 243 SVEXTRA = SVExtra
 244
 245
 246 class SVExtraRegType(Enum):
 247     NONE = None
 248     SRC = 's'
 249     DST = 'd'
 250
 251
 252 class SVExtraReg(Enum):
 253     NONE = auto()
 254     RA = auto()
 255     RA_OR_ZERO = RA
 256     RB = auto()
 257     RC = auto()
 258     RS = auto()
 259     RT = auto()
 260     RT_OR_ZERO = RT
 261     FRA = auto()
 262     FRB = auto()
 263     FRC = auto()
 264     FRS = auto()
 265     FRT = auto()
 266     CR = auto()
 267     CR0 = auto()
 268     CR1 = auto()
 269     BF = auto()
 270     BFA = auto()
 271     BA = auto()
 272     BB = auto()
 273     BC = auto()
 274     BI = auto()
 275     BT = auto()
 276     BFT = auto()
 277     WHOLE_REG = auto()
 278     SPR = auto()
 279
 280     @classmethod
 281     def _missing_(cls, value):
 282         selectors = (
 283             In1Sel, In2Sel, In3Sel, CRInSel, CRIn2Sel,
 284             OutSel, CROutSel,
 285         )
 286         if isinstance(value, selectors):
 287             return cls.__members__[value.name]
 288         return super()._missing_(value)
 289
 290
 291 @unique
 292 class SVP64PredMode(Enum):
 293     ALWAYS = 0
 294     INT = 1
 295     CR = 2
 296
 297
 298 @unique
 299 class SVP64PredInt(Enum):
 300     ALWAYS = 0
 301     R3_UNARY = 1
 302     R3 = 2
 303     R3_N = 3
 304     R10 = 4
 305     R10_N = 5
 306     R30 = 6
 307     R30_N = 7
 308
 309
 310 @unique
 311 class SVP64PredCR(Enum):
 312     LT = 0
 313     GE = 1
 314     GT = 2
 315     LE = 3
 316     EQ = 4
 317     NE = 5
 318     SO = 6
 319     NS = 7
 320
 321
 322 @unique
 323 class SVP64RMMode(Enum):
 324     NORMAL = 0
 325     MAPREDUCE = 1
 326     FFIRST = 2
 327     SATURATE = 3
 328     PREDRES = 4
 329     BRANCH = 5
 330
 331
 332 @unique
 333 class SVP64BCPredMode(Enum):
 334     NONE = 0
 335     MASKZERO = 1
 336     MASKONE = 2
 337
 338
 339 @unique
 340 class SVP64BCVLSETMode(Enum):
 341     NONE = 0
 342     VL_INCL = 1
 343     VL_EXCL = 2
 344
 345
 346 # note that these are chosen to be exactly the same as
 347 # SVP64 RM bit 4.  ALL=1 => bit4=1
 348 @unique
 349 class SVP64BCGate(Enum):
 350     ANY = 0
 351     ALL = 1
 352
 353
 354 class SVP64BCCTRMode(Enum):
 355     NONE = 0
 356     TEST = 1
 357     TEST_INV = 2
 358
 359
 360 @unique
 361 class SVP64width(Enum):
 362     DEFAULT = 0
 363     EW_32 = 1
 364     EW_16 = 2
 365     EW_8 = 3
 366
 367
 368 @unique
 369 class SVP64subvl(Enum):
 370     VEC1 = 0
 371     VEC2 = 1
 372     VEC3 = 2
 373     VEC4 = 3
 374
 375
 376 @unique
 377 class SVP64sat(Enum):
 378     NONE = 0
 379     SIGNED = 1
 380     UNSIGNED = 2
 381
 382
 383 @unique
 384 class SVP64LDSTmode(Enum):
 385     NONE = 0
 386     INDEXED = 1
 387     ELSTRIDE = 2
 388     UNITSTRIDE = 3
 389
 390
 391 class RegType(Enum):
 392     GPR = 0
 393     RA = GPR
 394     RB = GPR
 395     RC = GPR
 396     RS = GPR
 397     RT = GPR
 398
 399     FPR = 1
 400     FRA = FPR
 401     FRB = FPR
 402     FRC = FPR
 403     FRS = FPR
 404     FRT = FPR
 405
 406     CR_REG = 2  # actually CR Field. the CR register is 32-bit.
 407     BF = CR_REG
 408     BFA = CR_REG
 409
 410     CR_BIT = 3 # refers to one bit of the 32-bit CR register
 411     BA = CR_BIT
 412     BB = CR_BIT
 413     BC = CR_BIT
 414     BI = CR_BIT
 415     BT = CR_BIT
 416
 417     XER_BIT = 4   # XER bits, includes OV, OV32, SO, CA, CA32
 418     OV = XER_BIT
 419     OV32 = XER_BIT
 420     CA = XER_BIT
 421     CA32 = XER_BIT
 422     SO = XER_BIT
 423
 424     @classmethod
 425     def _missing_(cls, value):
 426         if isinstance(value, SVExtraReg):
 427             return cls.__members__[value.name]
 428         return super()._missing_(value)
 429
 430
 431 FPTRANS_INSNS = (
 432     "fatan2", "fatan2s",
 433     "fatan2pi", "fatan2pis",
 434     "fpow", "fpows",
 435     "fpown", "fpowns",
 436     "fpowr", "fpowrs",
 437     "frootn", "frootns",
 438     "fhypot", "fhypots",
 439     "frsqrt", "frsqrts",
 440     "fcbrt", "fcbrts",
 441     "frecip", "frecips",
 442     "fexp2m1", "fexp2m1s",
 443     "flog2p1", "flog2p1s",
 444     "fexp2", "fexp2s",
 445     "flog2", "flog2s",
 446     "fexpm1", "fexpm1s",
 447     "flogp1", "flogp1s",
 448     "fexp", "fexps",
 449     "flog", "flogs",
 450     "fexp10m1", "fexp10m1s",
 451     "flog10p1", "flog10p1s",
 452     "fexp10", "fexp10s",
 453     "flog10", "flog10s",
 454     "fsin", "fsins",
 455     "fcos", "fcoss",
 456     "ftan", "ftans",
 457     "fasin", "fasins",
 458     "facos", "facoss",
 459     "fatan", "fatans",
 460     "fsinpi", "fsinpis",
 461     "fcospi", "fcospis",
 462     "ftanpi", "ftanpis",
 463     "fasinpi", "fasinpis",
 464     "facospi", "facospis",
 465     "fatanpi", "fatanpis",
 466     "fsinh", "fsinhs",
 467     "fcosh", "fcoshs",
 468     "ftanh", "ftanhs",
 469     "fasinh", "fasinhs",
 470     "facosh", "facoshs",
 471     "fatanh", "fatanhs",
 472     "fminnum08", "fminnum08s",
 473     "fmaxnum08", "fmaxnum08s",
 474     "fmin19", "fmin19s",
 475     "fmax19", "fmax19s",
 476     "fminnum19", "fminnum19s",
 477     "fmaxnum19", "fmaxnum19s",
 478     "fminc", "fmincs",
 479     "fmaxc", "fmaxcs",
 480     "fminmagnum08", "fminmagnum08s",
 481     "fmaxmagnum08", "fmaxmagnum08s",
 482     "fminmag19", "fminmag19s",
 483     "fmaxmag19", "fmaxmag19s",
 484     "fminmagnum19", "fminmagnum19s",
 485     "fmaxmagnum19", "fmaxmagnum19s",
 486     "fminmagc", "fminmagcs",
 487     "fmaxmagc", "fmaxmagcs",
 488     "fmod", "fmods",
 489     "fremainder", "fremainders",
 490 )
 491
 492
 493 # supported instructions: make sure to keep up-to-date with CSV files
 494 # just like everything else
 495 _insns = [
 496     "NONE", "add", "addc", "addco", "adde", "addeo",
 497     "addi", "addic", "addic.", "addis",
 498     "addme", "addmeo", "addo", "addze", "addzeo",
 499     "addg6s",
 500     "and", "andc", "andi.", "andis.",
 501     "attn",
 502     "absdu", "absds",                         # AV bitmanip
 503     "absdacs", "absdacu",                     # AV bitmanip
 504     "avgadd",                                 # AV bitmanip
 505     "b", "bc", "bcctr", "bclr", "bctar",
 506     "bmask",                                  # AV bitmanip
 507     "bpermd",
 508     "cbcdtd",
 509     "cdtbcd",
 510     "cmp", "cmpb", "cmpeqb", "cmpi", "cmpl", "cmpli", "cmprb",
 511     "cntlzd", "cntlzw", "cnttzd", "cnttzw",
 512     "cprop", # AV bitmanip
 513     "crand", "crandc", "creqv",
 514     "crnand", "crnor", "cror", "crorc", "crxor",
 515     "darn",
 516     "dcbf", "dcbst", "dcbt", "dcbtst", "dcbz",
 517     "divd", "divde", "divdeo", "divdeu",
 518     "divdeuo", "divdo", "divdu", "divduo",
 519     "divmod2du",
 520     "divw", "divwe", "divweo",
 521     "divweu", "divweuo", "divwo", "divwu", "divwuo",
 522     "dsld", "dsrd",
 523     "eieio", "eqv",
 524     "extsb", "extsh", "extsw", "extswsli",
 525     "fadd", "fadds", "fsub", "fsubs",                   # FP add / sub
 526     "fcfids", "fcfidus", "fsqrts", "fres", "frsqrtes",  # FP stuff
 527     "fdmadds",                                          # DCT FP 3-arg
 528     "fmsubs", "fmadds", "fnmsubs", "fnmadds",           # FP 3-arg
 529     "ffadds", "ffsubs", "ffmuls", "ffdivs",             # FFT FP 2-arg
 530     "ffmsubs", "ffmadds", "ffnmsubs", "ffnmadds",       # FFT FP 3-arg
 531     "fmul", "fmuls", "fdiv", "fdivs",                   # FP mul / div
 532     "fmr", "fabs", "fnabs", "fneg", "fcpsgn",           # FP move/abs/neg
 533     "fmvis",                                            # FP load immediate
 534     "fishmv",                                           # Float Replace Lower-Half Single, Immediate
 535     'grev', 'grev.', 'grevi', 'grevi.',
 536     'grevw', 'grevw.', 'grevwi', 'grevwi.',
 537     "hrfid", "icbi", "icbt", "isel", "isync",
 538     "lbarx", "lbz", "lbzcix", "lbzu", "lbzux", "lbzx",  # load byte
 539     "ld", "ldarx", "ldbrx", "ldu", "ldux", "ldx",       # load double
 540     # "lbzbr", "lbzubr",  # load byte SVP64 bit-reversed
 541     # "ldbr", "ldubr",    # load double SVP64 bit-reversed
 542     "lfs", "lfsx", "lfsu", "lfsux",                     # FP load single
 543     "lfd", "lfdx", "lfdu", "lfdux", "lfiwzx", "lfiwax",  # FP load double
 544     "lha", "lharx", "lhau", "lhaux", "lhax",            # load half
 545     "lhbrx", "lhz", "lhzu", "lhzux", "lhzx",            # more load half
 546     # "lhabr", "lhaubr",  # load half SVP64 bit-reversed
 547     # "lhzbr", "lhzubr",  # more load half SVP64 bit-reversed
 548     "lwa", "lwarx", "lwaux", "lwax", "lwbrx",           # load word
 549     "lwz", "lwzcix", "lwzu", "lwzux", "lwzx",           # more load word
 550     # "lwabr",           # load word SVP64 bit-reversed
 551     # "lwzbr", "lwzubr", # more load word SVP64 bit-reversed
 552     "maddedu",
 553     "maddhd", "maddhdu", "maddld",                      # INT multiply-and-add
 554     "mcrf", "mcrxr", "mcrxrx", "mfcr/mfocrf",           # CR mvs
 555     "mfmsr", "mfspr",
 556     "mins", "maxs", "minu", "maxu",                     # AV bitmanip
 557     "modsd", "modsw", "modud", "moduw",
 558     "mtcrf/mtocrf", "mtmsr", "mtmsrd", "mtspr",
 559     "mulhd", "mulhdu", "mulhw", "mulhwu", "mulld", "mulldo",
 560     "mulli", "mullw", "mullwo",
 561     "nand", "neg", "nego",
 562     "nop",
 563     "nor", "or", "orc", "ori", "oris",
 564     "pcdec",
 565     "popcntb", "popcntd", "popcntw",
 566     "prtyd", "prtyw",
 567     "rfid",
 568     "rldcl", "rldcr", "rldic", "rldicl", "rldicr", "rldimi",
 569     "rlwimi", "rlwinm",    "rlwnm",
 570     "setb",
 571     "setvl",  # https://libre-soc.org/openpower/sv/setvl
 572     "svindex",  # https://libre-soc.org/openpower/sv/remap
 573     "svremap",  # https://libre-soc.org/openpower/sv/remap - TEMPORARY
 574     "svshape",  # https://libre-soc.org/openpower/sv/remap/#svshape
 575     "svshape2",  # https://libre-soc.org/openpower/sv/remap/discussion TODO
 576     "svstep",  # https://libre-soc.org/openpower/sv/setvl
 577     "sim_cfg",
 578     "slbia", "sld", "slw", "srad", "sradi",
 579     "sraw", "srawi", "srd", "srw",
 580     "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
 581     "std", "stdbrx", "stdcx", "stdu", "stdux", "stdx",
 582     "stfs", "stfsx", "stfsu", "stfux", "stfsux",        # FP store single
 583     "stfd", "stfdx", "stfdu", "stfdux", "stfiwx",       # FP store double
 584     "sth", "sthbrx", "sthcx", "sthu", "sthux", "sthx",
 585     "stw", "stwbrx", "stwcx", "stwu", "stwux", "stwx",
 586     "subf", "subfc", "subfco", "subfe", "subfeo", "subfic",
 587     "subfme", "subfmeo", "subfo", "subfze", "subfzeo",
 588     "sync",
 589     "ternlogi",
 590     "td", "tdi",
 591     "tlbie", "tlbiel", "tlbsync",
 592     "tw", "twi",
 593     "wait",
 594     "xor", "xori", "xoris",
 595     *FPTRANS_INSNS,
 596 ]
 597
 598 # two-way lookup of instruction-to-index and vice-versa
 599 insns = {}
 600 asmidx = {}
 601 for i, insn in enumerate(_insns):
 602     insns[i] = insn
 603     asmidx[insn] = i
 604
 605 # must be long enough to cover all instructions
 606 asmlen = len(_insns).bit_length()
 607
 608 # Internal Operation numbering.  Add new opcodes here (FPADD, FPMUL etc.)
 609
 610
 611 @unique
 612 class MicrOp(Enum):
 613     OP_ILLEGAL = 0     # important that this is zero (see power_decoder.py)
 614     OP_NOP = 1
 615     OP_ADD = 2
 616     OP_ADDPCIS = 3
 617     OP_AND = 4
 618     OP_ATTN = 5
 619     OP_B = 6
 620     OP_BC = 7
 621     OP_BCREG = 8
 622     OP_BPERM = 9
 623     OP_CMP = 10
 624     OP_CMPB = 11
 625     OP_CMPEQB = 12
 626     OP_CMPRB = 13
 627     OP_CNTZ = 14
 628     OP_CRAND = 15
 629     OP_CRANDC = 16
 630     OP_CREQV = 17
 631     OP_CRNAND = 18
 632     OP_CRNOR = 19
 633     OP_CROR = 20
 634     OP_CRORC = 21
 635     OP_CRXOR = 22
 636     OP_DARN = 23
 637     OP_DCBF = 24
 638     OP_DCBST = 25
 639     OP_DCBT = 26
 640     OP_DCBTST = 27
 641     OP_DCBZ = 28
 642     OP_DIV = 29
 643     OP_DIVE = 30
 644     OP_EXTS = 31
 645     OP_EXTSWSLI = 32
 646     OP_ICBI = 33
 647     OP_ICBT = 34
 648     OP_ISEL = 35
 649     OP_ISYNC = 36
 650     OP_LOAD = 37
 651     OP_STORE = 38
 652     OP_MADDHD = 39
 653     OP_MADDHDU = 40
 654     OP_MADDLD = 41
 655     OP_MCRF = 42
 656     OP_MCRXR = 43
 657     OP_MCRXRX = 44
 658     OP_MFCR = 45
 659     OP_MFSPR = 46
 660     OP_MOD = 47
 661     OP_MTCRF = 48
 662     OP_MTSPR = 49
 663     OP_MUL_L64 = 50
 664     OP_MUL_H64 = 51
 665     OP_MUL_H32 = 52
 666     OP_OR = 53
 667     OP_POPCNT = 54
 668     OP_PRTY = 55
 669     OP_RLC = 56
 670     OP_RLCL = 57
 671     OP_RLCR = 58
 672     OP_SETB = 59
 673     OP_SHL = 60
 674     OP_SHR = 61
 675     OP_SYNC = 62
 676     OP_TRAP = 63
 677     OP_XOR = 67
 678     OP_SIM_CONFIG = 68
 679     OP_CROP = 69
 680     OP_RFID = 70
 681     OP_MFMSR = 71
 682     OP_MTMSRD = 72
 683     OP_SC = 73
 684     OP_MTMSR = 74
 685     OP_TLBIE = 75
 686     OP_SETVL = 76
 687     OP_FPOP = 77  # temporary: replace with actual ops
 688     OP_FPOP_I = 78  # temporary: replace with actual ops
 689     OP_FP_MADD = 79
 690     OP_SVREMAP = 80
 691     OP_SVSHAPE = 81
 692     OP_SVSTEP = 82
 693     OP_ADDG6S = 83
 694     OP_CDTBCD = 84
 695     OP_CBCDTD = 85
 696     OP_TERNLOG = 86
 697     OP_FETCH_FAILED = 87
 698     OP_GREV = 88
 699     OP_MINMAX = 89
 700     OP_AVGADD = 90
 701     OP_ABSDIFF = 91
 702     OP_ABSADD = 92
 703     OP_CPROP = 93
 704     OP_BMASK = 94
 705     OP_SVINDEX = 95
 706     OP_FMVIS = 96
 707     OP_FISHMV = 97
 708     OP_PCDEC = 98
 709     OP_MADDEDU = 99
 710     OP_DIVMOD2DU = 100
 711     OP_DSHL = 101
 712     OP_DSHR = 102
 713
 714
 715 @unique
 716 class In1Sel(Enum):
 717     NONE = 0
 718     RA = 1
 719     RA_OR_ZERO = 2
 720     SPR = 3
 721     RS = 4  # for some ALU/Logical operations
 722     FRA = 5
 723     FRS = 6
 724     CIA = 7 # for addpcis
 725
 726
 727 @unique
 728 class In2Sel(Enum):
 729     NONE = 0
 730     RB = 1
 731     CONST_UI = 2
 732     CONST_SI = 3
 733     CONST_UI_HI = 4
 734     CONST_SI_HI = 5
 735     CONST_LI = 6
 736     CONST_BD = 7
 737     CONST_DS = 8
 738     CONST_M1 = 9
 739     CONST_SH = 10
 740     CONST_SH32 = 11
 741     SPR = 12
 742     RS = 13  # for shiftrot (M-Form)
 743     FRB = 14
 744     CONST_SVD = 15  # for SVD-Form
 745     CONST_SVDS = 16  # for SVDS-Form
 746     CONST_XBI = 17
 747     CONST_DXHI4 = 18 # for addpcis
 748     CONST_DQ = 19 # for ld/st-quad
 749
 750
 751 @unique
 752 class In3Sel(Enum):
 753     NONE = 0
 754     RS = 1
 755     RB = 2  # for shiftrot (M-Form)
 756     FRS = 3
 757     FRC = 4
 758     RC = 5  # for SVP64 bit-reverse LD/ST
 759     RT = 6  # for ternlog[i]
 760
 761
 762 @unique
 763 class OutSel(Enum):
 764     NONE = 0
 765     RT = 1
 766     RA = 2
 767     SPR = 3
 768     RT_OR_ZERO = 4
 769     FRT = 5
 770     FRS = 6
 771     RS = 7
 772
 773
 774 @unique
 775 class LDSTLen(Enum):
 776     NONE = 0
 777     is1B = 1
 778     is2B = 2
 779     is4B = 4
 780     is8B = 8
 781
 782 # Backward compatibility
 783 LdstLen = LDSTLen
 784
 785
 786 @unique
 787 class LDSTMode(Enum):
 788     NONE = 0
 789     update = 1
 790     cix = 2
 791     cx = 3
 792
 793
 794 @unique
 795 class RCOE(Enum):
 796     NONE = 0
 797     ONE = 1
 798     RC = 2    # includes OE
 799     RC_ONLY = 3  # does not include OE
 800
 801
 802 @unique
 803 class CryIn(Enum):
 804     ZERO = 0
 805     ONE = 1
 806     CA = 2
 807     OV = 3
 808
 809
 810 @unique
 811 class CRInSel(Enum):
 812     NONE = 0
 813     CR0 = 1
 814     BI = 2
 815     BFA = 3
 816     BA_BB = 4
 817     BC = 5
 818     WHOLE_REG = 6
 819     CR1 = 7
 820     BA = 8
 821
 822
 823 @unique
 824 class CRIn2Sel(Enum):
 825     NONE = 0
 826     BB = 1
 827
 828
 829 @unique
 830 class CROutSel(Enum):
 831     NONE = 0
 832     CR0 = 1
 833     BF = 2
 834     BT = 3
 835     WHOLE_REG = 4
 836     CR1 = 5
 837
 838
 839 # SPRs - Special-Purpose Registers.  See V3.0B Figure 18 p971 and
 840 # http://libre-riscv.org/openpower/isatables/sprs.csv
 841 # http://bugs.libre-riscv.org/show_bug.cgi?id=261
 842 # http://bugs.libre-riscv.org/show_bug.cgi?id=859 - KAIVB
 843
 844 def get_spr_enum(full_file):
 845     """get_spr_enum - creates an Enum of SPRs, dynamically
 846     has the option to reduce the enum to a much shorter list.
 847     this saves drastically on the size of the regfile
 848     """
 849     short_list = {'PIDR', 'DAR', 'PRTBL', 'DSISR', 'SVSRR0', 'SVSTATE',
 850                   'SVSTATE0', 'SVSTATE1', 'SVSTATE2', 'SVSTATE3',
 851                   'SPRG0_priv', 'SPRG1_priv', 'SPRG2_priv', 'SPRG3_priv',
 852                   'SPRG0', 'SPRG1', 'SPRG2', 'SPRG3', 'KAIVB',
 853                   # hmmm should not be including these, they are FAST regs
 854                   'CTR', 'LR', 'TAR', 'SRR0', 'SRR1', 'XER', 'DEC', 'TB', 'TBU',
 855                   'HSRR0', 'HSRR1', 'HSPRG0', 'HSPRG1',
 856                   }
 857     spr_csv = []
 858     for row in get_csv("sprs.csv"):
 859         if full_file or row['SPR'] in short_list:
 860             spr_csv.append(row)
 861
 862     spr_info = namedtuple('spr_info', 'SPR priv_mtspr priv_mfspr length idx')
 863     spr_dict = {}
 864     spr_byname = {}
 865     for row in spr_csv:
 866         info = spr_info(SPR=row['SPR'], priv_mtspr=row['priv_mtspr'],
 867                         priv_mfspr=row['priv_mfspr'], length=int(row['len']),
 868                         idx=int(row['Idx']))
 869         spr_dict[int(row['Idx'])] = info
 870         spr_byname[row['SPR']] = info
 871     fields = [(row['SPR'], int(row['Idx'])) for row in spr_csv]
 872     SPR = Enum('SPR', fields)
 873     return SPR, spr_dict, spr_byname
 874
 875
 876 SPRfull, spr_dict, spr_byname = get_spr_enum(full_file=True)
 877 SPRreduced, _, _ = get_spr_enum(full_file=False)
 878
 879 XER_bits = {
 880     'SO': 32,
 881     'OV': 33,
 882     'CA': 34,
 883     'OV32': 44,
 884     'CA32': 45
 885 }
 886
 887 MSRSpec = namedtuple("MSRSpec", ["dr", "pr", "sf"])
 888
 889 if __name__ == '__main__':
 890     # find out what the heck is in SPR enum :)
 891     print("sprs full", len(SPRfull))
 892     print(dir(SPRfull))
 893     print("sprs reduced", len(SPRreduced))
 894     print(dir(SPRreduced))
 895     print(dir(Enum))
 896     print(SPRfull.__members__['TAR'])
 897     for x in SPRfull:
 898         print("full", x, x.value, str(x), x.name)
 899     for x in SPRreduced:
 900         print("reduced", x, x.value, str(x), x.name)
 901
 902     print("function", Function.ALU.name)