1 # SPDX-License-Identifier: LGPL-3-or-later
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2020, Michael Nolan
5 """Enums used in OpenPOWER ISA decoding
7 Note: for SV, from v3.1B p12:
9 The designated SPR sandbox consists of non-privileged SPRs 704-719 and
10 privileged SPRs 720-735.
12 Note: the option exists to select a much shorter list of SPRs, to reduce
13 regfile size in HDL. this is SPRreduced and the supported list is in
24 from os
.path
import dirname
, join
25 from collections
import namedtuple
30 filedir
= os
.path
.dirname(os
.path
.abspath(__file__
))
31 basedir
= dirname(dirname(dirname(filedir
)))
32 tabledir
= join(basedir
, 'openpower')
33 isatables
= join(tabledir
, 'isatables')
34 #print ("find_wiki_dir", isatables)
38 def find_wiki_file(name
):
39 return join(find_wiki_dir(), name
)
43 retval
= _get_csv(name
)
44 return [i
.copy() for i
in retval
]
47 @functools.lru_cache()
49 """gets a not-entirely-csv-file-formatted database, which allows comments
51 file_path
= find_wiki_file(name
)
52 with
open(file_path
, 'r') as csvfile
:
53 csvfile
= filter(lambda row
: row
[0] !='#', csvfile
) # strip "#..."
54 reader
= csv
.DictReader(csvfile
)
58 # names of the fields in the tables that don't correspond to an enum
59 single_bit_flags
= ['inv A', 'inv out',
60 'cry out', 'BR', 'sgn ext', 'rsrv', '32b',
61 'sgn', 'lk', 'sgl pipe']
63 # default values for fields in the table
64 default_values
= {'unit': "NONE", 'internal op': "OP_ILLEGAL",
65 'in1': "RA", 'in2': 'NONE', 'in3': 'NONE', 'out': 'NONE',
69 'rc': 'NONE', 'cry in': 'ZERO', 'form': 'NONE'}
72 def get_signal_name(name
):
75 return name
.lower().replace(' ', '_')
80 def _missing_(cls
, desc
):
81 if isinstance(desc
, str):
89 keys
= {item
.name
:item
for item
in cls
}
90 descs
= {item
.value
:item
for item
in cls
}
91 return keys
.get(desc
, descs
.get(desc
))
94 # this corresponds to which Function Unit (pipeline-with-Reservation-Stations)
95 # is to process and guard the operation. they are roughly divided by having
96 # the same register input/output signature (X-Form, etc.)
100 class Function(Enum
):
113 SV
= 1 << 12 # Simple-V https://libre-soc.org/openpower/sv
117 @functools.lru_cache(maxsize
=None)
120 value
= int(self
.value
)
126 desc
= f
"(1 << {counter})"
129 return f
"<{self.__class__.__name__}.{self.name}: {desc}>"
163 SVL
= 29 # Simple-V for setvl instruction
164 SVD
= 30 # Simple-V for LD/ST bit-reverse, variant of D-Form
165 SVDS
= 31 # Simple-V for LD/ST bit-reverse, variant of DS-Form
166 SVM
= 32 # Simple-V SHAPE mode
167 SVM2
= 33 # Simple-V SHAPE2 mode - fits into SVM
168 SVRM
= 34 # Simple-V REMAP mode
172 SVI
= 38 # Simple-V Index Mode
176 CRB
= 42 # crternlogi / crbinlut
177 MM
= 43 # [f]minmax[s][.]
182 # Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/
186 NONE
= 0 # for non-SV instructions only
199 P2M
= 3 # for mixed EXTRA3/3/2 where MASK_SRC is RM[6,7,18]
202 def _missing_(cls
, desc
):
203 return {"1P": SVPType
.P1
, "2P": SVPType
.P2
, "2PM": SVPType
.P2M
}.get(desc
)
207 SVPType
.NONE
: "NONE",
217 * EXTRA2 : 0: [10,11] 1: [12,13] 2: [14,15] 3: [16,17] unused: [18]
218 * EXTRA3 : 0: [10,11,12] 1: [13,14,15] mask: [16,17,18]
219 * EXTRA32: 0: [10,11,12] 1: [13,14,15] 2: [16,17] mask: [6,7,18]
224 EXTRA32
= 3 # mixed EXTRA3 and EXTRA2 using RM bits 6&7 for MASK_SRC
231 class SVMaskSrc(Enum
):
246 Idx_1_2
= 5 # due to weird BA/BB for crops
250 SVExtra
.NONE
: "NONE",
251 SVExtra
.Idx0
: "EXTRA0",
252 SVExtra
.Idx1
: "EXTRA1",
253 SVExtra
.Idx2
: "EXTRA2",
254 SVExtra
.Idx3
: "EXTRA3",
255 SVExtra
.Idx_1_2
: "EXTRA1/EXTRA2",
258 # Backward compatibility
300 def _missing_(cls
, desc
):
302 In1Sel
, In2Sel
, In3Sel
, CRInSel
, CRIn2Sel
,
305 if isinstance(desc
, selectors
):
306 return cls
.__members
__.get(desc
.name
)
308 return cls
.__members
__.get(desc
)
320 if alias
is not None:
324 Reg
.RA_OR_ZERO
: Reg
.RA
,
325 Reg
.RT_OR_ZERO
: Reg
.RT
,
327 if alias
is not None:
352 class SVP64PredMode(Enum
):
360 class SVP64PredInt(Enum
):
371 def _missing_(cls
, desc
):
372 if isinstance(desc
, str):
383 if value
.startswith("~"):
384 value
= f
"~{value[1:].strip()}"
385 elif "<<" in value
: # 1 << r3
386 (lhs
, _
, rhs
) = value
.partition("<<")
387 lhs
= lhs
.strip().lower()
388 rhs
= rhs
.strip().lower()
389 if (lhs
== "1") and (rhs
in ("r3", "%r3")):
392 return values
.get(value
)
394 return super()._missing
_(desc
)
398 self
.__class
__.ALWAYS
: "",
399 self
.__class
__.R3_UNARY
: "^r3",
400 self
.__class
__.R3
: "r3",
401 self
.__class
__.R3_N
: "~r3",
402 self
.__class
__.R10
: "r10",
403 self
.__class
__.R10_N
: "~r10",
404 self
.__class
__.R30
: "r30",
405 self
.__class
__.R30_N
: "~r30",
409 return f
"{self.__class__.__name__}({str(self)})"
416 return SVP64PredMode
.INT
420 return (self
.value
& 0b1)
424 return (self
.value
>> 1)
427 class SVP64PredCR(Enum
):
442 def _missing_(cls
, desc
):
443 if isinstance(desc
, str):
445 return cls
.__members
__.get(name
)
447 return super()._missing
_(desc
)
454 return SVP64PredMode
.CR
458 return (self
.value
& 0b1)
462 return (self
.value
>> 1)
466 class SVP64PredRC1(Enum
):
471 def _missing_(cls
, desc
):
473 "RC1": SVP64PredRC1
.RC1
,
474 "~RC1": SVP64PredRC1
.RC1_N
,
482 return SVP64PredMode
.RC1
486 return (self
is SVP64PredRC1
.RC1_N
)
493 class SVP64Pred(Enum
):
494 ALWAYS
= SVP64PredInt
.ALWAYS
495 R3_UNARY
= SVP64PredInt
.R3_UNARY
497 R3_N
= SVP64PredInt
.R3_N
498 R10
= SVP64PredInt
.R10
499 R10_N
= SVP64PredInt
.R10_N
500 R30
= SVP64PredInt
.R30
501 R30_N
= SVP64PredInt
.R30_N
512 RC1
= SVP64PredRC1
.RC1
513 RC1_N
= SVP64PredRC1
.RC1_N
516 def _missing_(cls
, desc
):
517 if isinstance(desc
, str):
518 values
= {item
.value
:item
for item
in cls
}
519 for subcls
in (SVP64PredInt
, SVP64PredCR
, SVP64PredRC1
):
521 return values
.get(subcls(desc
))
526 return super()._missing
_(desc
)
529 return int(self
.value
)
533 return self
.value
.mode
537 return self
.value
.inv
541 return self
.value
.state
545 class SVP64RMMode(Enum
):
554 class SVP64BCPredMode(Enum
):
561 class SVP64BCVLSETMode(Enum
):
567 # note that these are chosen to be exactly the same as
568 # SVP64 RM bit 4. ALL=1 => bit4=1
570 class SVP64BCGate(Enum
):
575 class SVP64BCCTRMode(Enum
):
582 class SVP64Width(Enum
):
589 def _missing_(cls
, desc
):
590 if isinstance(desc
, str):
592 "32": SVP64Width
.EW_32
,
593 "16": SVP64Width
.EW_16
,
594 "8": SVP64Width
.EW_8
,
597 return super()._missing
_(desc
)
601 class SVP64SubVL(Enum
):
608 def _missing_(cls
, desc
):
609 if isinstance(desc
, str):
611 return cls
.__members
__.get(name
)
613 return super()._missing
_(desc
)
617 class SVP64Sat(Enum
):
624 class SVP64LDSTmode(Enum
):
652 CR_3BIT
= 2 # CR field; the CR register is 32-bit
656 CR_5BIT
= 3 # bit of the 32-bit CR register
663 XER_BIT
= 4 # XER bits, includes OV, OV32, SO, CA, CA32
671 def _missing_(cls
, value
):
672 if isinstance(value
, Reg
):
673 return cls
.__members
__.get(value
.name
)
675 return super()._missing
_(value
)
680 "fatan2pi", "fatan2pis",
689 "fexp2m1", "fexp2m1s",
690 "flog2p1", "flog2p1s",
697 "fexp10m1", "fexp10m1s",
698 "flog10p1", "flog10p1s",
710 "fasinpi", "fasinpis",
711 "facospi", "facospis",
712 "fatanpi", "fatanpis",
721 "fremainder", "fremainders",
725 # supported instructions: make sure to keep up-to-date with CSV files
726 # just like everything else
728 "NONE", "add", "addc", "addco", "adde", "addeo",
729 "addi", "addic", "addic.", "addis",
730 "addme", "addmeo", "addo", "addze", "addzeo",
733 "and", "andc", "andi.", "andis.",
735 "absdu", "absds", # AV bitmanip
736 "absdacs", "absdacu", # AV bitmanip
737 "avgadd", # AV bitmanip
738 "b", "bc", "bcctr", "bclr", "bctar",
740 "bmask", # AV bitmanip
745 "cmp", "cmpb", "cmpeqb", "cmpi", "cmpl", "cmpli", "cmprb",
746 "cntlzd", "cntlzdm", "cntlzw", "cnttzd", "cnttzdm", "cnttzw",
747 "cprop", # AV bitmanip
748 "crand", "crandc", "creqv",
749 "crnand", "crnor", "cror", "crorc", "crxor",
751 "dcbf", "dcbst", "dcbt", "dcbtst", "dcbz",
752 "divd", "divde", "divdeo", "divdeu",
753 "divdeuo", "divdo", "divdu", "divduo",
755 "divw", "divwe", "divweo",
756 "divweu", "divweuo", "divwo", "divwu", "divwuo",
757 "dsld", "dsld.", "dsrd", "dsrd.",
759 "extsb", "extsh", "extsw", "extswsli",
760 "fadd", "fadds", "fsub", "fsubs", # FP add / sub
761 "fcfids", "fcfidus", "fsqrts", "fres", "frsqrtes", # FP stuff
762 "fdmadds", # DCT FP 3-arg
763 "fmsubs", "fmadds", "fnmsubs", "fnmadds", # FP 3-arg
764 "ffadds", "ffsubs", "ffmuls", "ffdivs", # FFT FP 2-arg
765 "ffmsubs", "ffmadds", "ffnmsubs", "ffnmadds", # FFT FP 3-arg
766 "fmul", "fmuls", "fdiv", "fdivs", # FP mul / div
767 "fmr", "fabs", "fnabs", "fneg", "fcpsgn", # FP move/abs/neg
768 "fmvis", # FP load immediate
769 "fishmv", # Float Replace Lower-Half Single, Immediate
774 "hrfid", "icbi", "icbt", "isel", "isync",
775 "lbarx", "lbz", "lbzcix", "lbzu", "lbzux", "lbzx", # load byte
776 "ld", "ldarx", "ldbrx", "ldu", "ldux", "ldx", # load double
777 # "lbzbr", "lbzubr", # load byte SVP64 bit-reversed
778 # "ldbr", "ldubr", # load double SVP64 bit-reversed
779 "lfs", "lfsx", "lfsu", "lfsux", # FP load single
780 "lfd", "lfdx", "lfdu", "lfdux", "lfiwzx", "lfiwax", # FP load double
781 "lha", "lharx", "lhau", "lhaux", "lhax", # load half
782 "lhbrx", "lhz", "lhzu", "lhzux", "lhzx", # more load half
783 # "lhabr", "lhaubr", # load half SVP64 bit-reversed
784 # "lhzbr", "lhzubr", # more load half SVP64 bit-reversed
785 "lwa", "lwarx", "lwaux", "lwax", "lwbrx", # load word
786 "lwz", "lwzcix", "lwzu", "lwzux", "lwzx", # more load word
787 # "lwabr", # load word SVP64 bit-reversed
788 # "lwzbr", "lwzubr", # more load word SVP64 bit-reversed
789 "maddedu", "maddedus",
790 "maddhd", "maddhdu", "maddld", # INT multiply-and-add
791 "maddsubrs", # Integer DCT Butterfly Add Sub and Round Shift
792 "maddrs", # Integer DCT Butterfly Add and Accumulate and Round Shift
793 "msubrs", # Integer DCT Butterfly Subtract from and Round Shift
794 "mcrf", "mcrxr", "mcrxrx", "mfcr/mfocrf", # CR mvs
796 "minmax", # AV bitmanip
797 "modsd", "modsw", "modud", "moduw",
798 "mtcrf/mtocrf", "mtmsr", "mtmsrd", "mtspr",
799 "mulhd", "mulhdu", "mulhw", "mulhwu", "mulld", "mulldo",
800 "mulli", "mullw", "mullwo",
801 "nand", "neg", "nego",
803 "nor", "or", "orc", "ori", "oris",
806 "popcntb", "popcntd", "popcntw",
809 "rldcl", "rldcr", "rldic", "rldicl", "rldicr", "rldimi",
810 "rlwimi", "rlwinm", "rlwnm",
812 "setbc", "setbcr", "setnbc", "setnbcr",
813 "setvl", # https://libre-soc.org/openpower/sv/setvl
815 "svindex", # https://libre-soc.org/openpower/sv/remap
816 "svremap", # https://libre-soc.org/openpower/sv/remap - TEMPORARY
817 "svshape", # https://libre-soc.org/openpower/sv/remap/#svshape
818 "svshape2", # https://libre-soc.org/openpower/sv/remap/discussion TODO
819 "svstep", # https://libre-soc.org/openpower/sv/setvl
821 "sadd", "saddw", "sadduw",
822 "slbia", "sld", "slw", "srad", "sradi",
823 "sraw", "srawi", "srd", "srw",
824 "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
825 "std", "stdbrx", "stdcx", "stdu", "stdux", "stdx",
826 "stfs", "stfsx", "stfsu", "stfux", "stfsux", # FP store single
827 "stfd", "stfdx", "stfdu", "stfdux", "stfiwx", # FP store double
828 "sth", "sthbrx", "sthcx", "sthu", "sthux", "sthx",
829 "stw", "stwbrx", "stwcx", "stwu", "stwux", "stwx",
830 "subf", "subfc", "subfco", "subfe", "subfeo", "subfic",
831 "subfme", "subfmeo", "subfo", "subfze", "subfzeo",
835 "tlbie", "tlbiel", "tlbsync",
838 "xor", "xori", "xoris",
842 # two-way lookup of instruction-to-index and vice-versa
845 for i
, insn
in enumerate(_insns
):
849 # must be long enough to cover all instructions
850 asmlen
= len(_insns
).bit_length()
852 # Internal Operation numbering. Add new opcodes here (FPADD, FPMUL etc.)
857 OP_ILLEGAL
= 0 # important that this is zero (see power_decoder.py)
931 OP_FPOP
= 77 # temporary: replace with actual ops
932 OP_FPOP_I
= 78 # temporary: replace with actual ops
975 SelType
.NONE
: "NONE",
986 RS
= 4 # for some ALU/Logical operations
993 CIA
= 8 # for addpcis
997 if self
is In1Sel
.RA_OR_ZERO
:
1003 if self
is In1Sel
.NONE
:
1022 RS
= 13 # for shiftrot (M-Form)
1026 CONST_SVD
= 15 # for SVD-Form
1027 CONST_SVDS
= 16 # for SVDS-Form
1029 CONST_DXHI4
= 18 # for addpcis
1030 CONST_DQ
= 19 # for ld/st-quad
1037 if self
is In2Sel
.NONE
:
1046 RB
= 2 # for shiftrot (M-Form)
1050 RC
= 5 # for SVP64 bit-reverse LD/ST
1051 RT
= 6 # for ternlog[i]
1060 if self
is In3Sel
.NONE
:
1081 if self
is OutSel
.RT_OR_ZERO
:
1087 if self
is OutSel
.NONE
:
1093 class LDSTLen(Enum
):
1100 # Backward compatibility
1105 class LDSTMode(Enum
):
1116 RC
= 2 # includes OE
1117 RC_ONLY
= 3 # does not include OE
1129 class CRInSel(Enum
):
1145 if self
is CRInSel
.NONE
:
1151 class CRIn2Sel(Enum
):
1160 if self
is CRIn2Sel
.NONE
:
1166 class CROutSel(Enum
):
1179 if self
is CROutSel
.NONE
:
1184 # SPRs - Special-Purpose Registers. See V3.0B Figure 18 p971 and
1185 # http://libre-riscv.org/openpower/isatables/sprs.csv
1186 # http://bugs.libre-riscv.org/show_bug.cgi?id=261
1187 # http://bugs.libre-riscv.org/show_bug.cgi?id=859 - KAIVB
1189 def get_spr_enum(full_file
):
1190 """get_spr_enum - creates an Enum of SPRs, dynamically
1191 has the option to reduce the enum to a much shorter list.
1192 this saves drastically on the size of the regfile
1194 short_list
= {'PIDR', 'DAR', 'PRTBL', 'DSISR', 'SVSRR0', 'SVSTATE',
1195 'SVSTATE0', 'SVSTATE1', 'SVSTATE2', 'SVSTATE3',
1196 'SPRG0_priv', 'SPRG1_priv', 'SPRG2_priv', 'SPRG3_priv',
1197 'SPRG0', 'SPRG1', 'SPRG2', 'SPRG3', 'KAIVB',
1198 # hmmm should not be including these, they are FAST regs
1199 'CTR', 'LR', 'TAR', 'SRR0', 'SRR1', 'XER', 'DEC', 'TB', 'TBU',
1200 'HSRR0', 'HSRR1', 'HSPRG0', 'HSPRG1',
1203 for row
in get_csv("sprs.csv"):
1204 if full_file
or row
['SPR'] in short_list
:
1207 spr_info
= namedtuple('spr_info', 'SPR priv_mtspr priv_mfspr length idx')
1211 info
= spr_info(SPR
=row
['SPR'], priv_mtspr
=row
['priv_mtspr'],
1212 priv_mfspr
=row
['priv_mfspr'], length
=int(row
['len']),
1213 idx
=int(row
['Idx']))
1214 spr_dict
[int(row
['Idx'])] = info
1215 spr_byname
[row
['SPR']] = info
1216 fields
= [(row
['SPR'], int(row
['Idx'])) for row
in spr_csv
]
1217 SPR
= Enum('SPR', fields
)
1218 return SPR
, spr_dict
, spr_byname
1221 SPRfull
, spr_dict
, spr_byname
= get_spr_enum(full_file
=True)
1222 SPRreduced
, _
, _
= get_spr_enum(full_file
=False)
1232 MSRSpec
= namedtuple("MSRSpec", ["dr", "pr", "sf"])
1234 # flags for bfp_* functions
1253 class FMinMaxMode(Enum
):
1254 """ FMM field for fminmax instruction.
1255 enumerant names match assembly aliases.
1261 fminmagnum08
= 0b0100
1263 fminmagnum19
= 0b0110
1269 fmaxmagnum08
= 0b1100
1271 fmaxmagnum19
= 0b1110
1274 if __name__
== '__main__':
1275 # find out what the heck is in SPR enum :)
1276 print("sprs full", len(SPRfull
))
1278 print("sprs reduced", len(SPRreduced
))
1279 print(dir(SPRreduced
))
1281 print(SPRfull
.__members
__['TAR'])
1283 print("full", x
, x
.value
, str(x
), x
.name
)
1284 for x
in SPRreduced
:
1285 print("reduced", x
, x
.value
, str(x
), x
.name
)
1287 print("function", Function
.ALU
.name
)