src/openpower/decoder/power_enums.py

   1 # SPDX-License-Identifier: LGPL-3-or-later
   2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3 # Copyright (C) 2020, Michael Nolan
   4
   5 """Enums used in OpenPOWER ISA decoding
   6
   7 Note: for SV, from v3.1B p12:
   8
   9     The designated SPR sandbox consists of non-privileged SPRs 704-719 and
  10     privileged SPRs 720-735.
  11
  12 Note: the option exists to select a much shorter list of SPRs, to reduce
  13 regfile size in HDL.  this is SPRreduced and the supported list is in
  14 get_spr_enum
  15 """
  16
  17 from enum import (
  18     auto,
  19     Enum as _Enum,
  20     unique,
  21 )
  22 import csv
  23 import os
  24 from os.path import dirname, join
  25 from collections import namedtuple
  26 import functools
  27
  28
  29 def find_wiki_dir():
  30     filedir = os.path.dirname(os.path.abspath(__file__))
  31     basedir = dirname(dirname(dirname(filedir)))
  32     tabledir = join(basedir, 'openpower')
  33     isatables = join(tabledir, 'isatables')
  34     #print ("find_wiki_dir", isatables)
  35     return isatables
  36
  37
  38 def find_wiki_file(name):
  39     return join(find_wiki_dir(), name)
  40
  41
  42 def get_csv(name):
  43     """gets a not-entirely-csv-file-formatted database, which allows comments
  44     """
  45     file_path = find_wiki_file(name)
  46     with open(file_path, 'r') as csvfile:
  47         csvfile = filter(lambda row: row[0] !='#', csvfile) # strip "#..."
  48         reader = csv.DictReader(csvfile)
  49         return list(reader)
  50
  51
  52 # names of the fields in the tables that don't correspond to an enum
  53 single_bit_flags = ['inv A', 'inv out',
  54                     'cry out', 'BR', 'sgn ext', 'rsrv', '32b',
  55                     'sgn', 'lk', 'sgl pipe']
  56
  57 # default values for fields in the table
  58 default_values = {'unit': "NONE", 'internal op': "OP_ILLEGAL",
  59                   'in1': "RA", 'in2': 'NONE', 'in3': 'NONE', 'out': 'NONE',
  60                   'CR in': 'NONE',
  61                   'ldst len': 'NONE',
  62                   'upd': '0',
  63                   'rc': 'NONE', 'cry in': 'ZERO', 'form': 'NONE'}
  64
  65
  66 def get_signal_name(name):
  67     if name[0].isdigit():
  68         name = "is_" + name
  69     return name.lower().replace(' ', '_')
  70
  71
  72 class Enum(_Enum):
  73     @classmethod
  74     def _missing_(cls, value):
  75         if isinstance(value, str):
  76             try:
  77                 if value == "":
  78                     value = 0
  79                 else:
  80                     value = int(value, 0)
  81             except ValueError:
  82                 pass
  83         keys = {item.name:item for item in cls}
  84         values = {item.value:item for item in cls}
  85         item = keys.get(value, values.get(value))
  86         if item is None:
  87             raise ValueError(value)
  88         return item
  89
  90
  91 # this corresponds to which Function Unit (pipeline-with-Reservation-Stations)
  92 # is to process and guard the operation.  they are roughly divided by having
  93 # the same register input/output signature (X-Form, etc.)
  94
  95
  96 @unique
  97 class Function(Enum):
  98     NONE = 0
  99     ALU = 1 << 1
 100     LDST = 1 << 2
 101     SHIFT_ROT = 1 << 3
 102     LOGICAL = 1 << 4
 103     BRANCH = 1 << 5
 104     CR = 1 << 6
 105     TRAP = 1 << 7
 106     MUL = 1 << 8
 107     DIV = 1 << 9
 108     SPR = 1 << 10
 109     MMU = 1 << 11
 110     SV = 1 << 12  # Simple-V https://libre-soc.org/openpower/sv
 111     VL = 1 << 13  # setvl
 112     FPU = 1 << 14  # FPU
 113
 114     @functools.lru_cache(maxsize=None)
 115     def __repr__(self):
 116         counter = 0
 117         value = int(self.value)
 118         if value != 0:
 119             while value != 0:
 120                 counter += 1
 121                 value >>= 1
 122             counter -= 1
 123             desc = f"(1 << {counter})"
 124         else:
 125             desc = "0"
 126         return f"<{self.__class__.__name__}.{self.name}: {desc}>"
 127
 128
 129 @unique
 130 class Form(Enum):
 131     NONE = 0
 132     I = 1
 133     B = 2
 134     SC = 3
 135     D = 4
 136     DS = 5
 137     DQ = 6
 138     DX = 7
 139     X = 8
 140     XL = 9
 141     XFX = 10
 142     XFL = 11
 143     XX1 = 12
 144     XX2 = 13
 145     XX3 = 14
 146     XX4 = 15
 147     XS = 16
 148     XO = 17
 149     A = 18
 150     M = 19
 151     MD = 20
 152     MDS = 21
 153     VA = 22
 154     VC = 23
 155     VX = 24
 156     EVX = 25
 157     EVS = 26
 158     Z22 = 27
 159     Z23 = 28
 160     SVL = 29  # Simple-V for setvl instruction
 161     SVD = 30  # Simple-V for LD/ST bit-reverse, variant of D-Form
 162     SVDS = 31  # Simple-V for LD/ST bit-reverse, variant of DS-Form
 163     SVM = 32  # Simple-V SHAPE mode
 164     SVM2 = 33  # Simple-V SHAPE2 mode - fits into SVM
 165     SVRM = 34  # Simple-V REMAP mode
 166     TLI = 35  # ternlogi
 167     XB = 36
 168     BM2 = 37 # bmask
 169     SVI = 38  # Simple-V Index Mode
 170     VA2 = 39
 171     SVC = 40
 172     SVR = 41
 173
 174 # Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/
 175
 176
 177 class SVMode(Enum):
 178     NONE = 0          # for non-SV instructions only
 179     NORMAL = auto()
 180     LDST_IDX = auto()
 181     LDST_IMM = auto()
 182     BRANCH = auto()
 183     CROP = auto()
 184
 185
 186 @unique
 187 class SVPtype(Enum):
 188     NONE = 0
 189     P1 = 1
 190     P2 = 2
 191
 192     @classmethod
 193     def _missing_(cls, value):
 194         return {"1P": SVPtype.P1, "2P": SVPtype.P2}[value]
 195
 196     def __repr__(self):
 197         return {
 198             SVPtype.NONE: "NONE",
 199             SVPtype.P1: "1P",
 200             SVPtype.P2: "2P",
 201         }[self]
 202
 203
 204 @unique
 205 class SVEtype(Enum):
 206     NONE = 0
 207     EXTRA2 = 1
 208     EXTRA3 = 2
 209
 210     def __repr__(self):
 211         return self.name
 212
 213
 214 @unique
 215 class SVmask_src(Enum):
 216     NO = 0
 217     EN = 1
 218
 219     def __repr__(self):
 220         return self.name
 221
 222
 223 @unique
 224 class SVExtra(Enum):
 225     NONE = 0
 226     Idx0 = 1
 227     Idx1 = 2
 228     Idx2 = 3
 229     Idx3 = 4
 230     Idx_1_2 = 5  # due to weird BA/BB for crops
 231
 232     def __repr__(self):
 233         return {
 234             SVExtra.NONE: "NONE",
 235             SVExtra.Idx0: "[0]",
 236             SVExtra.Idx1: "[1]",
 237             SVExtra.Idx2: "[2]",
 238             SVExtra.Idx3: "[3]",
 239             SVExtra.Idx_1_2: "[1:2]",
 240         }[self]
 241
 242 # Backward compatibility
 243 SVEXTRA = SVExtra
 244
 245
 246 class SVExtraRegType(Enum):
 247     NONE = None
 248     SRC = 's'
 249     DST = 'd'
 250
 251
 252 class SVExtraReg(Enum):
 253     NONE = auto()
 254     RA = auto()
 255     RA_OR_ZERO = RA
 256     RB = auto()
 257     RC = auto()
 258     RS = auto()
 259     RT = auto()
 260     RT_OR_ZERO = RT
 261     FRA = auto()
 262     FRB = auto()
 263     FRC = auto()
 264     FRS = auto()
 265     FRT = auto()
 266     CR = auto()
 267     CR0 = auto()
 268     CR1 = auto()
 269     BF = auto()
 270     BFA = auto()
 271     BA = auto()
 272     BB = auto()
 273     BC = auto()
 274     BI = auto()
 275     BT = auto()
 276     BFT = auto()
 277     WHOLE_REG = auto()
 278     SPR = auto()
 279
 280     @classmethod
 281     def _missing_(cls, value):
 282         selectors = (
 283             In1Sel, In2Sel, In3Sel, CRInSel, CRIn2Sel,
 284             OutSel, CROutSel,
 285         )
 286         if isinstance(value, selectors):
 287             return cls.__members__[value.name]
 288         return super()._missing_(value)
 289
 290
 291 @unique
 292 class SVP64PredMode(Enum):
 293     ALWAYS = 0
 294     INT = 1
 295     CR = 2
 296
 297
 298 @unique
 299 class SVP64PredInt(Enum):
 300     ALWAYS = 0
 301     R3_UNARY = 1
 302     R3 = 2
 303     R3_N = 3
 304     R10 = 4
 305     R10_N = 5
 306     R30 = 6
 307     R30_N = 7
 308
 309
 310 @unique
 311 class SVP64PredCR(Enum):
 312     LT = 0
 313     GE = 1
 314     GT = 2
 315     LE = 3
 316     EQ = 4
 317     NE = 5
 318     SO = 6
 319     NS = 7
 320
 321
 322 @unique
 323 class SVP64RMMode(Enum):
 324     NORMAL = 0
 325     MAPREDUCE = 1
 326     FFIRST = 2
 327     SATURATE = 3
 328     PREDRES = 4
 329     BRANCH = 5
 330
 331
 332 @unique
 333 class SVP64BCPredMode(Enum):
 334     NONE = 0
 335     MASKZERO = 1
 336     MASKONE = 2
 337
 338
 339 @unique
 340 class SVP64BCVLSETMode(Enum):
 341     NONE = 0
 342     VL_INCL = 1
 343     VL_EXCL = 2
 344
 345
 346 # note that these are chosen to be exactly the same as
 347 # SVP64 RM bit 4.  ALL=1 => bit4=1
 348 @unique
 349 class SVP64BCGate(Enum):
 350     ANY = 0
 351     ALL = 1
 352
 353
 354 class SVP64BCCTRMode(Enum):
 355     NONE = 0
 356     TEST = 1
 357     TEST_INV = 2
 358
 359
 360 @unique
 361 class SVP64width(Enum):
 362     DEFAULT = 0
 363     EW_32 = 1
 364     EW_16 = 2
 365     EW_8 = 3
 366
 367
 368 @unique
 369 class SVP64subvl(Enum):
 370     VEC1 = 0
 371     VEC2 = 1
 372     VEC3 = 2
 373     VEC4 = 3
 374
 375
 376 @unique
 377 class SVP64sat(Enum):
 378     NONE = 0
 379     SIGNED = 1
 380     UNSIGNED = 2
 381
 382
 383 @unique
 384 class SVP64LDSTmode(Enum):
 385     NONE = 0
 386     INDEXED = 1
 387     ELSTRIDE = 2
 388     UNITSTRIDE = 3
 389
 390
 391 class RegType(Enum):
 392     GPR = 0
 393     RA = GPR
 394     RB = GPR
 395     RC = GPR
 396     RS = GPR
 397     RT = GPR
 398
 399     FPR = 1
 400     FRA = FPR
 401     FRB = FPR
 402     FRC = FPR
 403     FRS = FPR
 404     FRT = FPR
 405
 406     CR_REG = 2  # actually CR Field. the CR register is 32-bit.
 407     BF = CR_REG
 408     BFA = CR_REG
 409
 410     CR_BIT = 3 # refers to one bit of the 32-bit CR register
 411     BA = CR_BIT
 412     BB = CR_BIT
 413     BC = CR_BIT
 414     BI = CR_BIT
 415     BT = CR_BIT
 416
 417     @classmethod
 418     def _missing_(cls, value):
 419         if isinstance(value, SVExtraReg):
 420             return cls.__members__[value.name]
 421         return super()._missing_(value)
 422
 423
 424 FPTRANS_INSNS = (
 425     "fatan2", "fatan2s",
 426     "fatan2pi", "fatan2pis",
 427     "fpow", "fpows",
 428     "fpown", "fpowns",
 429     "fpowr", "fpowrs",
 430     "frootn", "frootns",
 431     "fhypot", "fhypots",
 432     "frsqrt", "frsqrts",
 433     "fcbrt", "fcbrts",
 434     "frecip", "frecips",
 435     "fexp2m1", "fexp2m1s",
 436     "flog2p1", "flog2p1s",
 437     "fexp2", "fexp2s",
 438     "flog2", "flog2s",
 439     "fexpm1", "fexpm1s",
 440     "flogp1", "flogp1s",
 441     "fexp", "fexps",
 442     "flog", "flogs",
 443     "fexp10m1", "fexp10m1s",
 444     "flog10p1", "flog10p1s",
 445     "fexp10", "fexp10s",
 446     "flog10", "flog10s",
 447     "fsin", "fsins",
 448     "fcos", "fcoss",
 449     "ftan", "ftans",
 450     "fasin", "fasins",
 451     "facos", "facoss",
 452     "fatan", "fatans",
 453     "fsinpi", "fsinpis",
 454     "fcospi", "fcospis",
 455     "ftanpi", "ftanpis",
 456     "fasinpi", "fasinpis",
 457     "facospi", "facospis",
 458     "fatanpi", "fatanpis",
 459     "fsinh", "fsinhs",
 460     "fcosh", "fcoshs",
 461     "ftanh", "ftanhs",
 462     "fasinh", "fasinhs",
 463     "facosh", "facoshs",
 464     "fatanh", "fatanhs",
 465     "fminnum08", "fminnum08s",
 466     "fmaxnum08", "fmaxnum08s",
 467     "fmin19", "fmin19s",
 468     "fmax19", "fmax19s",
 469     "fminnum19", "fminnum19s",
 470     "fmaxnum19", "fmaxnum19s",
 471     "fminc", "fmincs",
 472     "fmaxc", "fmaxcs",
 473     "fminmagnum08", "fminmagnum08s",
 474     "fmaxmagnum08", "fmaxmagnum08s",
 475     "fminmag19", "fminmag19s",
 476     "fmaxmag19", "fmaxmag19s",
 477     "fminmagnum19", "fminmagnum19s",
 478     "fmaxmagnum19", "fmaxmagnum19s",
 479     "fminmagc", "fminmagcs",
 480     "fmaxmagc", "fmaxmagcs",
 481     "fmod", "fmods",
 482     "fremainder", "fremainders",
 483 )
 484
 485
 486 # supported instructions: make sure to keep up-to-date with CSV files
 487 # just like everything else
 488 _insns = [
 489     "NONE", "add", "addc", "addco", "adde", "addeo",
 490     "addi", "addic", "addic.", "addis",
 491     "addme", "addmeo", "addo", "addze", "addzeo",
 492     "addg6s",
 493     "and", "andc", "andi.", "andis.",
 494     "attn",
 495     "absdu", "absds",                         # AV bitmanip
 496     "absdacs", "absdacu",                     # AV bitmanip
 497     "avgadd",                                 # AV bitmanip
 498     "b", "bc", "bcctr", "bclr", "bctar",
 499     "bmask",                                  # AV bitmanip
 500     "bpermd",
 501     "cbcdtd",
 502     "cdtbcd",
 503     "cmp", "cmpb", "cmpeqb", "cmpi", "cmpl", "cmpli", "cmprb",
 504     "cntlzd", "cntlzw", "cnttzd", "cnttzw",
 505     "cprop", # AV bitmanip
 506     "crand", "crandc", "creqv",
 507     "crnand", "crnor", "cror", "crorc", "crxor",
 508     "darn",
 509     "dcbf", "dcbst", "dcbt", "dcbtst", "dcbz",
 510     "divd", "divde", "divdeo", "divdeu",
 511     "divdeuo", "divdo", "divdu", "divduo",
 512     "divmod2du",
 513     "divw", "divwe", "divweo",
 514     "divweu", "divweuo", "divwo", "divwu", "divwuo",
 515     "dsld", "dsrd",
 516     "eieio", "eqv",
 517     "extsb", "extsh", "extsw", "extswsli",
 518     "fadd", "fadds", "fsub", "fsubs",                   # FP add / sub
 519     "fcfids", "fcfidus", "fsqrts", "fres", "frsqrtes",  # FP stuff
 520     "fdmadds",                                          # DCT FP 3-arg
 521     "fmsubs", "fmadds", "fnmsubs", "fnmadds",           # FP 3-arg
 522     "ffadds", "ffsubs", "ffmuls", "ffdivs",             # FFT FP 2-arg
 523     "ffmsubs", "ffmadds", "ffnmsubs", "ffnmadds",       # FFT FP 3-arg
 524     "fmul", "fmuls", "fdiv", "fdivs",                   # FP mul / div
 525     "fmr", "fabs", "fnabs", "fneg", "fcpsgn",           # FP move/abs/neg
 526     "fmvis",                                            # FP load immediate
 527     "fishmv",                                           # Float Replace Lower-Half Single, Immediate
 528     'grev', 'grev.', 'grevi', 'grevi.',
 529     'grevw', 'grevw.', 'grevwi', 'grevwi.',
 530     "hrfid", "icbi", "icbt", "isel", "isync",
 531     "lbarx", "lbz", "lbzcix", "lbzu", "lbzux", "lbzx",  # load byte
 532     "ld", "ldarx", "ldbrx", "ldu", "ldux", "ldx",       # load double
 533     # "lbzbr", "lbzubr",  # load byte SVP64 bit-reversed
 534     # "ldbr", "ldubr",    # load double SVP64 bit-reversed
 535     "lfs", "lfsx", "lfsu", "lfsux",                     # FP load single
 536     "lfd", "lfdx", "lfdu", "lfdux", "lfiwzx", "lfiwax",  # FP load double
 537     "lha", "lharx", "lhau", "lhaux", "lhax",            # load half
 538     "lhbrx", "lhz", "lhzu", "lhzux", "lhzx",            # more load half
 539     # "lhabr", "lhaubr",  # load half SVP64 bit-reversed
 540     # "lhzbr", "lhzubr",  # more load half SVP64 bit-reversed
 541     "lwa", "lwarx", "lwaux", "lwax", "lwbrx",           # load word
 542     "lwz", "lwzcix", "lwzu", "lwzux", "lwzx",           # more load word
 543     # "lwabr",           # load word SVP64 bit-reversed
 544     # "lwzbr", "lwzubr", # more load word SVP64 bit-reversed
 545     "maddedu",
 546     "maddhd", "maddhdu", "maddld",                      # INT multiply-and-add
 547     "mcrf", "mcrxr", "mcrxrx", "mfcr/mfocrf",           # CR mvs
 548     "mfmsr", "mfspr",
 549     "mins", "maxs", "minu", "maxu",                     # AV bitmanip
 550     "modsd", "modsw", "modud", "moduw",
 551     "mtcrf/mtocrf", "mtmsr", "mtmsrd", "mtspr",
 552     "mulhd", "mulhdu", "mulhw", "mulhwu", "mulld", "mulldo",
 553     "mulli", "mullw", "mullwo",
 554     "nand", "neg", "nego",
 555     "nop",
 556     "nor", "or", "orc", "ori", "oris",
 557     "pcdec",
 558     "popcntb", "popcntd", "popcntw",
 559     "prtyd", "prtyw",
 560     "rfid",
 561     "rldcl", "rldcr", "rldic", "rldicl", "rldicr", "rldimi",
 562     "rlwimi", "rlwinm",    "rlwnm",
 563     "setb",
 564     "setvl",  # https://libre-soc.org/openpower/sv/setvl
 565     "svindex",  # https://libre-soc.org/openpower/sv/remap
 566     "svremap",  # https://libre-soc.org/openpower/sv/remap - TEMPORARY
 567     "svshape",  # https://libre-soc.org/openpower/sv/remap/#svshape
 568     "svshape2",  # https://libre-soc.org/openpower/sv/remap/discussion TODO
 569     "svstep",  # https://libre-soc.org/openpower/sv/setvl
 570     "sim_cfg",
 571     "slbia", "sld", "slw", "srad", "sradi",
 572     "sraw", "srawi", "srd", "srw",
 573     "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
 574     "std", "stdbrx", "stdcx", "stdu", "stdux", "stdx",
 575     "stfs", "stfsx", "stfsu", "stfux", "stfsux",        # FP store single
 576     "stfd", "stfdx", "stfdu", "stfdux", "stfiwx",       # FP store double
 577     "sth", "sthbrx", "sthcx", "sthu", "sthux", "sthx",
 578     "stw", "stwbrx", "stwcx", "stwu", "stwux", "stwx",
 579     "subf", "subfc", "subfco", "subfe", "subfeo", "subfic",
 580     "subfme", "subfmeo", "subfo", "subfze", "subfzeo",
 581     "sync",
 582     "ternlogi",
 583     "td", "tdi",
 584     "tlbie", "tlbiel", "tlbsync",
 585     "tw", "twi",
 586     "wait",
 587     "xor", "xori", "xoris",
 588     *FPTRANS_INSNS,
 589 ]
 590
 591 # two-way lookup of instruction-to-index and vice-versa
 592 insns = {}
 593 asmidx = {}
 594 for i, insn in enumerate(_insns):
 595     insns[i] = insn
 596     asmidx[insn] = i
 597
 598 # must be long enough to cover all instructions
 599 asmlen = len(_insns).bit_length()
 600
 601 # Internal Operation numbering.  Add new opcodes here (FPADD, FPMUL etc.)
 602
 603
 604 @unique
 605 class MicrOp(Enum):
 606     OP_ILLEGAL = 0     # important that this is zero (see power_decoder.py)
 607     OP_NOP = 1
 608     OP_ADD = 2
 609     OP_ADDPCIS = 3
 610     OP_AND = 4
 611     OP_ATTN = 5
 612     OP_B = 6
 613     OP_BC = 7
 614     OP_BCREG = 8
 615     OP_BPERM = 9
 616     OP_CMP = 10
 617     OP_CMPB = 11
 618     OP_CMPEQB = 12
 619     OP_CMPRB = 13
 620     OP_CNTZ = 14
 621     OP_CRAND = 15
 622     OP_CRANDC = 16
 623     OP_CREQV = 17
 624     OP_CRNAND = 18
 625     OP_CRNOR = 19
 626     OP_CROR = 20
 627     OP_CRORC = 21
 628     OP_CRXOR = 22
 629     OP_DARN = 23
 630     OP_DCBF = 24
 631     OP_DCBST = 25
 632     OP_DCBT = 26
 633     OP_DCBTST = 27
 634     OP_DCBZ = 28
 635     OP_DIV = 29
 636     OP_DIVE = 30
 637     OP_EXTS = 31
 638     OP_EXTSWSLI = 32
 639     OP_ICBI = 33
 640     OP_ICBT = 34
 641     OP_ISEL = 35
 642     OP_ISYNC = 36
 643     OP_LOAD = 37
 644     OP_STORE = 38
 645     OP_MADDHD = 39
 646     OP_MADDHDU = 40
 647     OP_MADDLD = 41
 648     OP_MCRF = 42
 649     OP_MCRXR = 43
 650     OP_MCRXRX = 44
 651     OP_MFCR = 45
 652     OP_MFSPR = 46
 653     OP_MOD = 47
 654     OP_MTCRF = 48
 655     OP_MTSPR = 49
 656     OP_MUL_L64 = 50
 657     OP_MUL_H64 = 51
 658     OP_MUL_H32 = 52
 659     OP_OR = 53
 660     OP_POPCNT = 54
 661     OP_PRTY = 55
 662     OP_RLC = 56
 663     OP_RLCL = 57
 664     OP_RLCR = 58
 665     OP_SETB = 59
 666     OP_SHL = 60
 667     OP_SHR = 61
 668     OP_SYNC = 62
 669     OP_TRAP = 63
 670     OP_XOR = 67
 671     OP_SIM_CONFIG = 68
 672     OP_CROP = 69
 673     OP_RFID = 70
 674     OP_MFMSR = 71
 675     OP_MTMSRD = 72
 676     OP_SC = 73
 677     OP_MTMSR = 74
 678     OP_TLBIE = 75
 679     OP_SETVL = 76
 680     OP_FPOP = 77  # temporary: replace with actual ops
 681     OP_FPOP_I = 78  # temporary: replace with actual ops
 682     OP_FP_MADD = 79
 683     OP_SVREMAP = 80
 684     OP_SVSHAPE = 81
 685     OP_SVSTEP = 82
 686     OP_ADDG6S = 83
 687     OP_CDTBCD = 84
 688     OP_CBCDTD = 85
 689     OP_TERNLOG = 86
 690     OP_FETCH_FAILED = 87
 691     OP_GREV = 88
 692     OP_MINMAX = 89
 693     OP_AVGADD = 90
 694     OP_ABSDIFF = 91
 695     OP_ABSADD = 92
 696     OP_CPROP = 93
 697     OP_BMASK = 94
 698     OP_SVINDEX = 95
 699     OP_FMVIS = 96
 700     OP_FISHMV = 97
 701     OP_PCDEC = 98
 702     OP_MADDEDU = 99
 703     OP_DIVMOD2DU = 100
 704     OP_DSHL = 101
 705     OP_DSHR = 102
 706
 707
 708 @unique
 709 class In1Sel(Enum):
 710     NONE = 0
 711     RA = 1
 712     RA_OR_ZERO = 2
 713     SPR = 3
 714     RS = 4  # for some ALU/Logical operations
 715     FRA = 5
 716     FRS = 6
 717     CIA = 7 # for addpcis
 718
 719
 720 @unique
 721 class In2Sel(Enum):
 722     NONE = 0
 723     RB = 1
 724     CONST_UI = 2
 725     CONST_SI = 3
 726     CONST_UI_HI = 4
 727     CONST_SI_HI = 5
 728     CONST_LI = 6
 729     CONST_BD = 7
 730     CONST_DS = 8
 731     CONST_M1 = 9
 732     CONST_SH = 10
 733     CONST_SH32 = 11
 734     SPR = 12
 735     RS = 13  # for shiftrot (M-Form)
 736     FRB = 14
 737     CONST_SVD = 15  # for SVD-Form
 738     CONST_SVDS = 16  # for SVDS-Form
 739     CONST_XBI = 17
 740     CONST_DXHI4 = 18 # for addpcis
 741
 742
 743 @unique
 744 class In3Sel(Enum):
 745     NONE = 0
 746     RS = 1
 747     RB = 2  # for shiftrot (M-Form)
 748     FRS = 3
 749     FRC = 4
 750     RC = 5  # for SVP64 bit-reverse LD/ST
 751     RT = 6  # for ternlog[i]
 752
 753
 754 @unique
 755 class OutSel(Enum):
 756     NONE = 0
 757     RT = 1
 758     RA = 2
 759     SPR = 3
 760     RT_OR_ZERO = 4
 761     FRT = 5
 762     FRS = 6
 763     RS = 7
 764
 765
 766 @unique
 767 class LDSTLen(Enum):
 768     NONE = 0
 769     is1B = 1
 770     is2B = 2
 771     is4B = 4
 772     is8B = 8
 773
 774 # Backward compatibility
 775 LdstLen = LDSTLen
 776
 777
 778 @unique
 779 class LDSTMode(Enum):
 780     NONE = 0
 781     update = 1
 782     cix = 2
 783     cx = 3
 784
 785
 786 @unique
 787 class RCOE(Enum):
 788     NONE = 0
 789     ONE = 1
 790     RC = 2    # includes OE
 791     RC_ONLY = 3  # does not include OE
 792
 793
 794 @unique
 795 class CryIn(Enum):
 796     ZERO = 0
 797     ONE = 1
 798     CA = 2
 799     # TODO OV = 3
 800
 801
 802 @unique
 803 class CRInSel(Enum):
 804     NONE = 0
 805     CR0 = 1
 806     BI = 2
 807     BFA = 3
 808     BA_BB = 4
 809     BC = 5
 810     WHOLE_REG = 6
 811     CR1 = 7
 812     BA = 8
 813
 814
 815 @unique
 816 class CRIn2Sel(Enum):
 817     NONE = 0
 818     BB = 1
 819
 820
 821 @unique
 822 class CROutSel(Enum):
 823     NONE = 0
 824     CR0 = 1
 825     BF = 2
 826     BT = 3
 827     WHOLE_REG = 4
 828     CR1 = 5
 829
 830
 831 # SPRs - Special-Purpose Registers.  See V3.0B Figure 18 p971 and
 832 # http://libre-riscv.org/openpower/isatables/sprs.csv
 833 # http://bugs.libre-riscv.org/show_bug.cgi?id=261
 834 # http://bugs.libre-riscv.org/show_bug.cgi?id=859 - KAIVB
 835
 836 def get_spr_enum(full_file):
 837     """get_spr_enum - creates an Enum of SPRs, dynamically
 838     has the option to reduce the enum to a much shorter list.
 839     this saves drastically on the size of the regfile
 840     """
 841     short_list = {'PIDR', 'DAR', 'PRTBL', 'DSISR', 'SVSRR0', 'SVSTATE',
 842                   'SVSTATE0', 'SVSTATE1', 'SVSTATE2', 'SVSTATE3',
 843                   'SPRG0_priv', 'SPRG1_priv', 'SPRG2_priv', 'SPRG3_priv',
 844                   'SPRG0', 'SPRG1', 'SPRG2', 'SPRG3', 'KAIVB',
 845                   # hmmm should not be including these, they are FAST regs
 846                   'CTR', 'LR', 'TAR', 'SRR0', 'SRR1', 'XER', 'DEC', 'TB', 'TBU',
 847                   'HSRR0', 'HSRR1', 'HSPRG0', 'HSPRG1',
 848                   }
 849     spr_csv = []
 850     for row in get_csv("sprs.csv"):
 851         if full_file or row['SPR'] in short_list:
 852             spr_csv.append(row)
 853
 854     spr_info = namedtuple('spr_info', 'SPR priv_mtspr priv_mfspr length idx')
 855     spr_dict = {}
 856     spr_byname = {}
 857     for row in spr_csv:
 858         info = spr_info(SPR=row['SPR'], priv_mtspr=row['priv_mtspr'],
 859                         priv_mfspr=row['priv_mfspr'], length=int(row['len']),
 860                         idx=int(row['Idx']))
 861         spr_dict[int(row['Idx'])] = info
 862         spr_byname[row['SPR']] = info
 863     fields = [(row['SPR'], int(row['Idx'])) for row in spr_csv]
 864     SPR = Enum('SPR', fields)
 865     return SPR, spr_dict, spr_byname
 866
 867
 868 SPRfull, spr_dict, spr_byname = get_spr_enum(full_file=True)
 869 SPRreduced, _, _ = get_spr_enum(full_file=False)
 870
 871 XER_bits = {
 872     'SO': 32,
 873     'OV': 33,
 874     'CA': 34,
 875     'OV32': 44,
 876     'CA32': 45
 877 }
 878
 879 MSRSpec = namedtuple("MSRSpec", ["dr", "pr", "sf"])
 880
 881 if __name__ == '__main__':
 882     # find out what the heck is in SPR enum :)
 883     print("sprs full", len(SPRfull))
 884     print(dir(SPRfull))
 885     print("sprs reduced", len(SPRreduced))
 886     print(dir(SPRreduced))
 887     print(dir(Enum))
 888     print(SPRfull.__members__['TAR'])
 889     for x in SPRfull:
 890         print("full", x, x.value, str(x), x.name)
 891     for x in SPRreduced:
 892         print("reduced", x, x.value, str(x), x.name)
 893
 894     print("function", Function.ALU.name)