1 # SPDX-License-Identifier: LGPL-3-or-later
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2020, Michael Nolan
5 """Enums used in OpenPOWER ISA decoding
7 Note: for SV, from v3.1B p12:
9 The designated SPR sandbox consists of non-privileged SPRs 704-719 and
10 privileged SPRs 720-735.
12 Note: the option exists to select a much shorter list of SPRs, to reduce
13 regfile size in HDL. this is SPRreduced and the supported list is in
24 from os
.path
import dirname
, join
25 from collections
import namedtuple
30 filedir
= os
.path
.dirname(os
.path
.abspath(__file__
))
31 basedir
= dirname(dirname(dirname(filedir
)))
32 tabledir
= join(basedir
, 'openpower')
33 isatables
= join(tabledir
, 'isatables')
34 #print ("find_wiki_dir", isatables)
38 def find_wiki_file(name
):
39 return join(find_wiki_dir(), name
)
43 """gets a not-entirely-csv-file-formatted database, which allows comments
45 file_path
= find_wiki_file(name
)
46 with
open(file_path
, 'r') as csvfile
:
47 csvfile
= filter(lambda row
: row
[0] !='#', csvfile
) # strip "#..."
48 reader
= csv
.DictReader(csvfile
)
52 # names of the fields in the tables that don't correspond to an enum
53 single_bit_flags
= ['inv A', 'inv out',
54 'cry out', 'BR', 'sgn ext', 'rsrv', '32b',
55 'sgn', 'lk', 'sgl pipe']
57 # default values for fields in the table
58 default_values
= {'unit': "NONE", 'internal op': "OP_ILLEGAL",
59 'in1': "RA", 'in2': 'NONE', 'in3': 'NONE', 'out': 'NONE',
63 'rc': 'NONE', 'cry in': 'ZERO', 'form': 'NONE'}
66 def get_signal_name(name
):
69 return name
.lower().replace(' ', '_')
74 def _missing_(cls
, value
):
75 if isinstance(value
, str):
83 keys
= {item
.name
:item
for item
in cls
}
84 values
= {item
.value
:item
for item
in cls
}
85 item
= keys
.get(value
, values
.get(value
))
87 raise ValueError(value
)
91 # this corresponds to which Function Unit (pipeline-with-Reservation-Stations)
92 # is to process and guard the operation. they are roughly divided by having
93 # the same register input/output signature (X-Form, etc.)
110 SV
= 1 << 12 # Simple-V https://libre-soc.org/openpower/sv
114 @functools.lru_cache(maxsize
=None)
117 value
= int(self
.value
)
123 desc
= f
"(1 << {counter})"
126 return f
"<{self.__class__.__name__}.{self.name}: {desc}>"
160 SVL
= 29 # Simple-V for setvl instruction
161 SVD
= 30 # Simple-V for LD/ST bit-reverse, variant of D-Form
162 SVDS
= 31 # Simple-V for LD/ST bit-reverse, variant of DS-Form
163 SVM
= 32 # Simple-V SHAPE mode
164 SVM2
= 33 # Simple-V SHAPE2 mode - fits into SVM
165 SVRM
= 34 # Simple-V REMAP mode
169 SVI
= 38 # Simple-V Index Mode
174 # Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/
192 def _missing_(cls
, value
):
193 return {"1P": SVPtype
.P1
, "2P": SVPtype
.P2
}[value
]
197 SVPtype
.NONE
: "NONE",
220 Idx_1_2
= 5 # due to weird BA/BB for crops
224 SVExtra
.NONE
: "NONE",
229 SVExtra
.Idx_1_2
: "[1:2]",
232 # Backward compatibility
236 class SVExtraRegType(Enum
):
242 class SVExtraReg(Enum
):
271 def _missing_(cls
, value
):
273 In1Sel
, In2Sel
, In3Sel
, CRInSel
,
276 if isinstance(value
, selectors
):
277 return cls
.__members
__.get(value
.name
, cls
.NONE
)
278 return super()._missing
_(value
)
282 class SVP64PredMode(Enum
):
289 class SVP64PredInt(Enum
):
301 class SVP64PredCR(Enum
):
313 class SVP64RMMode(Enum
):
323 class SVP64BCPredMode(Enum
):
330 class SVP64BCVLSETMode(Enum
):
336 # note that these are chosen to be exactly the same as
337 # SVP64 RM bit 4. ALL=1 => bit4=1
339 class SVP64BCGate(Enum
):
344 class SVP64BCCTRMode(Enum
):
351 class SVP64width(Enum
):
359 class SVP64subvl(Enum
):
367 class SVP64sat(Enum
):
374 class SVP64LDSTmode(Enum
):
396 CR_REG
= 2 # actually CR Field. the CR register is 32-bit.
400 CR_BIT
= 3 # refers to one bit of the 32-bit CR register
409 # supported instructions: make sure to keep up-to-date with CSV files
410 # just like everything else
412 "NONE", "add", "addc", "addco", "adde", "addeo",
413 "addi", "addic", "addic.", "addis",
414 "addme", "addmeo", "addo", "addze", "addzeo",
416 "and", "andc", "andi.", "andis.",
418 "absdu", "absds", # AV bitmanip
419 "absdacs", "absdacu", # AV bitmanip
420 "avgadd", # AV bitmanip
421 "b", "bc", "bcctr", "bclr", "bctar",
422 "bmask", # AV bitmanip
426 "cmp", "cmpb", "cmpeqb", "cmpi", "cmpl", "cmpli", "cmprb",
427 "cntlzd", "cntlzw", "cnttzd", "cnttzw",
428 "cprop", # AV bitmanip
429 "crand", "crandc", "creqv",
430 "crnand", "crnor", "cror", "crorc", "crxor",
432 "dcbf", "dcbst", "dcbt", "dcbtst", "dcbz",
433 "divd", "divde", "divdeo", "divdeu",
434 "divdeuo", "divdo", "divdu", "divduo", "divw", "divwe", "divweo",
435 "divweu", "divweuo", "divwo", "divwu", "divwuo",
437 "extsb", "extsh", "extsw", "extswsli",
438 "fadd", "fadds", "fsub", "fsubs", # FP add / sub
439 "fcfids", "fcfidus", "fsqrts", "fres", "frsqrtes", # FP stuff
440 "fdmadds", # DCT FP 3-arg
441 "fmsubs", "fmadds", "fnmsubs", "fnmadds", # FP 3-arg
442 "ffadds", "ffsubs", "ffmuls", "ffdivs", # FFT FP 2-arg
443 "ffmsubs", "ffmadds", "ffnmsubs", "ffnmadds", # FFT FP 3-arg
444 "fmul", "fmuls", "fdiv", "fdivs", # FP mul / div
445 "fmr", "fabs", "fnabs", "fneg", "fcpsgn", # FP move/abs/neg
446 "fsins", "fcoss", # FP SIN/COS
447 "fmvis", # FP load immediate
448 "fishmv", # Float Replace Lower-Half Single, Immediate
449 'grev', 'grev.', 'grevi', 'grevi.',
450 'grevw', 'grevw.', 'grevwi', 'grevwi.',
451 "hrfid", "icbi", "icbt", "isel", "isync",
452 "lbarx", "lbz", "lbzcix", "lbzu", "lbzux", "lbzx", # load byte
453 "ld", "ldarx", "ldbrx", "ldu", "ldux", "ldx", # load double
454 # "lbzbr", "lbzubr", # load byte SVP64 bit-reversed
455 # "ldbr", "ldubr", # load double SVP64 bit-reversed
456 "lfs", "lfsx", "lfsu", "lfsux", # FP load single
457 "lfd", "lfdx", "lfdu", "lfdux", "lfiwzx", "lfiwax", # FP load double
458 "lha", "lharx", "lhau", "lhaux", "lhax", # load half
459 "lhbrx", "lhz", "lhzu", "lhzux", "lhzx", # more load half
460 # "lhabr", "lhaubr", # load half SVP64 bit-reversed
461 # "lhzbr", "lhzubr", # more load half SVP64 bit-reversed
462 "lwa", "lwarx", "lwaux", "lwax", "lwbrx", # load word
463 "lwz", "lwzcix", "lwzu", "lwzux", "lwzx", # more load word
464 # "lwabr", # load word SVP64 bit-reversed
465 # "lwzbr", "lwzubr", # more load word SVP64 bit-reversed
466 "maddhd", "maddhdu", "maddld", # INT multiply-and-add
467 "mcrf", "mcrxr", "mcrxrx", "mfcr/mfocrf", # CR mvs
469 "mins", "maxs", "minu", "maxu", # AV bitmanip
470 "modsd", "modsw", "modud", "moduw",
471 "mtcrf/mtocrf", "mtmsr", "mtmsrd", "mtspr",
472 "mulhd", "mulhdu", "mulhw", "mulhwu", "mulld", "mulldo",
473 "mulli", "mullw", "mullwo",
474 "nand", "neg", "nego",
476 "nor", "or", "orc", "ori", "oris",
477 "popcntb", "popcntd", "popcntw",
480 "rldcl", "rldcr", "rldic", "rldicl", "rldicr", "rldimi",
481 "rlwimi", "rlwinm", "rlwnm",
483 "setvl", # https://libre-soc.org/openpower/sv/setvl
484 "svindex", # https://libre-soc.org/openpower/sv/remap
485 "svremap", # https://libre-soc.org/openpower/sv/remap - TEMPORARY
486 "svshape", # https://libre-soc.org/openpower/sv/remap/#svshape
487 "svshape2", # https://libre-soc.org/openpower/sv/remap/discussion TODO
488 "svstep", # https://libre-soc.org/openpower/sv/setvl
490 "slbia", "sld", "slw", "srad", "sradi",
491 "sraw", "srawi", "srd", "srw",
492 "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
493 "std", "stdbrx", "stdcx", "stdu", "stdux", "stdx",
494 "stfs", "stfsx", "stfsu", "stfux", "stfsux", # FP store single
495 "stfd", "stfdx", "stfdu", "stfdux", "stfiwx", # FP store double
496 "sth", "sthbrx", "sthcx", "sthu", "sthux", "sthx",
497 "stw", "stwbrx", "stwcx", "stwu", "stwux", "stwx",
498 "subf", "subfc", "subfco", "subfe", "subfeo", "subfic",
499 "subfme", "subfmeo", "subfo", "subfze", "subfzeo",
503 "tlbie", "tlbiel", "tlbsync",
506 "xor", "xori", "xoris",
509 # two-way lookup of instruction-to-index and vice-versa
512 for i
, insn
in enumerate(_insns
):
516 # must be long enough to cover all instructions
517 asmlen
= len(_insns
).bit_length()
519 # Internal Operation numbering. Add new opcodes here (FPADD, FPMUL etc.)
524 OP_ILLEGAL
= 0 # important that this is zero (see power_decoder.py)
598 OP_FPOP
= 77 # temporary: replace with actual ops
599 OP_FPOP_I
= 78 # temporary: replace with actual ops
627 RS
= 4 # for some ALU/Logical operations
647 RS
= 13 # for shiftrot (M-Form)
649 CONST_SVD
= 15 # for SVD-Form
650 CONST_SVDS
= 16 # for SVDS-Form
658 RB
= 2 # for shiftrot (M-Form)
661 RC
= 5 # for SVP64 bit-reverse LD/ST
662 RT
= 6 # for ternlog[i]
684 # Backward compatibility
689 class LDSTMode(Enum
):
701 RC_ONLY
= 3 # does not include OE
725 class CROutSel(Enum
):
734 # SPRs - Special-Purpose Registers. See V3.0B Figure 18 p971 and
735 # http://libre-riscv.org/openpower/isatables/sprs.csv
736 # http://bugs.libre-riscv.org/show_bug.cgi?id=261
737 # http://bugs.libre-riscv.org/show_bug.cgi?id=859 - KAIVB
739 def get_spr_enum(full_file
):
740 """get_spr_enum - creates an Enum of SPRs, dynamically
741 has the option to reduce the enum to a much shorter list.
742 this saves drastically on the size of the regfile
744 short_list
= {'PIDR', 'DAR', 'PRTBL', 'DSISR', 'SVSRR0', 'SVSTATE',
745 'SVSTATE0', 'SVSTATE1', 'SVSTATE2', 'SVSTATE3',
746 'SPRG0_priv', 'SPRG1_priv', 'SPRG2_priv', 'SPRG3_priv',
747 'SPRG0', 'SPRG1', 'SPRG2', 'SPRG3', 'KAIVB',
748 # hmmm should not be including these, they are FAST regs
749 'CTR', 'LR', 'TAR', 'SRR0', 'SRR1', 'XER', 'DEC', 'TB', 'TBU',
750 'HSRR0', 'HSRR1', 'HSPRG0', 'HSPRG1',
753 for row
in get_csv("sprs.csv"):
754 if full_file
or row
['SPR'] in short_list
:
757 spr_info
= namedtuple('spr_info', 'SPR priv_mtspr priv_mfspr length idx')
761 info
= spr_info(SPR
=row
['SPR'], priv_mtspr
=row
['priv_mtspr'],
762 priv_mfspr
=row
['priv_mfspr'], length
=int(row
['len']),
764 spr_dict
[int(row
['Idx'])] = info
765 spr_byname
[row
['SPR']] = info
766 fields
= [(row
['SPR'], int(row
['Idx'])) for row
in spr_csv
]
767 SPR
= Enum('SPR', fields
)
768 return SPR
, spr_dict
, spr_byname
771 SPRfull
, spr_dict
, spr_byname
= get_spr_enum(full_file
=True)
772 SPRreduced
, _
, _
= get_spr_enum(full_file
=False)
782 MSRSpec
= namedtuple("MSRSpec", ["dr", "pr", "sf"])
784 if __name__
== '__main__':
785 # find out what the heck is in SPR enum :)
786 print("sprs full", len(SPRfull
))
788 print("sprs reduced", len(SPRreduced
))
789 print(dir(SPRreduced
))
791 print(SPRfull
.__members
__['TAR'])
793 print("full", x
, x
.value
, str(x
), x
.name
)
795 print("reduced", x
, x
.value
, str(x
), x
.name
)
797 print("function", Function
.ALU
.name
)