1 import collections
as _collections
3 import dataclasses
as _dataclasses
5 import functools
as _functools
7 import operator
as _operator
8 import pathlib
as _pathlib
13 from functools
import cached_property
15 from cached_property
import cached_property
17 from openpower
.decoder
.power_enums
import (
18 Function
as _Function
,
25 CRIn2Sel
as _CRIn2Sel
,
26 CROutSel
as _CROutSel
,
28 LDSTMode
as _LDSTMode
,
33 SVMaskSrc
as _SVMaskSrc
,
38 SVP64RMMode
as _SVP64RMMode
,
39 SVExtraRegType
as _SVExtraRegType
,
40 SVExtraReg
as _SVExtraReg
,
41 SVP64SubVL
as _SVP64SubVL
,
42 SVP64Pred
as _SVP64Pred
,
43 SVP64PredMode
as _SVP64PredMode
,
44 SVP64Width
as _SVP64Width
,
46 from openpower
.decoder
.selectable_int
import (
47 SelectableInt
as _SelectableInt
,
48 selectconcat
as _selectconcat
,
50 from openpower
.decoder
.power_fields
import (
53 DecodeFields
as _DecodeFields
,
55 from openpower
.decoder
.pseudo
.pagereader
import ISA
as _ISA
58 @_functools.total_ordering
59 class Style(_enum
.Enum
):
63 VERBOSE
= _enum
.auto()
65 def __lt__(self
, other
):
66 if not isinstance(other
, self
.__class
__):
68 return (self
.value
< other
.value
)
71 @_functools.total_ordering
72 class Priority(_enum
.Enum
):
78 def _missing_(cls
, value
):
79 if isinstance(value
, str):
84 return super()._missing
_(value
)
86 def __lt__(self
, other
):
87 if not isinstance(other
, self
.__class
__):
90 # NOTE: the order is inversed, LOW < NORMAL < HIGH
91 return (self
.value
> other
.value
)
94 def dataclass(cls
, record
, keymap
=None, typemap
=None):
98 typemap
= {field
.name
:field
.type for field
in _dataclasses
.fields(cls
)}
100 def transform(key_value
):
101 (key
, value
) = key_value
102 key
= keymap
.get(key
, key
)
103 hook
= typemap
.get(key
, lambda value
: value
)
104 if hook
is bool and value
in ("", "0"):
110 record
= dict(map(transform
, record
.items()))
111 for key
in frozenset(record
.keys()):
112 if record
[key
] == "":
118 @_functools.total_ordering
119 @_dataclasses.dataclass(eq
=True, frozen
=True)
122 def __new__(cls
, value
):
123 if isinstance(value
, str):
124 value
= int(value
, 0)
125 if not isinstance(value
, int):
126 raise ValueError(value
)
128 if value
.bit_length() > 64:
129 raise ValueError(value
)
131 return super().__new
__(cls
, value
)
134 return self
.__repr
__()
137 return f
"{self:0{self.bit_length()}b}"
139 def bit_length(self
):
140 if super().bit_length() > 32:
144 class Value(Integer
):
153 def __lt__(self
, other
):
154 if not isinstance(other
, Opcode
):
155 return NotImplemented
156 return ((self
.value
, self
.mask
) < (other
.value
, other
.mask
))
159 def pattern(value
, mask
, bit_length
):
160 for bit
in range(bit_length
):
161 if ((mask
& (1 << (bit_length
- bit
- 1))) == 0):
163 elif (value
& (1 << (bit_length
- bit
- 1))):
168 return "".join(pattern(self
.value
, self
.mask
, self
.value
.bit_length()))
170 def match(self
, key
):
171 return ((self
.value
& self
.mask
) == (key
& self
.mask
))
174 @_functools.total_ordering
175 @_dataclasses.dataclass(eq
=True, frozen
=True)
176 class IntegerOpcode(Opcode
):
177 def __init__(self
, value
):
178 if value
.startswith("0b"):
179 mask
= int(("1" * len(value
[2:])), 2)
183 value
= Opcode
.Value(value
)
184 mask
= Opcode
.Mask(mask
)
186 return super().__init
__(value
=value
, mask
=mask
)
189 @_functools.total_ordering
190 @_dataclasses.dataclass(eq
=True, frozen
=True)
191 class PatternOpcode(Opcode
):
192 def __init__(self
, pattern
):
193 if not isinstance(pattern
, str):
194 raise ValueError(pattern
)
196 (value
, mask
) = (0, 0)
197 for symbol
in pattern
:
198 if symbol
not in {"0", "1", "-"}:
199 raise ValueError(pattern
)
200 value |
= (symbol
== "1")
201 mask |
= (symbol
!= "-")
207 value
= Opcode
.Value(value
)
208 mask
= Opcode
.Mask(mask
)
210 return super().__init
__(value
=value
, mask
=mask
)
213 @_dataclasses.dataclass(eq
=True, frozen
=True)
215 class FlagsMeta(type):
230 class Flags(tuple, metaclass
=FlagsMeta
):
231 def __new__(cls
, flags
=frozenset()):
232 flags
= frozenset(flags
)
233 diff
= (flags
- frozenset(cls
))
235 raise ValueError(flags
)
236 return super().__new
__(cls
, sorted(flags
))
240 flags
: Flags
= Flags()
242 function
: _Function
= _Function
.NONE
243 intop
: _MicrOp
= _MicrOp
.OP_ILLEGAL
244 in1
: _In1Sel
= _In1Sel
.RA
245 in2
: _In2Sel
= _In2Sel
.NONE
246 in3
: _In3Sel
= _In3Sel
.NONE
247 out
: _OutSel
= _OutSel
.NONE
248 cr_in
: _CRInSel
= _CRInSel
.NONE
249 cr_in2
: _CRIn2Sel
= _CRIn2Sel
.NONE
250 cr_out
: _CROutSel
= _CROutSel
.NONE
251 cry_in
: _CryIn
= _CryIn
.ZERO
252 ldst_len
: _LDSTLen
= _LDSTLen
.NONE
253 upd
: _LDSTMode
= _LDSTMode
.NONE
254 Rc
: _RCOE
= _RCOE
.NONE
255 form
: _Form
= _Form
.NONE
257 unofficial
: bool = False
261 "internal op": "intop",
265 "ldst len": "ldst_len",
267 "CONDITIONS": "conditions",
270 def __lt__(self
, other
):
271 if not isinstance(other
, self
.__class
__):
272 return NotImplemented
273 lhs
= (self
.opcode
, self
.comment
)
274 rhs
= (other
.opcode
, other
.comment
)
278 def CSV(cls
, record
, opcode_cls
):
279 typemap
= {field
.name
:field
.type for field
in _dataclasses
.fields(cls
)}
280 typemap
["opcode"] = opcode_cls
282 if record
["CR in"] == "BA_BB":
283 record
["cr_in"] = "BA"
284 record
["cr_in2"] = "BB"
288 for flag
in frozenset(PPCRecord
.Flags
):
289 if bool(record
.pop(flag
, "")):
291 record
["flags"] = PPCRecord
.Flags(flags
)
293 return dataclass(cls
, record
,
294 keymap
=PPCRecord
.__KEYMAP
,
299 return frozenset(self
.comment
.split("=")[-1].split("/"))
302 class PPCMultiRecord(tuple):
303 def __getattr__(self
, attr
):
306 raise AttributeError(attr
)
307 return getattr(self
[0], attr
)
310 @_dataclasses.dataclass(eq
=True, frozen
=True)
312 class ExtraMap(tuple):
314 @_dataclasses.dataclass(eq
=True, frozen
=True)
316 regtype
: _SVExtraRegType
= _SVExtraRegType
.NONE
317 reg
: _SVExtraReg
= _SVExtraReg
.NONE
320 return f
"{self.regtype.value}:{self.reg.name}"
322 def __new__(cls
, value
="0"):
323 if isinstance(value
, str):
324 def transform(value
):
325 (regtype
, reg
) = value
.split(":")
326 regtype
= _SVExtraRegType(regtype
)
327 reg
= _SVExtraReg(reg
)
328 return cls
.Entry(regtype
=regtype
, reg
=reg
)
333 value
= map(transform
, value
.split(";"))
335 return super().__new
__(cls
, value
)
338 return repr(list(self
))
340 def __new__(cls
, value
=tuple()):
344 return super().__new
__(cls
, map(cls
.Extra
, value
))
347 return repr({index
:self
[index
] for index
in range(0, 4)})
350 ptype
: _SVPType
= _SVPType
.NONE
351 etype
: _SVEType
= _SVEType
.NONE
352 msrc
: _SVMaskSrc
= _SVMaskSrc
.NO
# MASK_SRC is active
353 in1
: _In1Sel
= _In1Sel
.NONE
354 in2
: _In2Sel
= _In2Sel
.NONE
355 in3
: _In3Sel
= _In3Sel
.NONE
356 out
: _OutSel
= _OutSel
.NONE
357 out2
: _OutSel
= _OutSel
.NONE
358 cr_in
: _CRInSel
= _CRInSel
.NONE
359 cr_in2
: _CRIn2Sel
= _CRIn2Sel
.NONE
360 cr_out
: _CROutSel
= _CROutSel
.NONE
361 extra
: ExtraMap
= ExtraMap()
363 mode
: _SVMode
= _SVMode
.NORMAL
367 "CONDITIONS": "conditions",
376 def CSV(cls
, record
):
377 record
["insn"] = record
["insn"].split("=")[-1]
379 for key
in frozenset({
380 "in1", "in2", "in3", "CR in",
381 "out", "out2", "CR out",
387 if record
["CR in"] == "BA_BB":
388 record
["cr_in"] = "BA"
389 record
["cr_in2"] = "BB"
393 for idx
in range(0, 4):
394 extra
.append(record
.pop(f
"{idx}"))
396 record
["extra"] = cls
.ExtraMap(extra
)
398 return dataclass(cls
, record
, keymap
=cls
.__KEYMAP
)
400 def extra_idx(self
, key
):
408 if key
not in frozenset({
409 "in1", "in2", "in3", "cr_in", "cr_in2",
410 "out", "out2", "cr_out",
414 sel
= getattr(self
, key
)
415 if sel
is _CRInSel
.BA_BB
:
416 yield _SVExtra
.Idx_1_2
419 reg
= _SVExtraReg(sel
)
420 if reg
is _SVExtraReg
.NONE
:
424 _SVExtraRegType
.DST
: {},
425 _SVExtraRegType
.SRC
: {},
427 for index
in range(0, 4):
428 for entry
in self
.extra
[index
]:
429 extra_map
[entry
.regtype
][entry
.reg
] = extra_idx
[index
]
431 for regs
in extra_map
.values():
432 extra
= regs
.get(reg
, _SVExtra
.NONE
)
433 if extra
is not _SVExtra
.NONE
:
436 extra_idx_in1
= property(_functools
.partial(extra_idx
, key
="in1"))
437 extra_idx_in2
= property(_functools
.partial(extra_idx
, key
="in2"))
438 extra_idx_in3
= property(_functools
.partial(extra_idx
, key
="in3"))
439 extra_idx_out
= property(_functools
.partial(extra_idx
, key
="out"))
440 extra_idx_out2
= property(_functools
.partial(extra_idx
, key
="out2"))
441 extra_idx_cr_in
= property(_functools
.partial(extra_idx
, key
="cr_in"))
442 extra_idx_cr_in2
= property(_functools
.partial(extra_idx
, key
="cr_in2"))
443 extra_idx_cr_out
= property(_functools
.partial(extra_idx
, key
="cr_out"))
445 @_functools.lru_cache(maxsize
=None)
446 def extra_reg(self
, key
):
447 return _SVExtraReg(getattr(self
, key
))
449 extra_reg_in1
= property(_functools
.partial(extra_reg
, key
="in1"))
450 extra_reg_in2
= property(_functools
.partial(extra_reg
, key
="in2"))
451 extra_reg_in3
= property(_functools
.partial(extra_reg
, key
="in3"))
452 extra_reg_out
= property(_functools
.partial(extra_reg
, key
="out"))
453 extra_reg_out2
= property(_functools
.partial(extra_reg
, key
="out2"))
454 extra_reg_cr_in
= property(_functools
.partial(extra_reg
, key
="cr_in"))
455 extra_reg_cr_in2
= property(_functools
.partial(extra_reg
, key
="cr_in2"))
456 extra_reg_cr_out
= property(_functools
.partial(extra_reg
, key
="cr_out"))
461 for idx
in range(0, 4):
462 for entry
in self
.extra
[idx
]:
463 if entry
.regtype
is _SVExtraRegType
.DST
:
464 if extra
is not None:
465 raise ValueError(self
.svp64
)
469 if _RegType(extra
.reg
) not in (_RegType
.CR_3BIT
, _RegType
.CR_5BIT
):
470 raise ValueError(self
.svp64
)
475 def extra_CR_3bit(self
):
476 return (_RegType(self
.extra_CR
.reg
) is _RegType
.CR_3BIT
)
480 def __init__(self
, value
=(0, 32)):
481 if isinstance(value
, str):
482 (start
, end
) = map(int, value
.split(":"))
485 if start
< 0 or end
< 0 or start
>= end
:
486 raise ValueError(value
)
491 return super().__init
__()
494 return (self
.__end
- self
.__start
+ 1)
497 return f
"[{self.__start}:{self.__end}]"
500 yield from range(self
.start
, (self
.end
+ 1))
502 def __reversed__(self
):
503 return tuple(reversed(tuple(self
)))
514 @_dataclasses.dataclass(eq
=True, frozen
=True)
516 class Mode(_enum
.Enum
):
517 INTEGER
= _enum
.auto()
518 PATTERN
= _enum
.auto()
521 def _missing_(cls
, value
):
522 if isinstance(value
, str):
523 return cls
[value
.upper()]
524 return super()._missing
_(value
)
527 def __new__(cls
, value
=None):
528 if isinstance(value
, str):
529 if value
.upper() == "NONE":
532 value
= int(value
, 0)
536 return super().__new
__(cls
, value
)
542 return (bin(self
) if self
else "None")
548 opcode
: IntegerOpcode
= None
549 priority
: Priority
= Priority
.NORMAL
551 def __lt__(self
, other
):
552 if not isinstance(other
, self
.__class
__):
553 return NotImplemented
554 return (self
.priority
< other
.priority
)
557 def CSV(cls
, record
):
558 typemap
= {field
.name
:field
.type for field
in _dataclasses
.fields(cls
)}
559 if record
["opcode"] == "NONE":
560 typemap
["opcode"] = lambda _
: None
562 return dataclass(cls
, record
, typemap
=typemap
)
566 def __init__(self
, items
):
567 if isinstance(items
, dict):
568 items
= items
.items()
571 (name
, bitrange
) = item
572 return (name
, tuple(bitrange
.values()))
574 self
.__mapping
= dict(map(transform
, items
))
576 return super().__init
__()
579 return repr(self
.__mapping
)
582 yield from self
.__mapping
.items()
584 def __contains__(self
, key
):
585 return self
.__mapping
.__contains
__(key
)
587 def __getitem__(self
, key
):
588 return self
.__mapping
.get(key
, None)
603 def __init__(self
, insn
, operands
):
605 "b": {"target_addr": TargetAddrOperandLI
},
606 "ba": {"target_addr": TargetAddrOperandLI
},
607 "bl": {"target_addr": TargetAddrOperandLI
},
608 "bla": {"target_addr": TargetAddrOperandLI
},
609 "bc": {"target_addr": TargetAddrOperandBD
},
610 "bca": {"target_addr": TargetAddrOperandBD
},
611 "bcl": {"target_addr": TargetAddrOperandBD
},
612 "bcla": {"target_addr": TargetAddrOperandBD
},
613 "addpcis": {"D": DOperandDX
},
614 "fishmv": {"D": DOperandDX
},
615 "fmvis": {"D": DOperandDX
},
617 # FIXME: these instructions are broken according to the specs.
618 # The operands in the assembly syntax are FRT,FRA,FRC,FRB.
619 # The real assembly order, however, is FRT,FRA,FRB,FRC.
620 # The legacy assembler placed operands in syntax order.
621 "ffmadds": {"FRB": FMAOperandFRB
, "FRC": FMAOperandFRC
},
622 "ffmadds.": {"FRB": FMAOperandFRB
, "FRC": FMAOperandFRC
},
623 "fdmadds": {"FRB": FMAOperandFRB
, "FRC": FMAOperandFRC
},
624 "fdmadds.": {"FRB": FMAOperandFRB
, "FRC": FMAOperandFRC
},
627 "SVi": NonZeroOperand
,
628 "SVd": NonZeroOperand
,
629 "SVxd": NonZeroOperand
,
630 "SVyd": NonZeroOperand
,
631 "SVzd": NonZeroOperand
,
633 "D": SignedImmediateOperand
,
637 "SIM": SignedOperand
,
638 "SVD": SignedOperand
,
639 "SVDS": SignedOperand
,
640 "RSp": GPRPairOperand
,
641 "RTp": GPRPairOperand
,
642 "FRAp": FPRPairOperand
,
643 "FRBp": FPRPairOperand
,
644 "FRSp": FPRPairOperand
,
645 "FRTp": FPRPairOperand
,
647 custom_immediates
= {
653 for operand
in operands
:
657 (name
, value
) = operand
.split("=")
658 mapping
[name
] = (StaticOperand
, {
664 if name
.endswith(")"):
665 name
= name
.replace("(", " ").replace(")", "")
666 (imm_name
, _
, name
) = name
.partition(" ")
670 if imm_name
is not None:
671 imm_cls
= custom_immediates
.get(imm_name
, ImmediateOperand
)
673 if insn
in custom_insns
and name
in custom_insns
[insn
]:
674 cls
= custom_insns
[insn
][name
]
675 elif name
in custom_fields
:
676 cls
= custom_fields
[name
]
677 elif name
in _SVExtraReg
.__members
__:
678 reg
= _SVExtraReg
[name
]
679 if reg
in self
.__class
__.__GPR
_PAIRS
:
681 elif reg
in self
.__class
__.__FPR
_PAIRS
:
684 regtype
= _RegType
[name
]
685 if regtype
is _RegType
.GPR
:
687 elif regtype
is _RegType
.FPR
:
689 elif regtype
is _RegType
.CR_3BIT
:
691 elif regtype
is _RegType
.CR_5BIT
:
694 if imm_name
is not None:
695 mapping
[imm_name
] = (imm_cls
, {"name": imm_name
})
696 mapping
[name
] = (cls
, {"name": name
})
700 for (name
, (cls
, kwargs
)) in mapping
.items():
701 kwargs
= dict(kwargs
)
702 kwargs
["name"] = name
703 if issubclass(cls
, StaticOperand
):
704 static
.append((cls
, kwargs
))
705 elif issubclass(cls
, DynamicOperand
):
706 dynamic
.append((cls
, kwargs
))
708 raise ValueError(name
)
710 self
.__mapping
= mapping
711 self
.__static
= tuple(static
)
712 self
.__dynamic
= tuple(dynamic
)
714 return super().__init
__()
717 for (_
, items
) in self
.__mapping
.items():
718 (cls
, kwargs
) = items
722 return self
.__mapping
.__repr
__()
724 def __contains__(self
, key
):
725 return self
.__mapping
.__contains
__(key
)
727 def __getitem__(self
, key
):
728 return self
.__mapping
.__getitem
__(key
)
736 return self
.__dynamic
739 class Arguments(tuple):
740 def __new__(cls
, record
, arguments
, operands
):
741 operands
= iter(tuple(operands
))
742 arguments
= iter(tuple(arguments
))
747 operand
= next(operands
)
748 except StopIteration:
752 argument
= next(arguments
)
753 except StopIteration:
754 raise ValueError("operands count mismatch")
756 if isinstance(operand
, ImmediateOperand
):
757 argument
= argument
.replace("(", " ").replace(")", "")
758 (imm_argument
, _
, argument
) = argument
.partition(" ")
760 (imm_operand
, operand
) = (operand
, next(operands
))
761 except StopIteration:
762 raise ValueError("operands count mismatch")
763 items
.append((imm_argument
, imm_operand
))
764 items
.append((argument
, operand
))
768 except StopIteration:
771 raise ValueError("operands count mismatch")
773 return super().__new
__(cls
, items
)
777 def __init__(self
, iterable
):
778 self
.__pcode
= tuple(iterable
)
779 return super().__init
__()
782 yield from self
.__pcode
785 return self
.__pcode
.__repr
__()
788 @_dataclasses.dataclass(eq
=True, frozen
=True)
789 class MarkdownRecord
:
794 @_functools.total_ordering
795 @_dataclasses.dataclass(eq
=True, frozen
=True)
802 svp64
: SVP64Record
= None
804 def __lt__(self
, other
):
805 if not isinstance(other
, Record
):
806 return NotImplemented
807 lhs
= (min(self
.opcodes
), self
.name
)
808 rhs
= (min(other
.opcodes
), other
.name
)
813 return (self
.static_operands
+ self
.dynamic_operands
)
816 def static_operands(self
):
818 operands
.append(POStaticOperand(record
=self
, value
=self
.PO
))
820 operands
.append(XOStaticOperand(
822 value
=ppc
.opcode
.value
,
823 span
=self
.section
.bitsel
,
825 for (cls
, kwargs
) in self
.mdwn
.operands
.static
:
826 operands
.append(cls(record
=self
, **kwargs
))
827 return tuple(operands
)
830 def dynamic_operands(self
):
832 for (cls
, kwargs
) in self
.mdwn
.operands
.dynamic
:
833 operands
.append(cls(record
=self
, **kwargs
))
834 return tuple(operands
)
839 return int("".join(str(int(mapping
[bit
])) for bit
in sorted(mapping
)), 2)
841 def PO_XO(value
, mask
, opcode
, bits
):
844 for (src
, dst
) in enumerate(reversed(bits
)):
845 value
[dst
] = ((opcode
.value
& (1 << src
)) != 0)
846 mask
[dst
] = ((opcode
.mask
& (1 << src
)) != 0)
849 def PO(value
, mask
, opcode
, bits
):
850 return PO_XO(value
=value
, mask
=mask
, opcode
=opcode
, bits
=bits
)
852 def XO(value
, mask
, opcode
, bits
):
853 (value
, mask
) = PO_XO(value
=value
, mask
=mask
, opcode
=opcode
, bits
=bits
)
854 for (op_cls
, op_kwargs
) in self
.mdwn
.operands
.static
:
855 operand
= op_cls(record
=self
, **op_kwargs
)
856 for (src
, dst
) in enumerate(reversed(operand
.span
)):
857 value
[dst
] = ((operand
.value
& (1 << src
)) != 0)
862 value
= {bit
:False for bit
in range(32)}
863 mask
= {bit
:False for bit
in range(32)}
864 if self
.section
.opcode
is not None:
865 (value
, mask
) = PO(value
=value
, mask
=mask
,
866 opcode
=self
.section
.opcode
, bits
=range(0, 6))
868 pairs
.append(XO(value
=value
, mask
=mask
,
869 opcode
=ppc
.opcode
, bits
=self
.section
.bitsel
))
872 for (value
, mask
) in pairs
:
873 value
= Opcode
.Value(binary(value
))
874 mask
= Opcode
.Mask(binary(mask
))
875 result
.append(Opcode(value
=value
, mask
=mask
))
881 opcode
= self
.section
.opcode
883 opcode
= self
.ppc
[0].opcode
884 if isinstance(opcode
, PatternOpcode
):
885 value
= int(opcode
.value
)
886 bits
= opcode
.value
.bit_length()
887 return int(_SelectableInt(value
=value
, bits
=bits
)[0:6])
889 return int(opcode
.value
)
893 return tuple(ppc
.opcode
for ppc
in self
.ppc
)
895 def match(self
, key
):
896 for opcode
in self
.opcodes
:
897 if opcode
.match(key
):
904 return self
.svp64
.mode
924 if self
.svp64
is None:
930 return self
.ppc
.cr_in
934 return self
.ppc
.cr_in2
938 return self
.ppc
.cr_out
940 ptype
= property(lambda self
: self
.svp64
.ptype
)
941 etype
= property(lambda self
: self
.svp64
.etype
)
943 def extra_idx(self
, key
):
944 return self
.svp64
.extra_idx(key
)
946 extra_idx_in1
= property(lambda self
: self
.svp64
.extra_idx_in1
)
947 extra_idx_in2
= property(lambda self
: self
.svp64
.extra_idx_in2
)
948 extra_idx_in3
= property(lambda self
: self
.svp64
.extra_idx_in3
)
949 extra_idx_out
= property(lambda self
: self
.svp64
.extra_idx_out
)
950 extra_idx_out2
= property(lambda self
: self
.svp64
.extra_idx_out2
)
951 extra_idx_cr_in
= property(lambda self
: self
.svp64
.extra_idx_cr_in
)
952 extra_idx_cr_in2
= property(lambda self
: self
.svp64
.extra_idx_cr_in2
)
953 extra_idx_cr_out
= property(lambda self
: self
.svp64
.extra_idx_cr_out
)
955 def __contains__(self
, key
):
956 return self
.mdwn
.operands
.__contains
__(key
)
958 def __getitem__(self
, key
):
959 (cls
, kwargs
) = self
.mdwn
.operands
.__getitem
__(key
)
960 return cls(record
=self
, **kwargs
)
966 return self
["Rc"].value
970 def __init__(self
, record
, name
):
971 self
.__record
= record
975 yield ("record", self
.record
)
976 yield ("name", self
.__name
)
979 return f
"{self.__class__.__name__}({self.name})"
991 return self
.record
.fields
[self
.name
]
993 def assemble(self
, insn
):
994 raise NotImplementedError()
996 def disassemble(self
, insn
,
997 style
=Style
.NORMAL
, indent
=""):
998 raise NotImplementedError()
1001 class DynamicOperand(Operand
):
1002 def assemble(self
, insn
, value
):
1004 if isinstance(value
, str):
1005 value
= int(value
, 0)
1007 raise ValueError("signed operands not allowed")
1010 def disassemble(self
, insn
,
1011 style
=Style
.NORMAL
, indent
=""):
1015 if style
>= Style
.VERBOSE
:
1016 span
= map(str, span
)
1017 yield f
"{indent}{self.name}"
1018 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
1019 yield f
"{indent}{indent}{', '.join(span)}"
1021 yield str(int(value
))
1024 class SignedOperand(DynamicOperand
):
1025 def assemble(self
, insn
, value
):
1026 if isinstance(value
, str):
1027 value
= int(value
, 0)
1028 return super().assemble(value
=value
, insn
=insn
)
1030 def assemble(self
, insn
, value
):
1032 if isinstance(value
, str):
1033 value
= int(value
, 0)
1036 def disassemble(self
, insn
,
1037 style
=Style
.NORMAL
, indent
=""):
1039 value
= insn
[span
].to_signed_int()
1040 sign
= "-" if (value
< 0) else ""
1043 if style
>= Style
.VERBOSE
:
1044 span
= map(str, span
)
1045 yield f
"{indent}{self.name}"
1046 yield f
"{indent}{indent}{sign}{value}"
1047 yield f
"{indent}{indent}{', '.join(span)}"
1049 yield f
"{sign}{value}"
1052 class StaticOperand(Operand
):
1053 def __init__(self
, record
, name
, value
):
1054 self
.__value
= value
1055 return super().__init
__(record
=record
, name
=name
)
1058 yield ("value", self
.__value
)
1059 yield from super().__iter
__()
1062 return f
"{self.__class__.__name__}({self.name}, value={self.value})"
1068 def assemble(self
, insn
):
1069 insn
[self
.span
] = self
.value
1071 def disassemble(self
, insn
,
1072 style
=Style
.NORMAL
, indent
=""):
1076 if style
>= Style
.VERBOSE
:
1077 span
= map(str, span
)
1078 yield f
"{indent}{self.name}"
1079 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
1080 yield f
"{indent}{indent}{', '.join(span)}"
1082 yield str(int(value
))
1085 class SpanStaticOperand(StaticOperand
):
1086 def __init__(self
, record
, name
, value
, span
):
1087 self
.__span
= tuple(span
)
1088 return super().__init
__(record
=record
, name
=name
, value
=value
)
1091 yield ("span", self
.__span
)
1092 yield from super().__iter
__()
1099 class POStaticOperand(SpanStaticOperand
):
1100 def __init__(self
, record
, value
):
1101 return super().__init
__(record
=record
, name
="PO", value
=value
, span
=range(0, 6))
1104 for (key
, value
) in super().__iter
__():
1105 if key
not in {"name", "span"}:
1109 class XOStaticOperand(SpanStaticOperand
):
1110 def __init__(self
, record
, value
, span
):
1111 bits
= record
.section
.bitsel
1112 value
= _SelectableInt(value
=value
, bits
=len(bits
))
1113 span
= dict(zip(bits
, range(len(bits
))))
1114 span_rev
= {value
:key
for (key
, value
) in span
.items()}
1116 # This part is tricky: we cannot use record.operands,
1117 # as this code is called by record.static_operands method.
1118 for (cls
, kwargs
) in record
.mdwn
.operands
:
1119 operand
= cls(record
=record
, **kwargs
)
1120 for idx
in operand
.span
:
1121 rev
= span
.pop(idx
, None)
1123 span_rev
.pop(rev
, None)
1125 value
= int(_selectconcat(*(value
[bit
] for bit
in span
.values())))
1126 span
= tuple(span
.keys())
1128 return super().__init
__(record
=record
, name
="XO", value
=value
, span
=span
)
1131 for (key
, value
) in super().__iter
__():
1132 if key
not in {"name"}:
1136 class ImmediateOperand(DynamicOperand
):
1140 class SignedImmediateOperand(SignedOperand
, ImmediateOperand
):
1144 class NonZeroOperand(DynamicOperand
):
1145 def assemble(self
, insn
, value
):
1146 if isinstance(value
, str):
1147 value
= int(value
, 0)
1148 if not isinstance(value
, int):
1149 raise ValueError("non-integer operand")
1151 return super().assemble(value
=value
, insn
=insn
)
1153 def disassemble(self
, insn
,
1154 style
=Style
.NORMAL
, indent
=""):
1158 if style
>= Style
.VERBOSE
:
1159 span
= map(str, span
)
1160 yield f
"{indent}{self.name}"
1161 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
1162 yield f
"{indent}{indent}{', '.join(span)}"
1164 yield str(int(value
) + 1)
1167 class ExtendableOperand(DynamicOperand
):
1168 def sv_spec_enter(self
, value
, span
):
1169 return (value
, span
)
1171 def sv_spec(self
, insn
):
1175 span
= tuple(map(str, span
))
1177 if isinstance(insn
, SVP64Instruction
):
1178 (origin_value
, origin_span
) = (value
, span
)
1179 (value
, span
) = self
.sv_spec_enter(value
=value
, span
=span
)
1181 for extra_idx
in self
.extra_idx
:
1182 if self
.record
.etype
is _SVEType
.EXTRA3
:
1183 spec
= insn
.prefix
.rm
.extra3
[extra_idx
]
1184 elif self
.record
.etype
is _SVEType
.EXTRA2
:
1185 spec
= insn
.prefix
.rm
.extra2
[extra_idx
]
1187 raise ValueError(self
.record
.etype
)
1190 vector
= bool(spec
[0])
1191 spec_span
= spec
.__class
__
1192 if self
.record
.etype
is _SVEType
.EXTRA3
:
1193 spec_span
= tuple(map(str, spec_span
[1, 2]))
1195 elif self
.record
.etype
is _SVEType
.EXTRA2
:
1196 spec_span
= tuple(map(str, spec_span
[1,]))
1197 spec
= _SelectableInt(value
=spec
[1].value
, bits
=2)
1200 spec_span
= (spec_span
+ ("{0}",))
1202 spec_span
= (("{0}",) + spec_span
)
1204 raise ValueError(self
.record
.etype
)
1206 vector_shift
= (2 + (5 - value
.bits
))
1207 scalar_shift
= value
.bits
1208 spec_shift
= (5 - value
.bits
)
1210 bits
= (len(span
) + len(spec_span
))
1211 value
= _SelectableInt(value
=value
.value
, bits
=bits
)
1212 spec
= _SelectableInt(value
=spec
.value
, bits
=bits
)
1214 value
= ((value
<< vector_shift
) |
(spec
<< spec_shift
))
1215 span
= (span
+ spec_span
+ ((spec_shift
* ("{0}",))))
1217 value
= ((spec
<< scalar_shift
) | value
)
1218 span
= ((spec_shift
* ("{0}",)) + spec_span
+ span
)
1220 (value
, span
) = self
.sv_spec_leave(value
=value
, span
=span
,
1221 origin_value
=origin_value
, origin_span
=origin_span
)
1223 return (vector
, value
, span
)
1225 def sv_spec_leave(self
, value
, span
, origin_value
, origin_span
):
1226 return (value
, span
)
1229 def extra_reg(self
):
1230 return _SVExtraReg(self
.name
)
1233 def extra_idx(self
):
1235 _SVExtraReg
.RSp
: _SVExtraReg
.RS
,
1236 _SVExtraReg
.RTp
: _SVExtraReg
.RT
,
1237 _SVExtraReg
.FRAp
: _SVExtraReg
.FRA
,
1238 _SVExtraReg
.FRBp
: _SVExtraReg
.FRB
,
1239 _SVExtraReg
.FRSp
: _SVExtraReg
.FRS
,
1240 _SVExtraReg
.FRTp
: _SVExtraReg
.FRT
,
1243 for key
in frozenset({
1244 "in1", "in2", "in3", "cr_in", "cr_in2",
1245 "out", "out2", "cr_out",
1247 extra_reg
= self
.record
.svp64
.extra_reg(key
=key
)
1248 this_extra_reg
= pairs
.get(self
.extra_reg
, self
.extra_reg
)
1249 that_extra_reg
= pairs
.get(extra_reg
, extra_reg
)
1250 if this_extra_reg
is that_extra_reg
:
1251 yield from tuple(self
.record
.extra_idx(key
=key
))
1253 def remap(self
, value
, vector
):
1254 raise NotImplementedError()
1256 def assemble(self
, value
, insn
, prefix
):
1259 if isinstance(value
, str):
1260 value
= value
.lower()
1261 if value
.startswith("%"):
1263 if value
.startswith("*"):
1264 if not isinstance(insn
, SVP64Instruction
):
1265 raise ValueError(value
)
1268 if value
.startswith(prefix
):
1269 value
= value
[len(prefix
):]
1270 value
= int(value
, 0)
1272 if isinstance(insn
, SVP64Instruction
):
1273 (value
, extra
) = self
.remap(value
=value
, vector
=vector
)
1275 for extra_idx
in self
.extra_idx
:
1276 if self
.record
.etype
is _SVEType
.EXTRA3
:
1277 insn
.prefix
.rm
.extra3
[extra_idx
] = extra
1278 elif self
.record
.etype
is _SVEType
.EXTRA2
:
1279 insn
.prefix
.rm
.extra2
[extra_idx
] = extra
1281 raise ValueError(self
.record
.etype
)
1283 return super().assemble(value
=value
, insn
=insn
)
1285 def disassemble(self
, insn
,
1286 style
=Style
.NORMAL
, prefix
="", indent
=""):
1287 (vector
, value
, span
) = self
.sv_spec(insn
=insn
)
1289 if style
>= Style
.VERBOSE
:
1290 mode
= "vector" if vector
else "scalar"
1291 yield f
"{indent}{self.name} ({mode})"
1292 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
1293 yield f
"{indent}{indent}{', '.join(span)}"
1294 if isinstance(insn
, SVP64Instruction
):
1295 extra_idx
= self
.extra_idx
1296 if self
.record
.etype
is _SVEType
.NONE
:
1297 yield f
"{indent}{indent}extra[none]"
1299 etype
= repr(self
.record
.etype
).lower()
1300 yield f
"{indent}{indent}{etype}{extra_idx!r}"
1302 vector
= "*" if vector
else ""
1303 yield f
"{vector}{prefix}{int(value)}"
1306 class SimpleRegisterOperand(ExtendableOperand
):
1307 def remap(self
, value
, vector
):
1309 extra
= (value
& 0b11)
1310 value
= (value
>> 2)
1312 extra
= (value
>> 5)
1313 value
= (value
& 0b11111)
1315 # now sanity-check. EXTRA3 is ok, EXTRA2 has limits
1316 # (and shrink to a single bit if ok)
1317 if self
.record
.etype
is _SVEType
.EXTRA2
:
1319 # range is r0-r127 in increments of 2 (r0 r2 ... r126)
1320 assert (extra
& 0b01) == 0, \
1321 ("vector field %s cannot fit into EXTRA2" % value
)
1322 extra
= (0b10 |
(extra
>> 1))
1324 # range is r0-r63 in increments of 1
1325 assert (extra
>> 1) == 0, \
1326 ("scalar GPR %d cannot fit into EXTRA2" % value
)
1328 elif self
.record
.etype
is _SVEType
.EXTRA3
:
1330 # EXTRA3 vector bit needs marking
1333 raise ValueError(self
.record
.etype
)
1335 return (value
, extra
)
1338 class GPROperand(SimpleRegisterOperand
):
1339 def assemble(self
, insn
, value
):
1340 return super().assemble(value
=value
, insn
=insn
, prefix
="r")
1342 def disassemble(self
, insn
,
1343 style
=Style
.NORMAL
, indent
=""):
1344 prefix
= "" if (style
<= Style
.SHORT
) else "r"
1345 yield from super().disassemble(prefix
=prefix
, insn
=insn
,
1346 style
=style
, indent
=indent
)
1349 class GPRPairOperand(GPROperand
):
1353 class FPROperand(SimpleRegisterOperand
):
1354 def assemble(self
, insn
, value
):
1355 return super().assemble(value
=value
, insn
=insn
, prefix
="f")
1357 def disassemble(self
, insn
,
1358 style
=Style
.NORMAL
, indent
=""):
1359 prefix
= "" if (style
<= Style
.SHORT
) else "f"
1360 yield from super().disassemble(prefix
=prefix
, insn
=insn
,
1361 style
=style
, indent
=indent
)
1364 class RedirectedOperand(DynamicOperand
):
1365 def __init__(self
, record
, name
, target
):
1366 self
.__target
= target
1367 return super().__init
__(record
=record
, name
=name
)
1371 print(f
"{self.record.name}: {self.name} => {self.__target}", file=_sys
.stderr
)
1372 return self
.record
.fields
[self
.__target
]
1375 class FMAOperandFRB(RedirectedOperand
, FPROperand
):
1376 def __init__(self
, record
, name
):
1377 return super().__init
__(record
=record
, name
=name
, target
="FRC")
1380 class FMAOperandFRC(RedirectedOperand
, FPROperand
):
1381 def __init__(self
, record
, name
):
1382 return super().__init
__(record
=record
, name
=name
, target
="FRB")
1385 class FPRPairOperand(FPROperand
):
1389 class ConditionRegisterFieldOperand(ExtendableOperand
):
1390 def pattern(name_pattern
):
1391 (name
, pattern
) = name_pattern
1392 return (name
, _re
.compile(f
"^{pattern}$", _re
.S
))
1401 CR
= r
"(?:CR|cr)([0-9]+)"
1403 BIT
= rf
"({'|'.join(CONDS.keys())})"
1404 LBIT
= fr
"{BIT}\s*\+\s*" # BIT+
1405 RBIT
= fr
"\s*\+\s*{BIT}" # +BIT
1406 CRN
= fr
"{CR}\s*\*\s*{N}" # CR*N
1407 NCR
= fr
"{N}\s*\*\s*{CR}" # N*CR
1408 XCR
= fr
"{CR}\.{BIT}"
1409 PATTERNS
= tuple(map(pattern
, (
1414 ("BIT+CR", (LBIT
+ CR
)),
1415 ("CR+BIT", (CR
+ RBIT
)),
1416 ("BIT+CR*N", (LBIT
+ CRN
)),
1417 ("CR*N+BIT", (CRN
+ RBIT
)),
1418 ("BIT+N*CR", (LBIT
+ NCR
)),
1419 ("N*CR+BIT", (NCR
+ RBIT
)),
1422 def remap(self
, value
, vector
, regtype
):
1423 if regtype
is _RegType
.CR_5BIT
:
1424 subvalue
= (value
& 0b11)
1428 extra
= (value
& 0b1111)
1431 extra
= (value
>> 3)
1434 if self
.record
.etype
is _SVEType
.EXTRA2
:
1436 assert (extra
& 0b111) == 0, \
1437 "vector CR cannot fit into EXTRA2"
1438 extra
= (0b10 |
(extra
>> 3))
1440 assert (extra
>> 1) == 0, \
1441 "scalar CR cannot fit into EXTRA2"
1443 elif self
.record
.etype
is _SVEType
.EXTRA3
:
1445 assert (extra
& 0b11) == 0, \
1446 "vector CR cannot fit into EXTRA3"
1447 extra
= (0b100 |
(extra
>> 2))
1449 assert (extra
>> 2) == 0, \
1450 "scalar CR cannot fit into EXTRA3"
1453 if regtype
is _RegType
.CR_5BIT
:
1454 value
= ((value
<< 2) | subvalue
)
1456 return (value
, extra
)
1458 def assemble(self
, insn
, value
):
1459 if isinstance(value
, str):
1462 if value
.startswith("*"):
1463 if not isinstance(insn
, SVP64Instruction
):
1464 raise ValueError(value
)
1468 for (name
, pattern
) in reversed(self
.__class
__.PATTERNS
):
1469 match
= pattern
.match(value
)
1470 if match
is not None:
1471 keys
= name
.replace("+", "_").replace("*", "_").split("_")
1472 values
= match
.groups()
1473 match
= dict(zip(keys
, values
))
1474 CR
= int(match
["CR"])
1478 N
= int(match
.get("N", "1"))
1479 BIT
= self
.__class
__.CONDS
[match
.get("BIT", "lt")]
1480 value
= ((CR
* N
) + BIT
)
1487 return super().assemble(value
=value
, insn
=insn
, prefix
="cr")
1489 def disassemble(self
, insn
,
1490 style
=Style
.NORMAL
, prefix
="", indent
=""):
1491 (vector
, value
, span
) = self
.sv_spec(insn
=insn
)
1493 if style
>= Style
.VERBOSE
:
1494 mode
= "vector" if vector
else "scalar"
1495 yield f
"{indent}{self.name} ({mode})"
1496 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
1497 yield f
"{indent}{indent}{', '.join(span)}"
1498 if isinstance(insn
, SVP64Instruction
):
1499 extra_idx
= self
.extra_idx
1500 if self
.record
.etype
is _SVEType
.NONE
:
1501 yield f
"{indent}{indent}extra[none]"
1503 etype
= repr(self
.record
.etype
).lower()
1504 yield f
"{indent}{indent}{etype}{extra_idx!r}"
1506 vector
= "*" if vector
else ""
1507 CR
= int(value
>> 2)
1509 cond
= ("lt", "gt", "eq", "so")[CC
]
1510 if style
>= Style
.NORMAL
:
1512 if isinstance(insn
, SVP64Instruction
):
1513 yield f
"{vector}cr{CR}.{cond}"
1515 yield f
"4*cr{CR}+{cond}"
1519 yield f
"{vector}{prefix}{int(value)}"
1522 class CR3Operand(ConditionRegisterFieldOperand
):
1523 def remap(self
, value
, vector
):
1524 return super().remap(value
=value
, vector
=vector
,
1525 regtype
=_RegType
.CR_3BIT
)
1528 class CR5Operand(ConditionRegisterFieldOperand
):
1529 def remap(self
, value
, vector
):
1530 return super().remap(value
=value
, vector
=vector
,
1531 regtype
=_RegType
.CR_5BIT
)
1533 def sv_spec_enter(self
, value
, span
):
1534 value
= _SelectableInt(value
=(value
.value
>> 2), bits
=3)
1535 return (value
, span
)
1537 def sv_spec_leave(self
, value
, span
, origin_value
, origin_span
):
1538 value
= _selectconcat(value
, origin_value
[3:5])
1540 return (value
, span
)
1543 class EXTSOperand(SignedOperand
):
1544 field
: str # real name to report
1545 nz
: int = 0 # number of zeros
1546 fmt
: str = "d" # integer formatter
1548 def __init__(self
, record
, name
, field
, nz
=0, fmt
="d"):
1549 self
.__field
= field
1552 return super().__init
__(record
=record
, name
=name
)
1568 return self
.record
.fields
[self
.field
]
1570 def assemble(self
, insn
, value
):
1572 if isinstance(value
, str):
1573 value
= int(value
, 0)
1574 insn
[span
] = (value
>> self
.nz
)
1576 def disassemble(self
, insn
,
1577 style
=Style
.NORMAL
, indent
=""):
1579 value
= insn
[span
].to_signed_int()
1580 sign
= "-" if (value
< 0) else ""
1581 value
= (abs(value
) << self
.nz
)
1583 if style
>= Style
.VERBOSE
:
1584 span
= (tuple(map(str, span
)) + (("{0}",) * self
.nz
))
1585 zeros
= ("0" * self
.nz
)
1586 hint
= f
"{self.name} = EXTS({self.field} || {zeros})"
1587 yield f
"{indent * 1}{hint}"
1588 yield f
"{indent * 2}{self.field}"
1589 yield f
"{indent * 3}{sign}{value:{self.fmt}}"
1590 yield f
"{indent * 3}{', '.join(span)}"
1592 yield f
"{sign}{value:{self.fmt}}"
1595 class TargetAddrOperand(EXTSOperand
):
1596 def __init__(self
, record
, name
, field
):
1597 return super().__init
__(record
=record
, name
=name
, field
=field
, nz
=2, fmt
="#x")
1600 class TargetAddrOperandLI(TargetAddrOperand
):
1601 def __init__(self
, record
, name
):
1602 return super().__init
__(record
=record
, name
=name
, field
="LI")
1605 class TargetAddrOperandBD(TargetAddrOperand
):
1606 def __init__(self
, record
, name
):
1607 return super().__init
__(record
=record
, name
=name
, field
="BD")
1610 class EXTSOperandDS(EXTSOperand
, ImmediateOperand
):
1611 def __init__(self
, record
, name
):
1612 return super().__init
__(record
=record
, name
=name
, field
="DS", nz
=2)
1615 class EXTSOperandDQ(EXTSOperand
, ImmediateOperand
):
1616 def __init__(self
, record
, name
):
1617 return super().__init
__(record
=record
, name
=name
, field
="DQ", nz
=4)
1620 class DOperandDX(SignedOperand
):
1623 cls
= lambda name
: DynamicOperand(record
=self
.record
, name
=name
)
1624 operands
= map(cls
, ("d0", "d1", "d2"))
1625 spans
= map(lambda operand
: operand
.span
, operands
)
1626 return sum(spans
, tuple())
1628 def disassemble(self
, insn
,
1629 style
=Style
.NORMAL
, indent
=""):
1631 value
= insn
[span
].to_signed_int()
1632 sign
= "-" if (value
< 0) else ""
1635 if style
>= Style
.VERBOSE
:
1642 for (subname
, subspan
) in mapping
.items():
1643 operand
= DynamicOperand(name
=subname
)
1645 span
= map(str, span
)
1646 yield f
"{indent}{indent}{operand.name} = D{subspan}"
1647 yield f
"{indent}{indent}{indent}{sign}{value}"
1648 yield f
"{indent}{indent}{indent}{', '.join(span)}"
1650 yield f
"{sign}{value}"
1653 class Instruction(_Mapping
):
1655 def integer(cls
, value
=0, bits
=None, byteorder
="little"):
1656 if isinstance(value
, (int, bytes
)) and not isinstance(bits
, int):
1657 raise ValueError(bits
)
1659 if isinstance(value
, bytes
):
1660 if ((len(value
) * 8) != bits
):
1661 raise ValueError(f
"bit length mismatch")
1662 value
= int.from_bytes(value
, byteorder
=byteorder
)
1664 if isinstance(value
, int):
1665 value
= _SelectableInt(value
=value
, bits
=bits
)
1666 elif isinstance(value
, Instruction
):
1667 value
= value
.storage
1669 if not isinstance(value
, _SelectableInt
):
1670 raise ValueError(value
)
1673 if len(value
) != bits
:
1674 raise ValueError(value
)
1676 value
= _SelectableInt(value
=value
, bits
=bits
)
1678 return cls(storage
=value
)
1681 return hash(int(self
))
1683 def __getitem__(self
, key
):
1684 return self
.storage
.__getitem
__(key
)
1686 def __setitem__(self
, key
, value
):
1687 return self
.storage
.__setitem
__(key
, value
)
1689 def bytes(self
, byteorder
="little"):
1690 nr_bytes
= (len(self
.__class
__) // 8)
1691 return int(self
).to_bytes(nr_bytes
, byteorder
=byteorder
)
1694 def record(cls
, db
, entry
):
1697 raise KeyError(entry
)
1701 def operands(cls
, record
):
1702 yield from record
.operands
1705 def static_operands(cls
, record
):
1706 return filter(lambda operand
: isinstance(operand
, StaticOperand
),
1707 cls
.operands(record
=record
))
1710 def dynamic_operands(cls
, record
):
1711 return filter(lambda operand
: isinstance(operand
, DynamicOperand
),
1712 cls
.operands(record
=record
))
1714 def spec(self
, record
, prefix
):
1715 dynamic_operands
= tuple(map(_operator
.itemgetter(0),
1716 self
.spec_dynamic_operands(record
=record
)))
1718 static_operands
= []
1719 for (name
, value
) in self
.spec_static_operands(record
=record
):
1720 static_operands
.append(f
"{name}={value}")
1723 if dynamic_operands
:
1725 operands
+= ",".join(dynamic_operands
)
1728 operands
+= " ".join(static_operands
)
1730 return f
"{prefix}{record.name}{operands}"
1732 def spec_static_operands(self
, record
):
1733 for operand
in self
.static_operands(record
=record
):
1734 if not isinstance(operand
, (POStaticOperand
, XOStaticOperand
)):
1735 yield (operand
.name
, operand
.value
)
1737 def spec_dynamic_operands(self
, record
, style
=Style
.NORMAL
):
1741 for operand
in self
.dynamic_operands(record
=record
):
1743 value
= " ".join(operand
.disassemble(insn
=self
,
1744 style
=min(style
, Style
.NORMAL
)))
1746 name
= f
"{imm_name}({name})"
1747 value
= f
"{imm_value}({value})"
1749 if isinstance(operand
, ImmediateOperand
):
1757 def assemble(cls
, record
, arguments
=None):
1758 if arguments
is None:
1761 insn
= cls
.integer(value
=0)
1763 for operand
in cls
.static_operands(record
=record
):
1764 operand
.assemble(insn
=insn
)
1766 arguments
= Arguments(record
=record
,
1767 arguments
=arguments
, operands
=cls
.dynamic_operands(record
=record
))
1768 for (value
, operand
) in arguments
:
1769 operand
.assemble(insn
=insn
, value
=value
)
1773 def disassemble(self
, record
,
1775 style
=Style
.NORMAL
):
1776 raise NotImplementedError()
1779 class WordInstruction(Instruction
):
1780 _
: _Field
= range(0, 32)
1781 PO
: _Field
= range(0, 6)
1784 def integer(cls
, value
, byteorder
="little"):
1785 return super().integer(bits
=32, value
=value
, byteorder
=byteorder
)
1790 for idx
in range(32):
1791 bit
= int(self
[idx
])
1793 return "".join(map(str, bits
))
1795 def disassemble(self
, record
,
1797 style
=Style
.NORMAL
):
1798 if style
<= Style
.SHORT
:
1801 blob
= self
.bytes(byteorder
=byteorder
)
1802 blob
= " ".join(map(lambda byte
: f
"{byte:02x}", blob
))
1806 yield f
"{blob}.long 0x{int(self):08x}"
1810 if style
is Style
.LEGACY
:
1812 for operand
in self
.dynamic_operands(record
=record
):
1813 if isinstance(operand
, (GPRPairOperand
, FPRPairOperand
)):
1816 if style
is Style
.LEGACY
and (paired
or record
.ppc
.unofficial
):
1817 yield f
"{blob}.long 0x{int(self):08x}"
1819 operands
= tuple(map(_operator
.itemgetter(1),
1820 self
.spec_dynamic_operands(record
=record
, style
=style
)))
1822 operands
= ",".join(operands
)
1823 yield f
"{blob}{record.name} {operands}"
1825 yield f
"{blob}{record.name}"
1827 if style
>= Style
.VERBOSE
:
1829 binary
= self
.binary
1830 spec
= self
.spec(record
=record
, prefix
="")
1831 yield f
"{indent}spec"
1832 yield f
"{indent}{indent}{spec}"
1833 yield f
"{indent}pcode"
1834 for stmt
in record
.mdwn
.pcode
:
1835 yield f
"{indent}{indent}{stmt}"
1836 yield f
"{indent}binary"
1837 yield f
"{indent}{indent}[0:8] {binary[0:8]}"
1838 yield f
"{indent}{indent}[8:16] {binary[8:16]}"
1839 yield f
"{indent}{indent}[16:24] {binary[16:24]}"
1840 yield f
"{indent}{indent}[24:32] {binary[24:32]}"
1841 yield f
"{indent}opcodes"
1842 for opcode
in record
.opcodes
:
1843 yield f
"{indent}{indent}{opcode!r}"
1844 for operand
in self
.operands(record
=record
):
1845 yield from operand
.disassemble(insn
=self
,
1846 style
=style
, indent
=indent
)
1850 class PrefixedInstruction(Instruction
):
1851 class Prefix(WordInstruction
.remap(range(0, 32))):
1854 class Suffix(WordInstruction
.remap(range(32, 64))):
1857 _
: _Field
= range(64)
1863 def integer(cls
, value
, byteorder
="little"):
1864 return super().integer(bits
=64, value
=value
, byteorder
=byteorder
)
1867 def pair(cls
, prefix
=0, suffix
=0, byteorder
="little"):
1868 def transform(value
):
1869 return WordInstruction
.integer(value
=value
,
1870 byteorder
=byteorder
)[0:32]
1872 (prefix
, suffix
) = map(transform
, (prefix
, suffix
))
1873 value
= _selectconcat(prefix
, suffix
)
1875 return super().integer(bits
=64, value
=value
)
1878 class Mode(_Mapping
):
1879 _
: _Field
= range(0, 5)
1880 sel
: _Field
= (0, 1)
1883 class Extra(_Mapping
):
1884 _
: _Field
= range(0, 9)
1887 class Extra2(Extra
):
1888 idx0
: _Field
= range(0, 2)
1889 idx1
: _Field
= range(2, 4)
1890 idx2
: _Field
= range(4, 6)
1891 idx3
: _Field
= range(6, 8)
1893 def __getitem__(self
, key
):
1899 _SVExtra
.Idx0
: self
.idx0
,
1900 _SVExtra
.Idx1
: self
.idx1
,
1901 _SVExtra
.Idx2
: self
.idx2
,
1902 _SVExtra
.Idx3
: self
.idx3
,
1905 def __setitem__(self
, key
, value
):
1906 self
[key
].assign(value
)
1909 class Extra3(Extra
):
1910 idx0
: _Field
= range(0, 3)
1911 idx1
: _Field
= range(3, 6)
1912 idx2
: _Field
= range(6, 9)
1914 def __getitem__(self
, key
):
1919 _SVExtra
.Idx0
: self
.idx0
,
1920 _SVExtra
.Idx1
: self
.idx1
,
1921 _SVExtra
.Idx2
: self
.idx2
,
1924 def __setitem__(self
, key
, value
):
1925 self
[key
].assign(value
)
1928 class BaseRM(_Mapping
):
1929 _
: _Field
= range(24)
1930 mmode
: _Field
= (0,)
1931 mask
: _Field
= range(1, 4)
1932 elwidth
: _Field
= range(4, 6)
1933 ewsrc
: _Field
= range(6, 8)
1934 subvl
: _Field
= range(8, 10)
1935 mode
: Mode
.remap(range(19, 24))
1936 smask
: _Field
= range(16, 19)
1937 extra
: Extra
.remap(range(10, 19))
1938 extra2
: Extra2
.remap(range(10, 19))
1939 extra3
: Extra3
.remap(range(10, 19))
1941 def specifiers(self
, record
):
1942 subvl
= int(self
.subvl
)
1950 def disassemble(self
, style
=Style
.NORMAL
):
1951 if style
>= Style
.VERBOSE
:
1953 for (name
, span
) in self
.traverse(path
="RM"):
1954 value
= self
.storage
[span
]
1956 yield f
"{indent}{int(value):0{value.bits}b}"
1957 yield f
"{indent}{', '.join(map(str, span))}"
1960 class FFPRRc1BaseRM(BaseRM
):
1961 def specifiers(self
, record
, mode
):
1962 inv
= _SelectableInt(value
=int(self
.inv
), bits
=1)
1963 CR
= _SelectableInt(value
=int(self
.CR
), bits
=2)
1964 mask
= int(_selectconcat(CR
, inv
))
1965 predicate
= PredicateBaseRM
.predicate(True, mask
)
1966 yield f
"{mode}={predicate}"
1968 yield from super().specifiers(record
=record
)
1971 class FFPRRc0BaseRM(BaseRM
):
1972 def specifiers(self
, record
, mode
):
1974 inv
= "~" if self
.inv
else ""
1975 yield f
"{mode}={inv}RC1"
1977 yield from super().specifiers(record
=record
)
1980 class SatBaseRM(BaseRM
):
1981 def specifiers(self
, record
):
1987 yield from super().specifiers(record
=record
)
1990 class ZZBaseRM(BaseRM
):
1991 def specifiers(self
, record
):
1995 yield from super().specifiers(record
=record
)
1998 class ZZCombinedBaseRM(BaseRM
):
1999 def specifiers(self
, record
):
2000 if self
.sz
and self
.dz
:
2007 yield from super().specifiers(record
=record
)
2010 class DZBaseRM(BaseRM
):
2011 def specifiers(self
, record
):
2015 yield from super().specifiers(record
=record
)
2018 class SZBaseRM(BaseRM
):
2019 def specifiers(self
, record
):
2023 yield from super().specifiers(record
=record
)
2026 class MRBaseRM(BaseRM
):
2027 def specifiers(self
, record
):
2033 yield from super().specifiers(record
=record
)
2036 class ElsBaseRM(BaseRM
):
2037 def specifiers(self
, record
):
2041 yield from super().specifiers(record
=record
)
2044 class WidthBaseRM(BaseRM
):
2046 def width(FP
, width
):
2055 width
= ("fp" + width
)
2058 def specifiers(self
, record
):
2059 # elwidths: use "w=" if same otherwise dw/sw
2060 # FIXME this should consider FP instructions
2062 dw
= WidthBaseRM
.width(FP
, int(self
.elwidth
))
2063 sw
= WidthBaseRM
.width(FP
, int(self
.ewsrc
))
2072 yield from super().specifiers(record
=record
)
2075 class PredicateBaseRM(BaseRM
):
2077 def predicate(CR
, mask
):
2080 (False, 0b001): "1<<r3",
2081 (False, 0b010): "r3",
2082 (False, 0b011): "~r3",
2083 (False, 0b100): "r10",
2084 (False, 0b101): "~r10",
2085 (False, 0b110): "r30",
2086 (False, 0b111): "~r30",
2088 (True, 0b000): "lt",
2089 (True, 0b001): "ge",
2090 (True, 0b010): "gt",
2091 (True, 0b011): "le",
2092 (True, 0b100): "eq",
2093 (True, 0b101): "ne",
2094 (True, 0b110): "so",
2095 (True, 0b111): "ns",
2098 def specifiers(self
, record
):
2099 # predication - single and twin
2100 # use "m=" if same otherwise sm/dm
2101 CR
= (int(self
.mmode
) == 1)
2102 mask
= int(self
.mask
)
2103 sm
= dm
= PredicateBaseRM
.predicate(CR
, mask
)
2104 if record
.svp64
.ptype
is _SVPType
.P2
:
2105 smask
= int(self
.smask
)
2106 sm
= PredicateBaseRM
.predicate(CR
, smask
)
2115 yield from super().specifiers(record
=record
)
2118 class PredicateWidthBaseRM(WidthBaseRM
, PredicateBaseRM
):
2122 class SEABaseRM(BaseRM
):
2123 def specifiers(self
, record
):
2127 yield from super().specifiers(record
=record
)
2130 class VLiBaseRM(BaseRM
):
2131 def specifiers(self
, record
):
2135 yield from super().specifiers(record
=record
)
2138 class NormalBaseRM(PredicateWidthBaseRM
):
2141 https://libre-soc.org/openpower/sv/normal/
2146 class NormalSimpleRM(ZZCombinedBaseRM
, NormalBaseRM
):
2147 """normal: simple mode"""
2151 def specifiers(self
, record
):
2152 yield from super().specifiers(record
=record
)
2155 class NormalMRRM(MRBaseRM
, NormalBaseRM
):
2156 """normal: scalar reduce mode (mapreduce), SUBVL=1"""
2160 class NormalFFRc1RM(FFPRRc1BaseRM
, NormalBaseRM
):
2161 """normal: Rc=1: ffirst CR sel"""
2163 CR
: BaseRM
.mode
[3, 4]
2165 def specifiers(self
, record
):
2166 yield from super().specifiers(record
=record
, mode
="ff")
2169 class NormalFFRc0RM(FFPRRc0BaseRM
, VLiBaseRM
, NormalBaseRM
):
2170 """normal: Rc=0: ffirst z/nonz"""
2175 def specifiers(self
, record
):
2176 yield from super().specifiers(record
=record
, mode
="ff")
2179 class NormalSatRM(SatBaseRM
, ZZCombinedBaseRM
, NormalBaseRM
):
2180 """normal: sat mode: N=0/1 u/s, SUBVL=1"""
2186 class NormalPRRc1RM(FFPRRc1BaseRM
, NormalBaseRM
):
2187 """normal: Rc=1: pred-result CR sel"""
2189 CR
: BaseRM
.mode
[3, 4]
2191 def specifiers(self
, record
):
2192 yield from super().specifiers(record
=record
, mode
="pr")
2195 class NormalPRRc0RM(FFPRRc0BaseRM
, ZZBaseRM
, NormalBaseRM
):
2196 """normal: Rc=0: pred-result z/nonz"""
2203 def specifiers(self
, record
):
2204 yield from super().specifiers(record
=record
, mode
="pr")
2207 class NormalRM(NormalBaseRM
):
2208 simple
: NormalSimpleRM
2210 ffrc1
: NormalFFRc1RM
2211 ffrc0
: NormalFFRc0RM
2213 prrc1
: NormalPRRc1RM
2214 prrc0
: NormalPRRc0RM
2217 class LDSTImmBaseRM(PredicateWidthBaseRM
):
2219 LD/ST Immediate mode
2220 https://libre-soc.org/openpower/sv/ldst/
2225 class LDSTImmSimpleRM(ElsBaseRM
, ZZBaseRM
, LDSTImmBaseRM
):
2226 """ld/st immediate: simple mode"""
2233 class LDSTImmPostRM(LDSTImmBaseRM
):
2234 """ld/st immediate: postinc mode (and load-fault)"""
2235 pi
: BaseRM
.mode
[3] # Post-Increment Mode
2236 lf
: BaseRM
.mode
[4] # Fault-First Mode (not *Data-Dependent* Fail-First)
2238 def specifiers(self
, record
):
2245 class LDSTImmFFRc1RM(FFPRRc1BaseRM
, LDSTImmBaseRM
):
2246 """ld/st immediate: Rc=1: ffirst CR sel"""
2248 CR
: BaseRM
.mode
[3, 4]
2250 def specifiers(self
, record
):
2251 yield from super().specifiers(record
=record
, mode
="ff")
2254 class LDSTImmFFRc0RM(FFPRRc0BaseRM
, ElsBaseRM
, LDSTImmBaseRM
):
2255 """ld/st immediate: Rc=0: ffirst z/nonz"""
2260 def specifiers(self
, record
):
2261 yield from super().specifiers(record
=record
, mode
="ff")
2264 class LDSTImmSatRM(ElsBaseRM
, SatBaseRM
, ZZBaseRM
, LDSTImmBaseRM
):
2265 """ld/st immediate: sat mode: N=0/1 u/s"""
2273 class LDSTImmPRRc1RM(FFPRRc1BaseRM
, LDSTImmBaseRM
):
2274 """ld/st immediate: Rc=1: pred-result CR sel"""
2276 CR
: BaseRM
.mode
[3, 4]
2278 def specifiers(self
, record
):
2279 yield from super().specifiers(record
=record
, mode
="pr")
2282 class LDSTImmPRRc0RM(FFPRRc0BaseRM
, ElsBaseRM
, LDSTImmBaseRM
):
2283 """ld/st immediate: Rc=0: pred-result z/nonz"""
2288 def specifiers(self
, record
):
2289 yield from super().specifiers(record
=record
, mode
="pr")
2292 class LDSTImmRM(LDSTImmBaseRM
):
2293 simple
: LDSTImmSimpleRM
2295 ffrc1
: LDSTImmFFRc1RM
2296 ffrc0
: LDSTImmFFRc0RM
2298 prrc1
: LDSTImmPRRc1RM
2299 prrc0
: LDSTImmPRRc0RM
2302 class LDSTIdxBaseRM(PredicateWidthBaseRM
):
2305 https://libre-soc.org/openpower/sv/ldst/
2310 class LDSTIdxSimpleRM(SEABaseRM
, ZZCombinedBaseRM
, LDSTIdxBaseRM
):
2311 """ld/st index: simple mode"""
2317 class LDSTIdxStrideRM(SEABaseRM
, ZZCombinedBaseRM
, LDSTIdxBaseRM
):
2318 """ld/st index: strided (scalar only source)"""
2323 def specifiers(self
, record
):
2326 yield from super().specifiers(record
=record
)
2329 class LDSTIdxSatRM(SatBaseRM
, ZZCombinedBaseRM
, LDSTIdxBaseRM
):
2330 """ld/st index: sat mode: N=0/1 u/s"""
2336 class LDSTIdxPRRc1RM(LDSTIdxBaseRM
):
2337 """ld/st index: Rc=1: pred-result CR sel"""
2339 CR
: BaseRM
.mode
[3, 4]
2341 def specifiers(self
, record
):
2342 yield from super().specifiers(record
=record
, mode
="pr")
2345 class LDSTIdxPRRc0RM(FFPRRc0BaseRM
, ZZBaseRM
, LDSTIdxBaseRM
):
2346 """ld/st index: Rc=0: pred-result z/nonz"""
2353 def specifiers(self
, record
):
2354 yield from super().specifiers(record
=record
, mode
="pr")
2357 class LDSTIdxRM(LDSTIdxBaseRM
):
2358 simple
: LDSTIdxSimpleRM
2359 stride
: LDSTIdxStrideRM
2361 prrc1
: LDSTIdxPRRc1RM
2362 prrc0
: LDSTIdxPRRc0RM
2366 class CROpBaseRM(BaseRM
):
2369 https://libre-soc.org/openpower/sv/cr_ops/
2374 class CROpSimpleRM(PredicateBaseRM
, ZZCombinedBaseRM
, CROpBaseRM
):
2375 """crop: simple mode"""
2380 def specifiers(self
, record
):
2382 yield "rg" # simple CR Mode reports /rg
2384 yield from super().specifiers(record
=record
)
2387 class CROpMRRM(MRBaseRM
, ZZCombinedBaseRM
, CROpBaseRM
):
2388 """crop: scalar reduce mode (mapreduce), SUBVL=1"""
2394 class CROpFF3RM(FFPRRc0BaseRM
, PredicateBaseRM
, VLiBaseRM
, DZBaseRM
, SZBaseRM
, CROpBaseRM
):
2395 """crop: ffirst 3-bit mode"""
2402 def specifiers(self
, record
):
2403 yield from super().specifiers(record
=record
, mode
="ff")
2406 # FIXME: almost everything in this class contradicts the specs.
2407 # However, this is the direct translation of the pysvp64asm code.
2408 # Please revisit this code; there is an inactive sketch below.
2409 class CROpFF5RM(FFPRRc1BaseRM
, PredicateBaseRM
, VLiBaseRM
, CROpBaseRM
):
2410 """cr_op: ffirst 5-bit mode"""
2417 def specifiers(self
, record
):
2418 yield from super().specifiers(record
=record
, mode
="ff")
2421 class CROpRM(CROpBaseRM
):
2422 simple
: CROpSimpleRM
2428 # ********************
2430 # https://libre-soc.org/openpower/sv/branches/
2431 class BranchBaseRM(BaseRM
):
2441 def specifiers(self
, record
):
2453 raise ValueError(self
.sz
)
2465 # Branch modes lack source mask.
2466 # Therefore a custom code is needed.
2467 CR
= (int(self
.mmode
) == 1)
2468 mask
= int(self
.mask
)
2469 m
= PredicateBaseRM
.predicate(CR
, mask
)
2473 yield from super().specifiers(record
=record
)
2476 class BranchSimpleRM(BranchBaseRM
):
2477 """branch: simple mode"""
2481 class BranchVLSRM(BranchBaseRM
):
2482 """branch: VLSET mode"""
2486 def specifiers(self
, record
):
2492 }[int(self
.VSb
), int(self
.VLi
)]
2494 yield from super().specifiers(record
=record
)
2497 class BranchCTRRM(BranchBaseRM
):
2498 """branch: CTR-test mode"""
2501 def specifiers(self
, record
):
2507 yield from super().specifiers(record
=record
)
2510 class BranchCTRVLSRM(BranchVLSRM
, BranchCTRRM
):
2511 """branch: CTR-test+VLSET mode"""
2515 class BranchRM(BranchBaseRM
):
2516 simple
: BranchSimpleRM
2519 ctrvls
: BranchCTRVLSRM
2530 @_dataclasses.dataclass(eq
=True, frozen
=True)
2535 def match(cls
, desc
, record
):
2536 raise NotImplementedError()
2538 def validate(self
, others
):
2541 def assemble(self
, insn
):
2542 raise NotImplementedError()
2545 @_dataclasses.dataclass(eq
=True, frozen
=True)
2546 class SpecifierWidth(Specifier
):
2550 def match(cls
, desc
, record
, etalon
):
2551 (mode
, _
, value
) = desc
.partition("=")
2553 value
= value
.strip()
2556 width
= _SVP64Width(value
)
2558 return cls(record
=record
, width
=width
)
2561 @_dataclasses.dataclass(eq
=True, frozen
=True)
2562 class SpecifierW(SpecifierWidth
):
2564 def match(cls
, desc
, record
):
2565 return super().match(desc
=desc
, record
=record
, etalon
="w")
2567 def assemble(self
, insn
):
2568 selector
= insn
.select(record
=self
.record
)
2569 selector
.ewsrc
= self
.width
.value
2570 selector
.elwidth
= self
.width
.value
2573 @_dataclasses.dataclass(eq
=True, frozen
=True)
2574 class SpecifierSW(SpecifierWidth
):
2576 def match(cls
, desc
, record
):
2577 return super().match(desc
=desc
, record
=record
, etalon
="sw")
2579 def assemble(self
, insn
):
2580 selector
= insn
.select(record
=self
.record
)
2581 selector
.ewsrc
= self
.width
.value
2584 @_dataclasses.dataclass(eq
=True, frozen
=True)
2585 class SpecifierDW(SpecifierWidth
):
2587 def match(cls
, desc
, record
):
2588 return super().match(desc
=desc
, record
=record
, etalon
="dw")
2590 def assemble(self
, insn
):
2591 selector
= insn
.select(record
=self
.record
)
2592 selector
.elwidth
= self
.width
.value
2595 @_dataclasses.dataclass(eq
=True, frozen
=True)
2596 class SpecifierSubVL(Specifier
):
2600 def match(cls
, desc
, record
):
2602 value
= _SVP64SubVL(desc
)
2606 return cls(record
=record
, value
=value
)
2608 def assemble(self
, insn
):
2609 selector
= insn
.select(record
=self
.record
)
2610 selector
.subvl
= int(self
.value
.value
)
2613 @_dataclasses.dataclass(eq
=True, frozen
=True)
2614 class SpecifierPredicate(Specifier
):
2619 def match(cls
, desc
, record
, mode_match
, pred_match
):
2620 (mode
, _
, pred
) = desc
.partition("=")
2623 if not mode_match(mode
):
2626 pred
= _SVP64Pred(pred
.strip())
2627 if not pred_match(pred
):
2628 raise ValueError(pred
)
2630 return cls(record
=record
, mode
=mode
, pred
=pred
)
2633 @_dataclasses.dataclass(eq
=True, frozen
=True)
2634 class SpecifierFFPR(SpecifierPredicate
):
2636 def match(cls
, desc
, record
, mode
):
2637 return super().match(desc
=desc
, record
=record
,
2638 mode_match
=lambda mode_arg
: mode_arg
== mode
,
2639 pred_match
=lambda pred_arg
: pred_arg
.mode
in (
2644 def validate(self
, others
):
2645 if self
.record
.svp64
.mode
is _SVMode
.CROP
:
2646 if self
.mode
== "pr":
2647 raise ValueError("crop: 'pr' mode not supported")
2649 def assemble(self
, insn
):
2650 selector
= insn
.select(record
=self
.record
)
2651 if selector
.mode
.sel
!= 0:
2652 raise ValueError("cannot override mode")
2653 if self
.record
.svp64
.mode
is _SVMode
.CROP
:
2654 selector
.mode
.sel
= 0b10
2655 # HACK: please finally provide correct logic for CRs.
2656 if self
.pred
in (_SVP64Pred
.RC1
, _SVP64Pred
.RC1_N
):
2657 selector
.mode
[2] = (self
.pred
is _SVP64Pred
.RC1_N
)
2659 selector
.mode
[2] = self
.pred
.inv
2660 selector
.mode
[3, 4] = self
.pred
.state
2662 selector
.mode
.sel
= 0b01 if self
.mode
== "ff" else 0b11
2663 selector
.inv
= self
.pred
.inv
2665 selector
.CR
= self
.pred
.state
2667 selector
.RC1
= self
.pred
.state
2670 @_dataclasses.dataclass(eq
=True, frozen
=True)
2671 class SpecifierFF(SpecifierFFPR
):
2673 def match(cls
, desc
, record
):
2674 return super().match(desc
=desc
, record
=record
, mode
="ff")
2677 @_dataclasses.dataclass(eq
=True, frozen
=True)
2678 class SpecifierPR(SpecifierFFPR
):
2680 def match(cls
, desc
, record
):
2681 return super().match(desc
=desc
, record
=record
, mode
="pr")
2684 @_dataclasses.dataclass(eq
=True, frozen
=True)
2685 class SpecifierMask(SpecifierPredicate
):
2687 def match(cls
, desc
, record
, mode
):
2688 return super().match(desc
=desc
, record
=record
,
2689 mode_match
=lambda mode_arg
: mode_arg
== mode
,
2690 pred_match
=lambda pred_arg
: pred_arg
.mode
in (
2695 def assemble(self
, insn
):
2696 raise NotImplementedError()
2699 @_dataclasses.dataclass(eq
=True, frozen
=True)
2700 class SpecifierM(SpecifierMask
):
2702 def match(cls
, desc
, record
):
2703 return super().match(desc
=desc
, record
=record
, mode
="m")
2705 def validate(self
, others
):
2707 if isinstance(spec
, SpecifierSM
):
2708 raise ValueError("source-mask and predicate mask conflict")
2709 elif isinstance(spec
, SpecifierDM
):
2710 raise ValueError("dest-mask and predicate mask conflict")
2712 def assemble(self
, insn
):
2713 selector
= insn
.select(record
=self
.record
)
2714 selector
.mask
= int(self
.pred
)
2715 if ((self
.record
.ptype
is _SVPType
.P2
) and
2716 (self
.record
.svp64
.mode
is not _SVMode
.BRANCH
)):
2717 selector
.smask
= int(self
.pred
)
2718 selector
.mmode
= (self
.pred
.mode
is _SVP64PredMode
.CR
)
2721 @_dataclasses.dataclass(eq
=True, frozen
=True)
2722 class SpecifierSM(SpecifierMask
):
2724 def match(cls
, desc
, record
):
2725 return super().match(desc
=desc
, record
=record
, mode
="sm")
2727 def validate(self
, others
):
2728 if self
.record
.svp64
.ptype
is _SVPType
.P1
:
2729 raise ValueError("source-mask on non-twin predicate")
2731 if self
.pred
.mode
is _SVP64PredMode
.CR
:
2734 if isinstance(spec
, SpecifierDM
):
2738 raise ValueError("missing dest-mask in CR twin predication")
2739 if self
.pred
.mode
!= twin
.pred
.mode
:
2740 raise ValueError(f
"predicate masks mismatch: {self.pred!r} vs {twin.pred!r}")
2742 def assemble(self
, insn
):
2743 selector
= insn
.select(record
=self
.record
)
2744 selector
.smask
= int(self
.pred
)
2745 selector
.mmode
= (self
.pred
.mode
is _SVP64PredMode
.CR
)
2748 @_dataclasses.dataclass(eq
=True, frozen
=True)
2749 class SpecifierDM(SpecifierMask
):
2751 def match(cls
, desc
, record
):
2752 return super().match(desc
=desc
, record
=record
, mode
="dm")
2754 def validate(self
, others
):
2755 if self
.record
.svp64
.ptype
is _SVPType
.P1
:
2756 raise ValueError("dest-mask on non-twin predicate")
2758 if self
.pred
.mode
is _SVP64PredMode
.CR
:
2761 if isinstance(spec
, SpecifierSM
):
2765 raise ValueError("missing source-mask in CR twin predication")
2766 if self
.pred
.mode
!= twin
.pred
.mode
:
2767 raise ValueError(f
"predicate masks mismatch: {self.pred!r} vs {twin.pred!r}")
2769 def assemble(self
, insn
):
2770 selector
= insn
.select(record
=self
.record
)
2771 selector
.mask
= int(self
.pred
)
2772 selector
.mmode
= (self
.pred
.mode
is _SVP64PredMode
.CR
)
2775 @_dataclasses.dataclass(eq
=True, frozen
=True)
2776 class SpecifierZZ(Specifier
):
2778 def match(cls
, desc
, record
):
2782 return cls(record
=record
)
2784 def validate(self
, others
):
2786 # Since zz takes precedence (overrides) sz and dz,
2787 # treat them as mutually exclusive.
2788 if isinstance(spec
, (SpecifierSZ
, SpecifierDZ
)):
2789 raise ValueError("mutually exclusive predicate masks")
2791 def assemble(self
, insn
):
2792 selector
= insn
.select(record
=self
.record
)
2793 if hasattr(selector
, "zz"): # this should be done in a different way
2800 @_dataclasses.dataclass(eq
=True, frozen
=True)
2801 class SpecifierXZ(Specifier
):
2803 hint
: str = _dataclasses
.field(repr=False)
2806 def match(cls
, desc
, record
, etalon
, hint
):
2810 return cls(desc
=desc
, record
=record
, hint
=hint
)
2812 def validate(self
, others
):
2813 if self
.record
.svp64
.ptype
is _SVPType
.P1
:
2814 raise ValueError(f
"{self.hint} on non-twin predicate")
2816 if self
.pred
.mode
is _SVP64PredMode
.CR
:
2819 if isinstance(spec
, SpecifierXZ
):
2823 raise ValueError(f
"missing {self.hint} in CR twin predication")
2824 if self
.pred
!= twin
.pred
:
2825 raise ValueError(f
"predicate masks mismatch: {self.pred!r} vs {twin.pred!r}")
2827 def assemble(self
, insn
):
2828 selector
= insn
.select(record
=self
.record
)
2829 setattr(selector
, self
.desc
, 1)
2832 @_dataclasses.dataclass(eq
=True, frozen
=True)
2833 class SpecifierSZ(SpecifierXZ
):
2835 def match(cls
, desc
, record
):
2836 return super().match(desc
=desc
, record
=record
,
2837 etalon
="sz", hint
="source-mask")
2839 def validate(self
, others
):
2841 if self
.record
.svp64
.mode
is not _SVMode
.CROP
:
2842 if isinstance(spec
, SpecifierFF
):
2843 raise ValueError("source-zero not allowed in ff mode")
2844 elif isinstance(spec
, SpecifierPR
):
2845 raise ValueError("source-zero not allowed in pr mode")
2848 @_dataclasses.dataclass(eq
=True, frozen
=True)
2849 class SpecifierDZ(SpecifierXZ
):
2851 def match(cls
, desc
, record
):
2852 return super().match(desc
=desc
, record
=record
,
2853 etalon
="dz", hint
="dest-mask")
2855 def validate(self
, others
):
2857 if ((self
.record
.svp64
.mode
is not _SVMode
.CROP
) and
2858 isinstance(spec
, (SpecifierFF
, SpecifierPR
)) and
2859 (spec
.pred
.mode
is _SVP64PredMode
.RC1
)):
2860 mode
= "ff" if isinstance(spec
, SpecifierFF
) else "pr"
2861 raise ValueError(f
"dest-zero not allowed in {mode} mode BO")
2864 @_dataclasses.dataclass(eq
=True, frozen
=True)
2865 class SpecifierEls(Specifier
):
2867 def match(cls
, desc
, record
):
2871 if record
.svp64
.mode
not in (_SVMode
.LDST_IMM
, _SVMode
.LDST_IDX
):
2872 raise ValueError("els is only valid in ld/st modes")
2874 return cls(record
=record
)
2876 def assemble(self
, insn
):
2877 if self
.record
.svp64
.mode
is _SVMode
.LDST_IDX
: # stride mode
2878 insn
.prefix
.rm
.mode
[0] = 0
2879 insn
.prefix
.rm
.mode
[1] = 1
2881 selector
= insn
.select(record
=self
.record
)
2882 if self
.record
.svp64
.mode
is not _SVMode
.LDST_IDX
: # stride mode
2887 @_dataclasses.dataclass(eq
=True, frozen
=True)
2888 class SpecifierSEA(Specifier
):
2890 def match(cls
, desc
, record
):
2894 return cls(record
=record
)
2896 def validate(self
, others
):
2897 if self
.record
.svp64
.mode
is not _SVMode
.LDST_IDX
:
2898 raise ValueError("sea is only valid in ld/st modes")
2901 if isinstance(spec
, SpecifierFF
):
2902 raise ValueError(f
"sea cannot be used in ff mode")
2904 def assemble(self
, insn
):
2905 selector
= insn
.select(record
=self
.record
)
2906 if selector
.mode
.sel
not in (0b00, 0b01):
2907 raise ValueError("sea is only valid for normal and els modes")
2911 @_dataclasses.dataclass(eq
=True, frozen
=True)
2912 class SpecifierSat(Specifier
):
2917 def match(cls
, desc
, record
, etalon
, sign
):
2921 if record
.svp64
.mode
not in (_SVMode
.NORMAL
, _SVMode
.LDST_IMM
, _SVMode
.LDST_IDX
):
2922 raise ValueError("only normal, ld/st imm and ld/st idx modes supported")
2924 return cls(record
=record
, desc
=desc
, sign
=sign
)
2926 def assemble(self
, insn
):
2927 selector
= insn
.select(record
=self
.record
)
2928 selector
.mode
[0] = 0b1
2929 selector
.mode
[1] = 0b0
2930 selector
.N
= int(self
.sign
)
2933 @_dataclasses.dataclass(eq
=True, frozen
=True)
2934 class SpecifierSatS(SpecifierSat
):
2936 def match(cls
, desc
, record
):
2937 return super().match(desc
=desc
, record
=record
,
2938 etalon
="sats", sign
=True)
2941 @_dataclasses.dataclass(eq
=True, frozen
=True)
2942 class SpecifierSatU(SpecifierSat
):
2944 def match(cls
, desc
, record
):
2945 return super().match(desc
=desc
, record
=record
,
2946 etalon
="satu", sign
=False)
2949 @_dataclasses.dataclass(eq
=True, frozen
=True)
2950 class SpecifierMapReduce(Specifier
):
2954 def match(cls
, record
, RG
):
2955 if record
.svp64
.mode
not in (_SVMode
.NORMAL
, _SVMode
.CROP
):
2956 raise ValueError("only normal and crop modes supported")
2958 return cls(record
=record
, RG
=RG
)
2960 def assemble(self
, insn
):
2961 selector
= insn
.select(record
=self
.record
)
2962 if self
.record
.svp64
.mode
not in (_SVMode
.NORMAL
, _SVMode
.CROP
):
2963 raise ValueError("only normal and crop modes supported")
2964 selector
.mode
[0] = 0
2965 selector
.mode
[1] = 0
2966 selector
.mode
[2] = 1
2967 selector
.RG
= self
.RG
2970 @_dataclasses.dataclass(eq
=True, frozen
=True)
2971 class SpecifierMR(SpecifierMapReduce
):
2973 def match(cls
, desc
, record
):
2977 return super().match(record
=record
, RG
=False)
2980 @_dataclasses.dataclass(eq
=True, frozen
=True)
2981 class SpecifierMRR(SpecifierMapReduce
):
2983 def match(cls
, desc
, record
):
2987 return super().match(record
=record
, RG
=True)
2990 @_dataclasses.dataclass(eq
=True, frozen
=True)
2991 class SpecifierBranch(Specifier
):
2993 def match(cls
, desc
, record
, etalon
):
2997 if record
.svp64
.mode
is not _SVMode
.BRANCH
:
2998 raise ValueError("only branch modes supported")
3000 return cls(record
=record
)
3003 @_dataclasses.dataclass(eq
=True, frozen
=True)
3004 class SpecifierAll(SpecifierBranch
):
3006 def match(cls
, desc
, record
):
3007 return super().match(desc
=desc
, record
=record
, etalon
="all")
3009 def assemble(self
, insn
):
3010 selector
= insn
.select(record
=self
.record
)
3014 @_dataclasses.dataclass(eq
=True, frozen
=True)
3015 class SpecifierSNZ(Specifier
):
3017 def match(cls
, desc
, record
):
3021 if record
.svp64
.mode
not in (_SVMode
.BRANCH
, _SVMode
.CROP
):
3022 raise ValueError("only branch and crop modes supported")
3024 return cls(record
=record
)
3026 def assemble(self
, insn
):
3027 selector
= insn
.select(record
=self
.record
)
3028 if self
.record
.svp64
.mode
in (_SVMode
.CROP
, _SVMode
.BRANCH
):
3030 if self
.record
.svp64
.mode
is _SVMode
.BRANCH
:
3033 raise ValueError("only branch and crop modes supported")
3036 @_dataclasses.dataclass(eq
=True, frozen
=True)
3037 class SpecifierSL(SpecifierBranch
):
3039 def match(cls
, desc
, record
):
3040 return super().match(desc
=desc
, record
=record
, etalon
="sl")
3042 def assemble(self
, insn
):
3043 selector
= insn
.select(record
=self
.record
)
3047 @_dataclasses.dataclass(eq
=True, frozen
=True)
3048 class SpecifierSLu(SpecifierBranch
):
3050 def match(cls
, desc
, record
):
3051 return super().match(desc
=desc
, record
=record
, etalon
="slu")
3053 def assemble(self
, insn
):
3054 selector
= insn
.select(record
=self
.record
)
3058 @_dataclasses.dataclass(eq
=True, frozen
=True)
3059 class SpecifierLRu(SpecifierBranch
):
3061 def match(cls
, desc
, record
):
3062 return super().match(desc
=desc
, record
=record
, etalon
="lru")
3064 def assemble(self
, insn
):
3065 selector
= insn
.select(record
=self
.record
)
3069 @_dataclasses.dataclass(eq
=True, frozen
=True)
3070 class SpecifierVSXX(SpecifierBranch
):
3075 def match(cls
, desc
, record
, etalon
, VSb
, VLi
):
3079 if record
.svp64
.mode
is not _SVMode
.BRANCH
:
3080 raise ValueError("only branch modes supported")
3082 return cls(record
=record
, VSb
=VSb
, VLi
=VLi
)
3084 def assemble(self
, insn
):
3085 selector
= insn
.select(record
=self
.record
)
3087 selector
.VSb
= int(self
.VSb
)
3088 selector
.VLi
= int(self
.VLi
)
3091 @_dataclasses.dataclass(eq
=True, frozen
=True)
3092 class SpecifierVS(SpecifierVSXX
):
3094 def match(cls
, desc
, record
):
3095 return super().match(desc
=desc
, record
=record
,
3096 etalon
="vs", VSb
=False, VLi
=False)
3099 @_dataclasses.dataclass(eq
=True, frozen
=True)
3100 class SpecifierVSi(SpecifierVSXX
):
3102 def match(cls
, desc
, record
):
3103 return super().match(desc
=desc
, record
=record
,
3104 etalon
="vsi", VSb
=False, VLi
=True)
3107 @_dataclasses.dataclass(eq
=True, frozen
=True)
3108 class SpecifierVSb(SpecifierVSXX
):
3110 def match(cls
, desc
, record
):
3111 return super().match(desc
=desc
, record
=record
,
3112 etalon
="vsb", VSb
=True, VLi
=False)
3115 @_dataclasses.dataclass(eq
=True, frozen
=True)
3116 class SpecifierVSbi(SpecifierVSXX
):
3118 def match(cls
, desc
, record
):
3119 return super().match(desc
=desc
, record
=record
,
3120 etalon
="vsbi", VSb
=True, VLi
=True)
3123 @_dataclasses.dataclass(eq
=True, frozen
=True)
3124 class SpecifierCTX(Specifier
):
3128 def match(cls
, desc
, record
, etalon
, CTi
):
3132 if record
.svp64
.mode
is not _SVMode
.BRANCH
:
3133 raise ValueError("only branch modes supported")
3135 return cls(record
=record
, CTi
=CTi
)
3137 def assemble(self
, insn
):
3138 selector
= insn
.select(record
=self
.record
)
3140 selector
.CTi
= int(self
.CTi
)
3143 @_dataclasses.dataclass(eq
=True, frozen
=True)
3144 class SpecifierCTR(SpecifierCTX
):
3146 def match(cls
, desc
, record
):
3147 return super().match(desc
=desc
, record
=record
,
3148 etalon
="ctr", CTi
=False)
3151 @_dataclasses.dataclass(eq
=True, frozen
=True)
3152 class SpecifierCTi(SpecifierCTX
):
3154 def match(cls
, desc
, record
):
3155 return super().match(desc
=desc
, record
=record
,
3156 etalon
="cti", CTi
=True)
3159 @_dataclasses.dataclass(eq
=True, frozen
=True)
3160 class SpecifierPI(Specifier
):
3162 def match(cls
, desc
, record
):
3166 if record
.svp64
.mode
is not _SVMode
.LDST_IMM
:
3167 raise ValueError("only ld/st imm mode supported")
3169 return cls(record
=record
)
3171 def assemble(self
, insn
):
3172 selector
= insn
.select(record
=self
.record
)
3173 selector
.mode
[0] = 0b0
3174 selector
.mode
[1] = 0b0
3175 selector
.mode
[2] = 0b1
3179 @_dataclasses.dataclass(eq
=True, frozen
=True)
3180 class SpecifierLF(Specifier
):
3182 def match(cls
, desc
, record
):
3186 if record
.svp64
.mode
is not _SVMode
.LDST_IMM
:
3187 raise ValueError("only ld/st imm mode supported")
3189 return cls(record
=record
)
3191 def assemble(self
, insn
):
3192 selector
= insn
.select(record
=self
.record
)
3193 selector
.mode
[2] = 1
3197 @_dataclasses.dataclass(eq
=True, frozen
=True)
3198 class SpecifierVLi(Specifier
):
3200 def match(cls
, desc
, record
):
3204 return cls(record
=record
)
3206 def validate(self
, others
):
3208 if isinstance(spec
, SpecifierFF
):
3211 raise ValueError("VLi only allowed in failfirst")
3213 def assemble(self
, insn
):
3214 selector
= insn
.select(record
=self
.record
)
3218 class Specifiers(tuple):
3254 def __new__(cls
, items
, record
):
3255 def transform(item
):
3256 for spec_cls
in cls
.SPECS
:
3257 spec
= spec_cls
.match(item
, record
=record
)
3258 if spec
is not None:
3260 raise ValueError(item
)
3262 # TODO: remove this hack
3263 items
= dict.fromkeys(items
)
3267 items
= tuple(items
)
3269 specs
= tuple(map(transform
, items
))
3270 for (index
, spec
) in enumerate(specs
):
3271 head
= specs
[:index
]
3272 tail
= specs
[index
+ 1:]
3273 spec
.validate(others
=(head
+ tail
))
3275 return super().__new
__(cls
, specs
)
3278 class SVP64OperandMeta(type):
3279 class SVP64NonZeroOperand(NonZeroOperand
):
3280 def assemble(self
, insn
, value
):
3281 if isinstance(value
, str):
3282 value
= int(value
, 0)
3283 if not isinstance(value
, int):
3284 raise ValueError("non-integer operand")
3286 # FIXME: this is really weird
3287 if self
.record
.name
in ("svstep", "svstep."):
3288 value
+= 1 # compensation
3290 return super().assemble(value
=value
, insn
=insn
)
3292 class SVP64XOStaticOperand(SpanStaticOperand
):
3293 def __init__(self
, record
, value
, span
):
3294 return super().__init
__(record
=record
, name
="XO", value
=value
, span
=span
)
3297 NonZeroOperand
: SVP64NonZeroOperand
,
3298 XOStaticOperand
: SVP64XOStaticOperand
,
3301 def __new__(metacls
, name
, bases
, ns
):
3303 for (index
, base_cls
) in enumerate(bases
):
3304 bases
[index
] = metacls
.__TRANSFORM
.get(base_cls
, base_cls
)
3306 bases
= tuple(bases
)
3308 return super().__new
__(metacls
, name
, bases
, ns
)
3311 class SVP64Operand(Operand
, metaclass
=SVP64OperandMeta
):
3314 return tuple(map(lambda bit
: (bit
+ 32), super().span
))
3318 def __init__(self
, insn
, record
):
3320 self
.__record
= record
3321 return super().__init
__()
3324 return self
.rm
.__doc
__
3327 return repr(self
.rm
)
3335 return self
.__record
3339 rm
= getattr(self
.insn
.prefix
.rm
, self
.record
.svp64
.mode
.name
.lower())
3341 # The idea behind these tables is that they are now literally
3342 # in identical format to insndb.csv and minor_xx.csv and can
3343 # be done precisely as that. The only thing to watch out for
3344 # is the insertion of Rc=1 as a "mask/value" bit and likewise
3345 # regtype detection (3-bit BF/BFA, 5-bit BA/BB/BT) also inserted
3348 if self
.record
.svp64
.mode
is _SVMode
.NORMAL
:
3349 # concatenate mode 5-bit with Rc (LSB) then do a mask/map search
3350 # mode Rc mask Rc member
3352 (0b000000, 0b111000, "simple"), # simple (no Rc)
3353 (0b001000, 0b111000, "mr"), # mapreduce (no Rc)
3354 (0b010001, 0b110001, "ffrc1"), # ffirst, Rc=1
3355 (0b010000, 0b110001, "ffrc0"), # ffirst, Rc=0
3356 (0b100000, 0b110000, "sat"), # saturation (no Rc)
3357 (0b110000, 0b110001, "prrc0"), # predicate, Rc=0
3358 (0b110001, 0b110001, "prrc1"), # predicate, Rc=1
3360 search
= ((int(self
.insn
.prefix
.rm
.normal
.mode
) << 1) | self
.record
.Rc
)
3362 elif self
.record
.svp64
.mode
is _SVMode
.LDST_IMM
:
3363 # concatenate mode 5-bit with Rc (LSB) then do a mask/map search
3364 # mode Rc mask Rc member
3365 # ironically/coincidentally this table is identical to NORMAL
3366 # mode except reserved in place of mr
3368 (0b000000, 0b111000, "simple"), # simple (no Rc)
3369 (0b001000, 0b111000, "post"), # post (no Rc)
3370 (0b010001, 0b110001, "ffrc1"), # ffirst, Rc=1
3371 (0b010000, 0b110001, "ffrc0"), # ffirst, Rc=0
3372 (0b100000, 0b110000, "sat"), # saturation (no Rc)
3373 (0b110001, 0b110001, "prrc1"), # predicate, Rc=1
3374 (0b110000, 0b110001, "prrc0"), # predicate, Rc=0
3376 search
= ((int(self
.insn
.prefix
.rm
.ldst_imm
.mode
) << 1) | self
.record
.Rc
)
3378 elif self
.record
.svp64
.mode
is _SVMode
.LDST_IDX
:
3379 # concatenate mode 5-bit with Rc (LSB) then do a mask/map search
3380 # mode Rc mask Rc member
3382 (0b000000, 0b110000, "simple"), # simple (no Rc)
3383 (0b010000, 0b110000, "stride"), # strided, (no Rc)
3384 (0b100000, 0b110000, "sat"), # saturation (no Rc)
3385 (0b110001, 0b110001, "prrc1"), # predicate, Rc=1
3386 (0b110000, 0b110001, "prrc0"), # predicate, Rc=0
3388 search
= ((int(self
.insn
.prefix
.rm
.ldst_idx
.mode
) << 1) | self
.record
.Rc
)
3390 elif self
.record
.svp64
.mode
is _SVMode
.CROP
:
3391 # concatenate mode 5-bit with regtype (LSB) then do mask/map search
3392 # mode 3b mask 3b member
3394 (0b000000, 0b111000, "simple"), # simple
3395 (0b001000, 0b111000, "mr"), # mapreduce
3396 (0b100001, 0b100001, "ff3"), # ffirst, 3-bit CR
3397 (0b100000, 0b100000, "ff5"), # ffirst, 5-bit CR
3399 search
= ((int(self
.insn
.prefix
.rm
.crop
.mode
) << 1) |
int(self
.record
.svp64
.extra_CR_3bit
))
3401 elif self
.record
.svp64
.mode
is _SVMode
.BRANCH
:
3405 (0b00, 0b11, "simple"), # simple
3406 (0b01, 0b11, "vls"), # VLset
3407 (0b10, 0b11, "ctr"), # CTR mode
3408 (0b11, 0b11, "ctrvls"), # CTR+VLset mode
3410 # slightly weird: doesn't have a 5-bit "mode" field like others
3411 search
= int(self
.insn
.prefix
.rm
.branch
.mode
.sel
)
3414 if table
is not None:
3415 for (value
, mask
, field
) in table
:
3416 if ((value
& mask
) == (search
& mask
)):
3417 return getattr(rm
, field
)
3421 def __getattr__(self
, key
):
3422 if key
.startswith(f
"_{self.__class__.__name__}__"):
3423 return super().__getattribute
__(key
)
3425 return getattr(self
.rm
, key
)
3427 def __setattr__(self
, key
, value
):
3428 if key
.startswith(f
"_{self.__class__.__name__}__"):
3429 return super().__setattr
__(key
, value
)
3432 if not hasattr(rm
, key
):
3433 raise AttributeError(key
)
3435 return setattr(rm
, key
, value
)
3438 class SVP64Instruction(PrefixedInstruction
):
3439 """SVP64 instruction: https://libre-soc.org/openpower/sv/svp64/"""
3440 class Prefix(PrefixedInstruction
.Prefix
):
3442 rm
: RM
.remap((6, 8) + tuple(range(10, 32)))
3446 def select(self
, record
):
3447 return RMSelector(insn
=self
, record
=record
)
3452 for idx
in range(64):
3453 bit
= int(self
[idx
])
3455 return "".join(map(str, bits
))
3458 def assemble(cls
, record
, arguments
=None, specifiers
=None):
3459 insn
= super().assemble(record
=record
, arguments
=arguments
)
3461 specifiers
= Specifiers(items
=specifiers
, record
=record
)
3462 for specifier
in specifiers
:
3463 specifier
.assemble(insn
=insn
)
3465 insn
.prefix
.PO
= 0x1
3466 insn
.prefix
.id = 0x3
3470 def disassemble(self
, record
,
3472 style
=Style
.NORMAL
):
3474 if style
<= Style
.SHORT
:
3477 blob
= insn
.bytes(byteorder
=byteorder
)
3478 blob
= " ".join(map(lambda byte
: f
"{byte:02x}", blob
))
3481 blob_prefix
= blob(self
.prefix
)
3482 blob_suffix
= blob(self
.suffix
)
3484 yield f
"{blob_prefix}.long 0x{int(self.prefix):08x}"
3485 yield f
"{blob_suffix}.long 0x{int(self.suffix):08x}"
3488 assert record
.svp64
is not None
3490 name
= f
"sv.{record.name}"
3492 rm
= self
.select(record
=record
)
3494 # convert specifiers to /x/y/z (sorted lexicographically)
3495 specifiers
= sorted(rm
.specifiers(record
=record
))
3496 if specifiers
: # if any add one extra to get the extra "/"
3497 specifiers
= ([""] + specifiers
)
3498 specifiers
= "/".join(specifiers
)
3500 # convert operands to " ,x,y,z"
3501 operands
= tuple(map(_operator
.itemgetter(1),
3502 self
.spec_dynamic_operands(record
=record
, style
=style
)))
3503 operands
= ",".join(operands
)
3504 if len(operands
) > 0: # if any separate with a space
3505 operands
= (" " + operands
)
3507 if style
<= Style
.LEGACY
:
3508 yield f
"{blob_prefix}.long 0x{int(self.prefix):08x}"
3509 suffix
= WordInstruction
.integer(value
=int(self
.suffix
))
3510 yield from suffix
.disassemble(record
=record
,
3511 byteorder
=byteorder
, style
=style
)
3513 yield f
"{blob_prefix}{name}{specifiers}{operands}"
3515 yield f
"{blob_suffix}"
3517 if style
>= Style
.VERBOSE
:
3519 binary
= self
.binary
3520 spec
= self
.spec(record
=record
, prefix
="sv.")
3522 yield f
"{indent}spec"
3523 yield f
"{indent}{indent}{spec}"
3524 yield f
"{indent}pcode"
3525 for stmt
in record
.mdwn
.pcode
:
3526 yield f
"{indent}{indent}{stmt}"
3527 yield f
"{indent}binary"
3528 yield f
"{indent}{indent}[0:8] {binary[0:8]}"
3529 yield f
"{indent}{indent}[8:16] {binary[8:16]}"
3530 yield f
"{indent}{indent}[16:24] {binary[16:24]}"
3531 yield f
"{indent}{indent}[24:32] {binary[24:32]}"
3532 yield f
"{indent}{indent}[32:40] {binary[32:40]}"
3533 yield f
"{indent}{indent}[40:48] {binary[40:48]}"
3534 yield f
"{indent}{indent}[48:56] {binary[48:56]}"
3535 yield f
"{indent}{indent}[56:64] {binary[56:64]}"
3536 yield f
"{indent}opcodes"
3537 for opcode
in record
.opcodes
:
3538 yield f
"{indent}{indent}{opcode!r}"
3539 for operand
in self
.operands(record
=record
):
3540 yield from operand
.disassemble(insn
=self
,
3541 style
=style
, indent
=indent
)
3543 yield f
"{indent}{indent}{str(rm)}"
3544 for line
in rm
.disassemble(style
=style
):
3545 yield f
"{indent}{indent}{line}"
3549 def operands(cls
, record
):
3550 for operand
in super().operands(record
=record
):
3551 parent
= operand
.__class
__
3552 name
= f
"SVP64{parent.__name__}"
3553 bases
= (SVP64Operand
, parent
)
3554 child
= type(name
, bases
, {})
3555 yield child(**dict(operand
))
3558 def parse(stream
, factory
):
3560 return ("TODO" not in frozenset(entry
.values()))
3562 lines
= filter(lambda line
: not line
.strip().startswith("#"), stream
)
3563 entries
= _csv
.DictReader(lines
)
3564 entries
= filter(match
, entries
)
3565 return tuple(map(factory
, entries
))
3568 class MarkdownDatabase
:
3571 for (name
, desc
) in _ISA():
3574 (dynamic
, *static
) = desc
.regs
3575 operands
.extend(dynamic
)
3576 operands
.extend(static
)
3577 pcode
= PCode(iterable
=desc
.pcode
)
3578 operands
= Operands(insn
=name
, operands
=operands
)
3579 db
[name
] = MarkdownRecord(pcode
=pcode
, operands
=operands
)
3581 self
.__db
= dict(sorted(db
.items()))
3583 return super().__init
__()
3586 yield from self
.__db
.items()
3588 def __contains__(self
, key
):
3589 return self
.__db
.__contains
__(key
)
3591 def __getitem__(self
, key
):
3592 return self
.__db
.__getitem
__(key
)
3595 class FieldsDatabase
:
3598 df
= _DecodeFields()
3600 for (form
, fields
) in df
.instrs
.items():
3601 if form
in {"DQE", "TX"}:
3605 db
[_Form
[form
]] = Fields(fields
)
3609 return super().__init
__()
3611 def __getitem__(self
, key
):
3612 return self
.__db
.__getitem
__(key
)
3616 def __init__(self
, root
, mdwndb
):
3617 # The code below groups the instructions by name:section.
3618 # There can be multiple names for the same instruction.
3619 # The point is to capture different opcodes for the same instruction.
3621 records
= _collections
.defaultdict(set)
3622 path
= (root
/ "insndb.csv")
3623 with
open(path
, "r", encoding
="UTF-8") as stream
:
3624 for section
in sorted(parse(stream
, Section
.CSV
)):
3625 path
= (root
/ section
.path
)
3627 section
.Mode
.INTEGER
: IntegerOpcode
,
3628 section
.Mode
.PATTERN
: PatternOpcode
,
3630 factory
= _functools
.partial(
3631 PPCRecord
.CSV
, opcode_cls
=opcode_cls
)
3632 with
open(path
, "r", encoding
="UTF-8") as stream
:
3633 for insn
in parse(stream
, factory
):
3634 for name
in insn
.names
:
3635 records
[name
].add(insn
)
3636 sections
[name
] = section
3638 items
= sorted(records
.items())
3640 for (name
, multirecord
) in items
:
3641 records
[name
] = PPCMultiRecord(sorted(multirecord
))
3643 def exact_match(name
):
3644 record
= records
.get(name
)
3650 if not name
.endswith("l"):
3652 alias
= exact_match(name
[:-1])
3655 record
= records
[alias
]
3656 if "lk" not in record
.flags
:
3657 raise ValueError(record
)
3661 if not name
.endswith("a"):
3663 alias
= LK_match(name
[:-1])
3666 record
= records
[alias
]
3667 if record
.intop
not in {_MicrOp
.OP_B
, _MicrOp
.OP_BC
}:
3668 raise ValueError(record
)
3669 if "AA" not in mdwndb
[name
].operands
:
3670 raise ValueError(record
)
3674 if not name
.endswith("."):
3676 alias
= exact_match(name
[:-1])
3679 record
= records
[alias
]
3680 if record
.Rc
is _RCOE
.NONE
:
3681 raise ValueError(record
)
3685 matches
= (exact_match
, LK_match
, AA_match
, Rc_match
)
3686 for (name
, _
) in mdwndb
:
3687 if name
.startswith("sv."):
3690 for match
in matches
:
3692 if alias
is not None:
3696 section
= sections
[alias
]
3697 record
= records
[alias
]
3698 db
[name
] = (section
, record
)
3700 self
.__db
= dict(sorted(db
.items()))
3702 return super().__init
__()
3704 @_functools.lru_cache(maxsize
=512, typed
=False)
3705 def __getitem__(self
, key
):
3706 return self
.__db
.get(key
, (None, None))
3709 class SVP64Database
:
3710 def __init__(self
, root
, ppcdb
):
3712 pattern
= _re
.compile(r
"^(?:LDST)?RM-(1P|2P)-.*?\.csv$")
3713 for (prefix
, _
, names
) in _os
.walk(root
):
3714 prefix
= _pathlib
.Path(prefix
)
3715 for name
in filter(lambda name
: pattern
.match(name
), names
):
3716 path
= (prefix
/ _pathlib
.Path(name
))
3717 with
open(path
, "r", encoding
="UTF-8") as stream
:
3718 db
.update(parse(stream
, SVP64Record
.CSV
))
3719 db
= {record
.name
:record
for record
in db
}
3721 self
.__db
= dict(sorted(db
.items()))
3722 self
.__ppcdb
= ppcdb
3724 return super().__init
__()
3726 def __getitem__(self
, key
):
3727 (_
, record
) = self
.__ppcdb
[key
]
3731 for name
in record
.names
:
3732 record
= self
.__db
.get(name
, None)
3733 if record
is not None:
3740 def __init__(self
, root
):
3741 root
= _pathlib
.Path(root
)
3742 mdwndb
= MarkdownDatabase()
3743 fieldsdb
= FieldsDatabase()
3744 ppcdb
= PPCDatabase(root
=root
, mdwndb
=mdwndb
)
3745 svp64db
= SVP64Database(root
=root
, ppcdb
=ppcdb
)
3749 opcodes
= _collections
.defaultdict(
3750 lambda: _collections
.defaultdict(set))
3752 for (name
, mdwn
) in mdwndb
:
3753 if name
.startswith("sv."):
3755 (section
, ppc
) = ppcdb
[name
]
3758 svp64
= svp64db
[name
]
3759 fields
= fieldsdb
[ppc
.form
]
3760 record
= Record(name
=name
,
3761 section
=section
, ppc
=ppc
, svp64
=svp64
,
3762 mdwn
=mdwn
, fields
=fields
)
3764 names
[record
.name
] = record
3765 opcodes
[section
][record
.PO
].add(record
)
3767 self
.__db
= sorted(db
)
3768 self
.__names
= dict(sorted(names
.items()))
3769 self
.__opcodes
= dict(sorted(opcodes
.items()))
3771 return super().__init
__()
3774 return repr(self
.__db
)
3777 yield from self
.__db
3779 @_functools.lru_cache(maxsize
=None)
3780 def __contains__(self
, key
):
3781 return self
.__getitem
__(key
) is not None
3783 @_functools.lru_cache(maxsize
=None)
3784 def __getitem__(self
, key
):
3785 if isinstance(key
, SVP64Instruction
):
3788 if isinstance(key
, Instruction
):
3791 sections
= sorted(self
.__opcodes
)
3792 for section
in sections
:
3793 group
= self
.__opcodes
[section
]
3794 for record
in group
[PO
]:
3795 if record
.match(key
=key
):
3800 elif isinstance(key
, str):
3801 return self
.__names
.get(key
)
3803 raise ValueError("instruction or name expected")