1 import collections
as _collections
3 import dataclasses
as _dataclasses
5 import functools
as _functools
6 import itertools
as _itertools
8 import operator
as _operator
9 import pathlib
as _pathlib
13 from functools
import cached_property
15 from cached_property
import cached_property
17 from openpower
.decoder
.power_enums
import (
18 Function
as _Function
,
25 CRIn2Sel
as _CRIn2Sel
,
26 CROutSel
as _CROutSel
,
28 LDSTMode
as _LDSTMode
,
33 SVMaskSrc
as _SVMaskSrc
,
38 SVP64RMMode
as _SVP64RMMode
,
39 SVExtraRegType
as _SVExtraRegType
,
40 SVExtraReg
as _SVExtraReg
,
41 SVP64SubVL
as _SVP64SubVL
,
42 SVP64Pred
as _SVP64Pred
,
43 SVP64PredMode
as _SVP64PredMode
,
44 SVP64Width
as _SVP64Width
,
46 from openpower
.decoder
.selectable_int
import (
47 SelectableInt
as _SelectableInt
,
48 selectconcat
as _selectconcat
,
50 from openpower
.decoder
.power_fields
import (
53 DecodeFields
as _DecodeFields
,
55 from openpower
.decoder
.pseudo
.pagereader
import ISA
as _ISA
58 @_functools.total_ordering
59 class Verbosity(_enum
.Enum
):
62 VERBOSE
= _enum
.auto()
64 def __lt__(self
, other
):
65 if not isinstance(other
, self
.__class
__):
67 return (self
.value
< other
.value
)
70 @_functools.total_ordering
71 class Priority(_enum
.Enum
):
77 def _missing_(cls
, value
):
78 if isinstance(value
, str):
83 return super()._missing
_(value
)
85 def __lt__(self
, other
):
86 if not isinstance(other
, self
.__class
__):
89 # NOTE: the order is inversed, LOW < NORMAL < HIGH
90 return (self
.value
> other
.value
)
93 def dataclass(cls
, record
, keymap
=None, typemap
=None):
97 typemap
= {field
.name
:field
.type for field
in _dataclasses
.fields(cls
)}
99 def transform(key_value
):
100 (key
, value
) = key_value
101 key
= keymap
.get(key
, key
)
102 hook
= typemap
.get(key
, lambda value
: value
)
103 if hook
is bool and value
in ("", "0"):
109 record
= dict(map(transform
, record
.items()))
110 for key
in frozenset(record
.keys()):
111 if record
[key
] == "":
117 @_functools.total_ordering
118 @_dataclasses.dataclass(eq
=True, frozen
=True)
121 def __new__(cls
, value
):
122 if isinstance(value
, str):
123 value
= int(value
, 0)
124 if not isinstance(value
, int):
125 raise ValueError(value
)
127 if value
.bit_length() > 64:
128 raise ValueError(value
)
130 return super().__new
__(cls
, value
)
133 return self
.__repr
__()
136 return f
"{self:0{self.bit_length()}b}"
138 def bit_length(self
):
139 if super().bit_length() > 32:
143 class Value(Integer
):
152 def __lt__(self
, other
):
153 if not isinstance(other
, Opcode
):
154 return NotImplemented
155 return ((self
.value
, self
.mask
) < (other
.value
, other
.mask
))
158 def pattern(value
, mask
, bit_length
):
159 for bit
in range(bit_length
):
160 if ((mask
& (1 << (bit_length
- bit
- 1))) == 0):
162 elif (value
& (1 << (bit_length
- bit
- 1))):
167 return "".join(pattern(self
.value
, self
.mask
, self
.value
.bit_length()))
169 def match(self
, key
):
170 return ((self
.value
& self
.mask
) == (key
& self
.mask
))
173 class IntegerOpcode(Opcode
):
174 def __init__(self
, value
):
175 if value
.startswith("0b"):
176 mask
= int(("1" * len(value
[2:])), 2)
180 value
= Opcode
.Value(value
)
181 mask
= Opcode
.Mask(mask
)
183 return super().__init
__(value
=value
, mask
=mask
)
186 class PatternOpcode(Opcode
):
187 def __init__(self
, pattern
):
188 if not isinstance(pattern
, str):
189 raise ValueError(pattern
)
191 (value
, mask
) = (0, 0)
192 for symbol
in pattern
:
193 if symbol
not in {"0", "1", "-"}:
194 raise ValueError(pattern
)
195 value |
= (symbol
== "1")
196 mask |
= (symbol
!= "-")
202 value
= Opcode
.Value(value
)
203 mask
= Opcode
.Mask(mask
)
205 return super().__init
__(value
=value
, mask
=mask
)
208 @_dataclasses.dataclass(eq
=True, frozen
=True)
210 class FlagsMeta(type):
225 class Flags(frozenset, metaclass
=FlagsMeta
):
226 def __new__(cls
, flags
=frozenset()):
227 flags
= frozenset(flags
)
228 diff
= (flags
- frozenset(cls
))
230 raise ValueError(flags
)
231 return super().__new
__(cls
, flags
)
235 flags
: Flags
= Flags()
237 function
: _Function
= _Function
.NONE
238 intop
: _MicrOp
= _MicrOp
.OP_ILLEGAL
239 in1
: _In1Sel
= _In1Sel
.RA
240 in2
: _In2Sel
= _In2Sel
.NONE
241 in3
: _In3Sel
= _In3Sel
.NONE
242 out
: _OutSel
= _OutSel
.NONE
243 cr_in
: _CRInSel
= _CRInSel
.NONE
244 cr_in2
: _CRIn2Sel
= _CRIn2Sel
.NONE
245 cr_out
: _CROutSel
= _CROutSel
.NONE
246 cry_in
: _CryIn
= _CryIn
.ZERO
247 ldst_len
: _LDSTLen
= _LDSTLen
.NONE
248 upd
: _LDSTMode
= _LDSTMode
.NONE
249 Rc
: _RCOE
= _RCOE
.NONE
250 form
: _Form
= _Form
.NONE
252 unofficial
: bool = False
256 "internal op": "intop",
260 "ldst len": "ldst_len",
262 "CONDITIONS": "conditions",
265 def __lt__(self
, other
):
266 if not isinstance(other
, self
.__class
__):
267 return NotImplemented
268 lhs
= (self
.opcode
, self
.comment
)
269 rhs
= (other
.opcode
, other
.comment
)
273 def CSV(cls
, record
, opcode_cls
):
274 typemap
= {field
.name
:field
.type for field
in _dataclasses
.fields(cls
)}
275 typemap
["opcode"] = opcode_cls
277 if record
["CR in"] == "BA_BB":
278 record
["cr_in"] = "BA"
279 record
["cr_in2"] = "BB"
283 for flag
in frozenset(PPCRecord
.Flags
):
284 if bool(record
.pop(flag
, "")):
286 record
["flags"] = PPCRecord
.Flags(flags
)
288 return dataclass(cls
, record
,
289 keymap
=PPCRecord
.__KEYMAP
,
294 return frozenset(self
.comment
.split("=")[-1].split("/"))
297 class PPCMultiRecord(tuple):
298 def __getattr__(self
, attr
):
300 raise AttributeError(attr
)
301 return getattr(self
[0], attr
)
304 @_dataclasses.dataclass(eq
=True, frozen
=True)
306 class ExtraMap(tuple):
308 @_dataclasses.dataclass(eq
=True, frozen
=True)
310 regtype
: _SVExtraRegType
= _SVExtraRegType
.NONE
311 reg
: _SVExtraReg
= _SVExtraReg
.NONE
314 return f
"{self.regtype.value}:{self.reg.name}"
316 def __new__(cls
, value
="0"):
317 if isinstance(value
, str):
318 def transform(value
):
319 (regtype
, reg
) = value
.split(":")
320 regtype
= _SVExtraRegType(regtype
)
321 reg
= _SVExtraReg(reg
)
322 return cls
.Entry(regtype
=regtype
, reg
=reg
)
327 value
= map(transform
, value
.split(";"))
329 return super().__new
__(cls
, value
)
332 return repr(list(self
))
334 def __new__(cls
, value
=tuple()):
338 return super().__new
__(cls
, map(cls
.Extra
, value
))
341 return repr({index
:self
[index
] for index
in range(0, 4)})
344 ptype
: _SVPType
= _SVPType
.NONE
345 etype
: _SVEType
= _SVEType
.NONE
346 msrc
: _SVMaskSrc
= _SVMaskSrc
.NO
# MASK_SRC is active
347 in1
: _In1Sel
= _In1Sel
.NONE
348 in2
: _In2Sel
= _In2Sel
.NONE
349 in3
: _In3Sel
= _In3Sel
.NONE
350 out
: _OutSel
= _OutSel
.NONE
351 out2
: _OutSel
= _OutSel
.NONE
352 cr_in
: _CRInSel
= _CRInSel
.NONE
353 cr_in2
: _CRIn2Sel
= _CRIn2Sel
.NONE
354 cr_out
: _CROutSel
= _CROutSel
.NONE
355 extra
: ExtraMap
= ExtraMap()
357 mode
: _SVMode
= _SVMode
.NORMAL
361 "CONDITIONS": "conditions",
370 def CSV(cls
, record
):
371 for key
in frozenset({
372 "in1", "in2", "in3", "CR in",
373 "out", "out2", "CR out",
379 if record
["CR in"] == "BA_BB":
380 record
["cr_in"] = "BA"
381 record
["cr_in2"] = "BB"
385 for idx
in range(0, 4):
386 extra
.append(record
.pop(f
"{idx}"))
388 record
["extra"] = cls
.ExtraMap(extra
)
390 return dataclass(cls
, record
, keymap
=cls
.__KEYMAP
)
392 @_functools.lru_cache(maxsize
=None)
393 def extra_idx(self
, key
):
401 if key
not in frozenset({
402 "in1", "in2", "in3", "cr_in", "cr_in2",
403 "out", "out2", "cr_out",
407 sel
= getattr(self
, key
)
408 if sel
is _CRInSel
.BA_BB
:
409 return _SVExtra
.Idx_1_2
410 reg
= _SVExtraReg(sel
)
411 if reg
is _SVExtraReg
.NONE
:
415 _SVExtraRegType
.SRC
: {},
416 _SVExtraRegType
.DST
: {},
418 for index
in range(0, 4):
419 for entry
in self
.extra
[index
]:
420 extra_map
[entry
.regtype
][entry
.reg
] = extra_idx
[index
]
422 for regtype
in (_SVExtraRegType
.SRC
, _SVExtraRegType
.DST
):
423 extra
= extra_map
[regtype
].get(reg
, _SVExtra
.NONE
)
424 if extra
is not _SVExtra
.NONE
:
429 extra_idx_in1
= property(_functools
.partial(extra_idx
, key
="in1"))
430 extra_idx_in2
= property(_functools
.partial(extra_idx
, key
="in2"))
431 extra_idx_in3
= property(_functools
.partial(extra_idx
, key
="in3"))
432 extra_idx_out
= property(_functools
.partial(extra_idx
, key
="out"))
433 extra_idx_out2
= property(_functools
.partial(extra_idx
, key
="out2"))
434 extra_idx_cr_in
= property(_functools
.partial(extra_idx
, key
="cr_in"))
435 extra_idx_cr_in2
= property(_functools
.partial(extra_idx
, key
="cr_in2"))
436 extra_idx_cr_out
= property(_functools
.partial(extra_idx
, key
="cr_out"))
438 @_functools.lru_cache(maxsize
=None)
439 def extra_reg(self
, key
):
440 return _SVExtraReg(getattr(self
, key
))
442 extra_reg_in1
= property(_functools
.partial(extra_reg
, key
="in1"))
443 extra_reg_in2
= property(_functools
.partial(extra_reg
, key
="in2"))
444 extra_reg_in3
= property(_functools
.partial(extra_reg
, key
="in3"))
445 extra_reg_out
= property(_functools
.partial(extra_reg
, key
="out"))
446 extra_reg_out2
= property(_functools
.partial(extra_reg
, key
="out2"))
447 extra_reg_cr_in
= property(_functools
.partial(extra_reg
, key
="cr_in"))
448 extra_reg_cr_in2
= property(_functools
.partial(extra_reg
, key
="cr_in2"))
449 extra_reg_cr_out
= property(_functools
.partial(extra_reg
, key
="cr_out"))
454 for idx
in range(0, 4):
455 for entry
in self
.svp64
.extra
[idx
]:
456 if entry
.regtype
is _SVExtraRegType
.DST
:
457 if regtype
is not None:
458 raise ValueError(self
.svp64
)
459 regtype
= _RegType(entry
.reg
)
460 if regtype
not in (_RegType
.CR_5BIT
, _RegType
.CR_3BIT
):
461 raise ValueError(self
.svp64
)
462 return (regtype
is _RegType
.CR_3BIT
)
466 def __init__(self
, value
=(0, 32)):
467 if isinstance(value
, str):
468 (start
, end
) = map(int, value
.split(":"))
471 if start
< 0 or end
< 0 or start
>= end
:
472 raise ValueError(value
)
477 return super().__init
__()
480 return (self
.__end
- self
.__start
+ 1)
483 return f
"[{self.__start}:{self.__end}]"
486 yield from range(self
.start
, (self
.end
+ 1))
488 def __reversed__(self
):
489 return tuple(reversed(tuple(self
)))
500 @_dataclasses.dataclass(eq
=True, frozen
=True)
502 class Mode(_enum
.Enum
):
503 INTEGER
= _enum
.auto()
504 PATTERN
= _enum
.auto()
507 def _missing_(cls
, value
):
508 if isinstance(value
, str):
509 return cls
[value
.upper()]
510 return super()._missing
_(value
)
513 def __new__(cls
, value
=None):
514 if isinstance(value
, str):
515 if value
.upper() == "NONE":
518 value
= int(value
, 0)
522 return super().__new
__(cls
, value
)
528 return (bin(self
) if self
else "None")
534 opcode
: IntegerOpcode
= None
535 priority
: Priority
= Priority
.NORMAL
537 def __lt__(self
, other
):
538 if not isinstance(other
, self
.__class
__):
539 return NotImplemented
540 return (self
.priority
< other
.priority
)
543 def CSV(cls
, record
):
544 typemap
= {field
.name
:field
.type for field
in _dataclasses
.fields(cls
)}
545 if record
["opcode"] == "NONE":
546 typemap
["opcode"] = lambda _
: None
548 return dataclass(cls
, record
, typemap
=typemap
)
552 def __init__(self
, items
):
553 if isinstance(items
, dict):
554 items
= items
.items()
557 (name
, bitrange
) = item
558 return (name
, tuple(bitrange
.values()))
560 self
.__mapping
= dict(map(transform
, items
))
562 return super().__init
__()
565 return repr(self
.__mapping
)
568 yield from self
.__mapping
.items()
570 def __contains__(self
, key
):
571 return self
.__mapping
.__contains
__(key
)
573 def __getitem__(self
, key
):
574 return self
.__mapping
.get(key
, None)
578 def __init__(self
, insn
, iterable
):
580 "b": {"target_addr": TargetAddrOperandLI
},
581 "ba": {"target_addr": TargetAddrOperandLI
},
582 "bl": {"target_addr": TargetAddrOperandLI
},
583 "bla": {"target_addr": TargetAddrOperandLI
},
584 "bc": {"target_addr": TargetAddrOperandBD
},
585 "bca": {"target_addr": TargetAddrOperandBD
},
586 "bcl": {"target_addr": TargetAddrOperandBD
},
587 "bcla": {"target_addr": TargetAddrOperandBD
},
588 "addpcis": {"D": DOperandDX
},
589 "fishmv": {"D": DOperandDX
},
590 "fmvis": {"D": DOperandDX
},
593 "SVi": NonZeroOperand
,
594 "SVd": NonZeroOperand
,
595 "SVxd": NonZeroOperand
,
596 "SVyd": NonZeroOperand
,
597 "SVzd": NonZeroOperand
,
599 "D": SignedImmediateOperand
,
603 "SIM": SignedOperand
,
604 "SVD": SignedOperand
,
605 "SVDS": SignedOperand
,
607 custom_immediates
= {
613 for operand
in iterable
:
617 (name
, value
) = operand
.split("=")
618 mapping
[name
] = (StaticOperand
, {
624 if name
.endswith(")"):
625 name
= name
.replace("(", " ").replace(")", "")
626 (immediate
, _
, name
) = name
.partition(" ")
630 if immediate
is not None:
631 cls
= custom_immediates
.get(immediate
, ImmediateOperand
)
633 if insn
in custom_insns
and name
in custom_insns
[insn
]:
634 cls
= custom_insns
[insn
][name
]
635 elif name
in custom_fields
:
636 cls
= custom_fields
[name
]
638 if name
in _RegType
.__members
__:
639 regtype
= _RegType
[name
]
640 if regtype
is _RegType
.GPR
:
642 elif regtype
is _RegType
.FPR
:
644 if regtype
is _RegType
.CR_5BIT
:
646 if regtype
is _RegType
.CR_3BIT
:
649 mapping
[name
] = (cls
, {"name": name
})
653 for (name
, (cls
, kwargs
)) in mapping
.items():
654 kwargs
= dict(kwargs
)
655 kwargs
["name"] = name
656 if issubclass(cls
, StaticOperand
):
657 static
.append((cls
, kwargs
))
658 elif issubclass(cls
, DynamicOperand
):
659 dynamic
.append((cls
, kwargs
))
661 raise ValueError(name
)
663 self
.__mapping
= mapping
664 self
.__static
= tuple(static
)
665 self
.__dynamic
= tuple(dynamic
)
667 return super().__init
__()
670 for (_
, items
) in self
.__mapping
.items():
671 (cls
, kwargs
) = items
675 return self
.__mapping
.__repr
__()
677 def __contains__(self
, key
):
678 return self
.__mapping
.__contains
__(key
)
680 def __getitem__(self
, key
):
681 return self
.__mapping
.__getitem
__(key
)
689 return self
.__dynamic
693 def __init__(self
, iterable
):
694 self
.__pcode
= tuple(iterable
)
695 return super().__init
__()
698 yield from self
.__pcode
701 return self
.__pcode
.__repr
__()
704 @_dataclasses.dataclass(eq
=True, frozen
=True)
705 class MarkdownRecord
:
710 @_functools.total_ordering
711 @_dataclasses.dataclass(eq
=True, frozen
=True)
718 svp64
: SVP64Record
= None
720 def __lt__(self
, other
):
721 if not isinstance(other
, Record
):
722 return NotImplemented
723 lhs
= (min(self
.opcodes
), self
.name
)
724 rhs
= (min(other
.opcodes
), other
.name
)
729 PO
= self
.section
.opcode
731 assert len(self
.ppc
) == 1
732 PO
= self
.ppc
[0].opcode
734 return POStaticOperand(record
=self
,
735 name
="PO", value
=int(PO
.value
), mask
=int(PO
.mask
))
741 PO
= self
.section
.opcode
747 return XOStaticOperand(record
=self
,
748 name
="XO", value
=0, mask
=0)
750 return XOStaticOperand(record
=self
,
751 name
="XO", value
=int(XO
.value
), mask
=int(XO
.mask
))
753 return tuple(dict.fromkeys(map(XO
, self
.ppc
)))
756 def static_operands(self
):
759 operands
.append(self
.PO
)
760 operands
.extend(self
.XO
)
762 for (cls
, kwargs
) in self
.mdwn
.operands
.static
:
763 operands
.append(cls(record
=self
, **kwargs
))
765 return tuple(operands
)
768 def dynamic_operands(self
):
771 for (cls
, kwargs
) in self
.mdwn
.operands
.dynamic
:
772 operands
.append(cls(record
=self
, **kwargs
))
774 return tuple(operands
)
779 if self
.svp64
is not None:
781 origin_value
= ([0] * bits
)
782 origin_mask
= ([0] * bits
)
784 for operand
in ((self
.PO
,) + tuple(self
.static_operands
)):
785 for (src
, dst
) in enumerate(reversed(operand
.span
)):
786 origin_value
[dst
] = int((operand
.value
& (1 << src
)) != 0)
790 value
= list(origin_value
)
791 mask
= list(origin_mask
)
792 for (src
, dst
) in enumerate(reversed(XO
.span
)):
793 value
[dst
] = int((XO
.value
& (1 << src
)) != 0)
796 value
= Opcode
.Value(int(("".join(map(str, value
))), 2))
797 mask
= Opcode
.Mask(int(("".join(map(str, mask
))), 2))
799 return Opcode(value
=value
, mask
=mask
)
801 return tuple(dict.fromkeys(map(opcode
, self
.XO
)))
803 def match(self
, key
):
804 for opcode
in self
.opcodes
:
805 if opcode
.match(key
):
812 return self
.svp64
.mode
832 if self
.svp64
is None:
838 return self
.ppc
.cr_in
842 return self
.ppc
.cr_in2
846 return self
.ppc
.cr_out
848 ptype
= property(lambda self
: self
.svp64
.ptype
)
849 etype
= property(lambda self
: self
.svp64
.etype
)
851 def extra_idx(self
, key
):
852 return self
.svp64
.extra_idx(key
)
854 extra_idx_in1
= property(lambda self
: self
.svp64
.extra_idx_in1
)
855 extra_idx_in2
= property(lambda self
: self
.svp64
.extra_idx_in2
)
856 extra_idx_in3
= property(lambda self
: self
.svp64
.extra_idx_in3
)
857 extra_idx_out
= property(lambda self
: self
.svp64
.extra_idx_out
)
858 extra_idx_out2
= property(lambda self
: self
.svp64
.extra_idx_out2
)
859 extra_idx_cr_in
= property(lambda self
: self
.svp64
.extra_idx_cr_in
)
860 extra_idx_cr_in2
= property(lambda self
: self
.svp64
.extra_idx_cr_in2
)
861 extra_idx_cr_out
= property(lambda self
: self
.svp64
.extra_idx_cr_out
)
863 def __contains__(self
, key
):
864 return self
.mdwn
.operands
.__contains
__(key
)
866 def __getitem__(self
, key
):
867 (cls
, kwargs
) = self
.mdwn
.operands
.__getitem
__(key
)
868 return cls(record
=self
, **kwargs
)
874 return self
["Rc"].value
877 @_dataclasses.dataclass(eq
=True, frozen
=True)
880 record
: Record
= _dataclasses
.field(repr=False)
882 def __post_init__(self
):
887 span
= self
.record
.fields
[self
.name
]
888 if self
.record
.svp64
is not None:
889 span
= tuple(map(lambda bit
: (bit
+ 32), span
))
892 def assemble(self
, value
, insn
):
894 if isinstance(value
, str):
895 value
= int(value
, 0)
897 raise ValueError("signed operands not allowed")
900 def disassemble(self
, insn
,
901 verbosity
=Verbosity
.NORMAL
, indent
=""):
902 raise NotImplementedError
905 @_dataclasses.dataclass(eq
=True, frozen
=True)
906 class DynamicOperand(Operand
):
907 def disassemble(self
, insn
,
908 verbosity
=Verbosity
.NORMAL
, indent
=""):
912 if verbosity
>= Verbosity
.VERBOSE
:
913 span
= map(str, span
)
914 yield f
"{indent}{self.name}"
915 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
916 yield f
"{indent}{indent}{', '.join(span)}"
918 yield str(int(value
))
921 @_dataclasses.dataclass(eq
=True, frozen
=True)
922 class SignedOperand(DynamicOperand
):
923 def assemble(self
, value
, insn
):
924 if isinstance(value
, str):
925 value
= int(value
, 0)
926 return super().assemble(value
=value
, insn
=insn
)
928 def assemble(self
, value
, insn
):
930 if isinstance(value
, str):
931 value
= int(value
, 0)
934 def disassemble(self
, insn
,
935 verbosity
=Verbosity
.NORMAL
, indent
=""):
939 if verbosity
>= Verbosity
.VERBOSE
:
940 span
= map(str, span
)
941 yield f
"{indent}{self.name}"
942 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
943 yield f
"{indent}{indent}{', '.join(span)}"
945 yield str(value
.to_signed_int())
948 @_dataclasses.dataclass(eq
=True, frozen
=True)
949 class StaticOperand(Operand
):
952 def assemble(self
, insn
):
953 return super().assemble(value
=self
.value
, insn
=insn
)
955 def disassemble(self
, insn
,
956 verbosity
=Verbosity
.NORMAL
, indent
=""):
960 if verbosity
>= Verbosity
.VERBOSE
:
961 span
= map(str, span
)
962 yield f
"{indent}{self.name}"
963 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
964 yield f
"{indent}{indent}{', '.join(span)}"
966 yield str(int(value
))
969 @_dataclasses.dataclass(eq
=True, frozen
=True)
970 class POStaticOperand(StaticOperand
):
975 span
= tuple(range(0, 6))
976 if self
.record
.svp64
is not None:
977 span
= tuple(map(lambda bit
: (bit
+ 32), span
))
981 @_dataclasses.dataclass(eq
=True, frozen
=True)
982 class XOStaticOperand(StaticOperand
):
985 def __post_init__(self
):
986 if self
.record
.section
.opcode
is None:
987 assert self
.value
== 0
988 assert self
.mask
== 0
989 object.__setattr
__(self
, "span", ())
992 bits
= self
.record
.section
.bitsel
993 value
= _SelectableInt(value
=self
.value
, bits
=len(bits
))
994 span
= dict(zip(bits
, range(len(bits
))))
995 span_rev
= {value
:key
for (key
, value
) in span
.items()}
997 # This part is tricky: we could have used self.record.static_operands,
998 # but this would cause an infinite recursion, since this code is called
999 # from the self.record.static_operands method already.
1001 operands
.extend(self
.record
.mdwn
.operands
.static
)
1002 operands
.extend(self
.record
.mdwn
.operands
.dynamic
)
1003 for (cls
, kwargs
) in operands
:
1004 operand
= cls(record
=self
.record
, **kwargs
)
1005 for idx
in operand
.span
:
1006 rev
= span
.pop(idx
, None)
1008 span_rev
.pop(rev
, None)
1010 # This part is simpler: we drop bits which are not in the mask.
1011 for bit
in tuple(span
.values()):
1012 rev
= (len(bits
) - bit
- 1)
1013 if ((self
.mask
& (1 << bit
)) == 0):
1014 idx
= span_rev
.pop(rev
, None)
1018 value
= int(_selectconcat(*(value
[bit
] for bit
in span
.values())))
1019 span
= tuple(span
.keys())
1020 if self
.record
.svp64
is not None:
1021 span
= tuple(map(lambda bit
: (bit
+ 32), span
))
1023 object.__setattr
__(self
, "value", value
)
1024 object.__setattr
__(self
, "span", span
)
1026 return super().__post
_init
__()
1029 @_dataclasses.dataclass(eq
=True, frozen
=True)
1030 class ImmediateOperand(DynamicOperand
):
1034 @_dataclasses.dataclass(eq
=True, frozen
=True)
1035 class SignedImmediateOperand(SignedOperand
, ImmediateOperand
):
1039 @_dataclasses.dataclass(eq
=True, frozen
=True)
1040 class NonZeroOperand(DynamicOperand
):
1041 def assemble(self
, value
, insn
):
1042 if isinstance(value
, str):
1043 value
= int(value
, 0)
1044 if not isinstance(value
, int):
1045 raise ValueError("non-integer operand")
1047 return super().assemble(value
=value
, insn
=insn
)
1049 def disassemble(self
, insn
,
1050 verbosity
=Verbosity
.NORMAL
, indent
=""):
1054 if verbosity
>= Verbosity
.VERBOSE
:
1055 span
= map(str, span
)
1056 yield f
"{indent}{self.name}"
1057 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
1058 yield f
"{indent}{indent}{', '.join(span)}"
1060 yield str(int(value
) + 1)
1063 @_dataclasses.dataclass(eq
=True, frozen
=True)
1064 class ExtendableOperand(DynamicOperand
):
1065 def sv_spec_enter(self
, value
, span
):
1066 return (value
, span
)
1068 def sv_spec_leave(self
, value
, span
, origin_value
, origin_span
):
1069 return (value
, span
)
1071 def spec(self
, insn
):
1075 span
= tuple(map(str, span
))
1077 if isinstance(insn
, SVP64Instruction
):
1078 (origin_value
, origin_span
) = (value
, span
)
1079 (value
, span
) = self
.sv_spec_enter(value
=value
, span
=span
)
1081 extra_idx
= self
.extra_idx
1082 if extra_idx
is _SVExtra
.NONE
:
1083 return (vector
, value
, span
)
1085 if self
.record
.etype
is _SVEType
.EXTRA3
:
1086 spec
= insn
.prefix
.rm
.extra3
[extra_idx
]
1087 elif self
.record
.etype
is _SVEType
.EXTRA2
:
1088 spec
= insn
.prefix
.rm
.extra2
[extra_idx
]
1090 raise ValueError(self
.record
.etype
)
1093 vector
= bool(spec
[0])
1094 spec_span
= spec
.__class
__
1095 if self
.record
.etype
is _SVEType
.EXTRA3
:
1096 spec_span
= tuple(map(str, spec_span
[1, 2]))
1098 elif self
.record
.etype
is _SVEType
.EXTRA2
:
1099 spec_span
= tuple(map(str, spec_span
[1,]))
1100 spec
= _SelectableInt(value
=spec
[1].value
, bits
=2)
1103 spec_span
= (spec_span
+ ("{0}",))
1105 spec_span
= (("{0}",) + spec_span
)
1107 raise ValueError(self
.record
.etype
)
1109 vector_shift
= (2 + (5 - value
.bits
))
1110 scalar_shift
= value
.bits
1111 spec_shift
= (5 - value
.bits
)
1113 bits
= (len(span
) + len(spec_span
))
1114 value
= _SelectableInt(value
=value
.value
, bits
=bits
)
1115 spec
= _SelectableInt(value
=spec
.value
, bits
=bits
)
1117 value
= ((value
<< vector_shift
) |
(spec
<< spec_shift
))
1118 span
= (span
+ spec_span
+ ((spec_shift
* ("{0}",))))
1120 value
= ((spec
<< scalar_shift
) | value
)
1121 span
= ((spec_shift
* ("{0}",)) + spec_span
+ span
)
1123 (value
, span
) = self
.sv_spec_leave(value
=value
, span
=span
,
1124 origin_value
=origin_value
, origin_span
=origin_span
)
1126 return (vector
, value
, span
)
1129 def extra_reg(self
):
1130 return _SVExtraReg(self
.name
)
1133 def extra_idx(self
):
1134 for key
in frozenset({
1135 "in1", "in2", "in3", "cr_in", "cr_in2",
1136 "out", "out2", "cr_out",
1138 extra_reg
= self
.record
.svp64
.extra_reg(key
=key
)
1139 if extra_reg
is self
.extra_reg
:
1140 return self
.record
.extra_idx(key
=key
)
1142 return _SVExtra
.NONE
1144 def remap(self
, value
, vector
):
1145 raise NotImplementedError
1147 def assemble(self
, value
, insn
, prefix
):
1150 if isinstance(value
, str):
1151 value
= value
.lower()
1152 if value
.startswith("%"):
1154 if value
.startswith("*"):
1155 if not isinstance(insn
, SVP64Instruction
):
1156 raise ValueError(value
)
1159 if value
.startswith(prefix
):
1160 value
= value
[len(prefix
):]
1161 value
= int(value
, 0)
1163 if isinstance(insn
, SVP64Instruction
):
1164 (value
, extra
) = self
.remap(value
=value
, vector
=vector
)
1166 extra_idx
= self
.extra_idx
1167 if extra_idx
is _SVExtra
.NONE
:
1168 raise ValueError(self
.record
)
1170 if self
.record
.etype
is _SVEType
.EXTRA3
:
1171 insn
.prefix
.rm
.extra3
[extra_idx
] = extra
1172 elif self
.record
.etype
is _SVEType
.EXTRA2
:
1173 insn
.prefix
.rm
.extra2
[extra_idx
] = extra
1175 raise ValueError(self
.record
.etype
)
1177 return super().assemble(value
=value
, insn
=insn
)
1179 return super().assemble(value
=value
, insn
=insn
)
1181 def disassemble(self
, insn
,
1182 verbosity
=Verbosity
.NORMAL
, prefix
="", indent
=""):
1183 (vector
, value
, span
) = self
.spec(insn
=insn
)
1185 if verbosity
>= Verbosity
.VERBOSE
:
1186 mode
= "vector" if vector
else "scalar"
1187 yield f
"{indent}{self.name} ({mode})"
1188 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
1189 yield f
"{indent}{indent}{', '.join(span)}"
1190 if isinstance(insn
, SVP64Instruction
):
1191 extra_idx
= self
.extra_idx
1192 if self
.record
.etype
is _SVEType
.NONE
:
1193 yield f
"{indent}{indent}extra[none]"
1195 etype
= repr(self
.record
.etype
).lower()
1196 yield f
"{indent}{indent}{etype}{extra_idx!r}"
1198 vector
= "*" if vector
else ""
1199 yield f
"{vector}{prefix}{int(value)}"
1202 @_dataclasses.dataclass(eq
=True, frozen
=True)
1203 class SimpleRegisterOperand(ExtendableOperand
):
1204 def remap(self
, value
, vector
):
1206 extra
= (value
& 0b11)
1207 value
= (value
>> 2)
1209 extra
= (value
>> 5)
1210 value
= (value
& 0b11111)
1212 # now sanity-check. EXTRA3 is ok, EXTRA2 has limits
1213 # (and shrink to a single bit if ok)
1214 if self
.record
.etype
is _SVEType
.EXTRA2
:
1216 # range is r0-r127 in increments of 2 (r0 r2 ... r126)
1217 assert (extra
& 0b01) == 0, \
1218 ("vector field %s cannot fit into EXTRA2" % value
)
1219 extra
= (0b10 |
(extra
>> 1))
1221 # range is r0-r63 in increments of 1
1222 assert (extra
>> 1) == 0, \
1223 ("scalar GPR %d cannot fit into EXTRA2" % value
)
1225 elif self
.record
.etype
is _SVEType
.EXTRA3
:
1227 # EXTRA3 vector bit needs marking
1230 raise ValueError(self
.record
.etype
)
1232 return (value
, extra
)
1235 @_dataclasses.dataclass(eq
=True, frozen
=True)
1236 class GPROperand(SimpleRegisterOperand
):
1237 def assemble(self
, value
, insn
):
1238 return super().assemble(value
=value
, insn
=insn
, prefix
="r")
1240 def disassemble(self
, insn
,
1241 verbosity
=Verbosity
.NORMAL
, indent
=""):
1242 prefix
= "" if (verbosity
<= Verbosity
.SHORT
) else "r"
1243 yield from super().disassemble(prefix
=prefix
, insn
=insn
,
1244 verbosity
=verbosity
, indent
=indent
)
1247 @_dataclasses.dataclass(eq
=True, frozen
=True)
1248 class FPROperand(SimpleRegisterOperand
):
1249 def assemble(self
, value
, insn
):
1250 return super().assemble(value
=value
, insn
=insn
, prefix
="f")
1252 def disassemble(self
, insn
,
1253 verbosity
=Verbosity
.NORMAL
, indent
=""):
1254 prefix
= "" if (verbosity
<= Verbosity
.SHORT
) else "f"
1255 yield from super().disassemble(prefix
=prefix
, insn
=insn
,
1256 verbosity
=verbosity
, indent
=indent
)
1259 @_dataclasses.dataclass(eq
=True, frozen
=True)
1260 class ConditionRegisterFieldOperand(ExtendableOperand
):
1261 def pattern(name_pattern
):
1262 (name
, pattern
) = name_pattern
1263 return (name
, _re
.compile(f
"^{pattern}$", _re
.S
))
1272 CR
= r
"(?:CR|cr)([0-9]+)"
1274 BIT
= rf
"({'|'.join(CONDS.keys())})"
1275 LBIT
= fr
"{BIT}\s*\+\s*" # BIT+
1276 RBIT
= fr
"\s*\+\s*{BIT}" # +BIT
1277 CRN
= fr
"{CR}\s*\*\s*{N}" # CR*N
1278 NCR
= fr
"{N}\s*\*\s*{CR}" # N*CR
1279 XCR
= fr
"{CR}\.{BIT}"
1280 PATTERNS
= tuple(map(pattern
, (
1285 ("BIT+CR", (LBIT
+ CR
)),
1286 ("CR+BIT", (CR
+ RBIT
)),
1287 ("BIT+CR*N", (LBIT
+ CRN
)),
1288 ("CR*N+BIT", (CRN
+ RBIT
)),
1289 ("BIT+N*CR", (LBIT
+ NCR
)),
1290 ("N*CR+BIT", (NCR
+ RBIT
)),
1293 def remap(self
, value
, vector
, regtype
):
1294 if regtype
is _RegType
.CR_5BIT
:
1295 subvalue
= (value
& 0x3)
1299 extra
= (value
& 0xf)
1302 extra
= (value
>> 3)
1305 if self
.record
.etype
is _SVEType
.EXTRA2
:
1307 assert (extra
& 0x7) == 0, \
1308 "vector CR cannot fit into EXTRA2"
1309 extra
= (0x2 |
(extra
>> 3))
1311 assert (extra
>> 1) == 0, \
1312 "scalar CR cannot fit into EXTRA2"
1314 elif self
.record
.etype
is _SVEType
.EXTRA3
:
1316 assert (extra
& 0x3) == 0, \
1317 "vector CR cannot fit into EXTRA3"
1318 extra
= (0x4 |
(extra
>> 2))
1320 assert (extra
>> 2) == 0, \
1321 "scalar CR cannot fit into EXTRA3"
1324 if regtype
is _RegType
.CR_5BIT
:
1325 value
= ((value
<< 2) | subvalue
)
1327 return (value
, extra
)
1329 def assemble(self
, value
, insn
):
1330 if isinstance(value
, str):
1333 if value
.startswith("*"):
1334 if not isinstance(insn
, SVP64Instruction
):
1335 raise ValueError(value
)
1339 for (name
, pattern
) in reversed(self
.__class
__.PATTERNS
):
1340 match
= pattern
.match(value
)
1341 if match
is not None:
1342 keys
= name
.replace("+", "_").replace("*", "_").split("_")
1343 values
= match
.groups()
1344 match
= dict(zip(keys
, values
))
1345 CR
= int(match
["CR"])
1349 N
= int(match
.get("N", "1"))
1350 BIT
= self
.__class
__.CONDS
[match
.get("BIT", "lt")]
1351 value
= ((CR
* N
) + BIT
)
1354 return super().assemble(value
=value
, insn
=insn
, prefix
="cr")
1356 def disassemble(self
, insn
,
1357 verbosity
=Verbosity
.NORMAL
, prefix
="", indent
=""):
1358 (vector
, value
, span
) = self
.spec(insn
=insn
)
1360 if verbosity
>= Verbosity
.VERBOSE
:
1361 mode
= "vector" if vector
else "scalar"
1362 yield f
"{indent}{self.name} ({mode})"
1363 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
1364 yield f
"{indent}{indent}{', '.join(span)}"
1365 if isinstance(insn
, SVP64Instruction
):
1366 extra_idx
= self
.extra_idx
1367 if self
.record
.etype
is _SVEType
.NONE
:
1368 yield f
"{indent}{indent}extra[none]"
1370 etype
= repr(self
.record
.etype
).lower()
1371 yield f
"{indent}{indent}{etype}{extra_idx!r}"
1373 vector
= "*" if vector
else ""
1374 cr
= int(value
>> 2)
1376 cond
= ("lt", "gt", "eq", "so")[cc
]
1377 if verbosity
>= Verbosity
.NORMAL
:
1379 if isinstance(insn
, SVP64Instruction
):
1380 yield f
"{vector}cr{cr}.{cond}"
1382 yield f
"4*cr{cr}+{cond}"
1386 yield f
"{vector}{prefix}{int(value)}"
1389 @_dataclasses.dataclass(eq
=True, frozen
=True)
1390 class CR3Operand(ConditionRegisterFieldOperand
):
1391 def remap(self
, value
, vector
):
1392 return super().remap(value
=value
, vector
=vector
,
1393 regtype
=_RegType
.CR_3BIT
)
1396 @_dataclasses.dataclass(eq
=True, frozen
=True)
1397 class CR5Operand(ConditionRegisterFieldOperand
):
1398 def remap(self
, value
, vector
):
1399 return super().remap(value
=value
, vector
=vector
,
1400 regtype
=_RegType
.CR_5BIT
)
1402 def sv_spec_enter(self
, value
, span
):
1403 value
= _SelectableInt(value
=(value
.value
>> 2), bits
=3)
1404 return (value
, span
)
1406 def sv_spec_leave(self
, value
, span
, origin_value
, origin_span
):
1407 value
= _selectconcat(value
, origin_value
[3:5])
1409 return (value
, span
)
1412 @_dataclasses.dataclass(eq
=True, frozen
=True)
1413 class EXTSOperand(SignedOperand
):
1414 field
: str # real name to report
1415 nz
: int = 0 # number of zeros
1416 fmt
: str = "d" # integer formatter
1418 def __post_init__(self
):
1420 object.__setattr
__(self
, "field", self
.name
)
1424 span
= self
.record
.fields
[self
.field
]
1425 if self
.record
.svp64
is not None:
1426 span
= tuple(map(lambda bit
: (bit
+ 32), span
))
1429 def disassemble(self
, insn
,
1430 verbosity
=Verbosity
.NORMAL
, indent
=""):
1434 if verbosity
>= Verbosity
.VERBOSE
:
1435 span
= (tuple(map(str, span
)) + (("{0}",) * self
.nz
))
1436 zeros
= ("0" * self
.nz
)
1437 hint
= f
"{self.name} = EXTS({self.field} || {zeros})"
1438 yield f
"{indent * 1}{hint}"
1439 yield f
"{indent * 2}{self.field}"
1440 yield f
"{indent * 3}{int(value):0{value.bits}b}{zeros}"
1441 yield f
"{indent * 3}{', '.join(span)}"
1443 value
= _selectconcat(value
,
1444 _SelectableInt(value
=0, bits
=self
.nz
)).to_signed_int()
1445 yield f
"{value:{self.fmt}}"
1448 @_dataclasses.dataclass(eq
=True, frozen
=True)
1449 class TargetAddrOperand(EXTSOperand
):
1454 @_dataclasses.dataclass(eq
=True, frozen
=True)
1455 class TargetAddrOperandLI(TargetAddrOperand
):
1459 @_dataclasses.dataclass(eq
=True, frozen
=True)
1460 class TargetAddrOperandBD(TargetAddrOperand
):
1464 @_dataclasses.dataclass(eq
=True, frozen
=True)
1465 class EXTSOperandDS(EXTSOperand
, ImmediateOperand
):
1470 @_dataclasses.dataclass(eq
=True, frozen
=True)
1471 class EXTSOperandDQ(EXTSOperand
, ImmediateOperand
):
1476 @_dataclasses.dataclass(eq
=True, frozen
=True)
1477 class DOperandDX(SignedOperand
):
1480 cls
= lambda name
: DynamicOperand(record
=self
.record
, name
=name
)
1481 operands
= map(cls
, ("d0", "d1", "d2"))
1482 spans
= map(lambda operand
: operand
.span
, operands
)
1483 span
= sum(spans
, tuple())
1484 if self
.record
.svp64
is not None:
1485 span
= tuple(map(lambda bit
: (bit
+ 32), span
))
1488 def disassemble(self
, insn
,
1489 verbosity
=Verbosity
.NORMAL
, indent
=""):
1493 if verbosity
>= Verbosity
.VERBOSE
:
1500 for (subname
, subspan
) in mapping
.items():
1501 operand
= DynamicOperand(name
=subname
)
1504 span
= map(str, span
)
1505 yield f
"{indent}{indent}{operand.name} = D{subspan}"
1506 yield f
"{indent}{indent}{indent}{int(value):0{value.bits}b}"
1507 yield f
"{indent}{indent}{indent}{', '.join(span)}"
1509 yield str(value
.to_signed_int())
1512 class Instruction(_Mapping
):
1514 def integer(cls
, value
=0, bits
=None, byteorder
="little"):
1515 if isinstance(value
, (int, bytes
)) and not isinstance(bits
, int):
1516 raise ValueError(bits
)
1518 if isinstance(value
, bytes
):
1519 if ((len(value
) * 8) != bits
):
1520 raise ValueError(f
"bit length mismatch")
1521 value
= int.from_bytes(value
, byteorder
=byteorder
)
1523 if isinstance(value
, int):
1524 value
= _SelectableInt(value
=value
, bits
=bits
)
1525 elif isinstance(value
, Instruction
):
1526 value
= value
.storage
1528 if not isinstance(value
, _SelectableInt
):
1529 raise ValueError(value
)
1532 if len(value
) != bits
:
1533 raise ValueError(value
)
1535 value
= _SelectableInt(value
=value
, bits
=bits
)
1537 return cls(storage
=value
)
1540 return hash(int(self
))
1542 def __getitem__(self
, key
):
1543 return self
.storage
.__getitem
__(key
)
1545 def __setitem__(self
, key
, value
):
1546 return self
.storage
.__setitem
__(key
, value
)
1548 def bytes(self
, byteorder
="little"):
1549 nr_bytes
= (len(self
.__class
__) // 8)
1550 return int(self
).to_bytes(nr_bytes
, byteorder
=byteorder
)
1552 def record(self
, db
):
1555 raise KeyError(self
)
1558 def spec(self
, db
, prefix
):
1559 record
= self
.record(db
=db
)
1561 dynamic_operands
= tuple(map(_operator
.itemgetter(0),
1562 self
.dynamic_operands(db
=db
)))
1564 static_operands
= []
1565 for (name
, value
) in self
.static_operands(db
=db
):
1566 static_operands
.append(f
"{name}={value}")
1569 if dynamic_operands
:
1571 operands
+= ",".join(dynamic_operands
)
1574 operands
+= " ".join(static_operands
)
1576 return f
"{prefix}{record.name}{operands}"
1578 def dynamic_operands(self
, db
, verbosity
=Verbosity
.NORMAL
):
1579 record
= self
.record(db
=db
)
1584 for operand
in record
.dynamic_operands
:
1586 value
= " ".join(operand
.disassemble(insn
=self
,
1587 verbosity
=min(verbosity
, Verbosity
.NORMAL
)))
1589 name
= f
"{imm_name}({name})"
1590 value
= f
"{imm_value}({value})"
1592 if isinstance(operand
, ImmediateOperand
):
1599 def static_operands(self
, db
):
1600 record
= self
.record(db
=db
)
1601 for operand
in record
.static_operands
:
1602 yield (operand
.name
, operand
.value
)
1605 def assemble(cls
, db
, opcode
, arguments
=None):
1606 raise NotImplementedError(f
"{cls.__name__}.assemble")
1608 def disassemble(self
, db
,
1610 verbosity
=Verbosity
.NORMAL
):
1611 raise NotImplementedError
1614 class WordInstruction(Instruction
):
1615 _
: _Field
= range(0, 32)
1616 PO
: _Field
= range(0, 6)
1619 def integer(cls
, value
, byteorder
="little"):
1620 return super().integer(bits
=32, value
=value
, byteorder
=byteorder
)
1625 for idx
in range(32):
1626 bit
= int(self
[idx
])
1628 return "".join(map(str, bits
))
1631 def assemble(cls
, db
, opcode
, arguments
=None):
1632 if arguments
is None:
1636 record
= _dataclasses
.replace(record
, svp64
=None)
1637 insn
= cls
.integer(value
=0)
1638 for operand
in record
.static_operands
:
1639 operand
.assemble(insn
=insn
)
1641 dynamic_operands
= tuple(record
.dynamic_operands
)
1642 if len(dynamic_operands
) != len(arguments
):
1643 raise ValueError("operands count mismatch")
1644 for (value
, operand
) in zip(arguments
, dynamic_operands
):
1645 operand
.assemble(value
=value
, insn
=insn
)
1649 def disassemble(self
, db
,
1651 verbosity
=Verbosity
.NORMAL
):
1652 if verbosity
<= Verbosity
.SHORT
:
1655 blob
= self
.bytes(byteorder
=byteorder
)
1656 blob
= " ".join(map(lambda byte
: f
"{byte:02x}", blob
))
1661 yield f
"{blob}.long 0x{int(self):08x}"
1664 operands
= tuple(map(_operator
.itemgetter(1),
1665 self
.dynamic_operands(db
=db
, verbosity
=verbosity
)))
1667 operands
= ",".join(operands
)
1668 yield f
"{blob}{record.name} {operands}"
1670 yield f
"{blob}{record.name}"
1672 if verbosity
>= Verbosity
.VERBOSE
:
1674 binary
= self
.binary
1675 spec
= self
.spec(db
=db
, prefix
="")
1676 yield f
"{indent}spec"
1677 yield f
"{indent}{indent}{spec}"
1678 yield f
"{indent}pcode"
1679 for stmt
in record
.mdwn
.pcode
:
1680 yield f
"{indent}{indent}{stmt}"
1681 yield f
"{indent}binary"
1682 yield f
"{indent}{indent}[0:8] {binary[0:8]}"
1683 yield f
"{indent}{indent}[8:16] {binary[8:16]}"
1684 yield f
"{indent}{indent}[16:24] {binary[16:24]}"
1685 yield f
"{indent}{indent}[24:32] {binary[24:32]}"
1686 yield f
"{indent}opcodes"
1687 for opcode
in record
.opcodes
:
1688 yield f
"{indent}{indent}{opcode!r}"
1689 for (cls
, kwargs
) in record
.mdwn
.operands
:
1690 operand
= cls(record
=record
, **kwargs
)
1691 yield from operand
.disassemble(insn
=self
,
1692 verbosity
=verbosity
, indent
=indent
)
1696 class PrefixedInstruction(Instruction
):
1697 class Prefix(WordInstruction
.remap(range(0, 32))):
1700 class Suffix(WordInstruction
.remap(range(32, 64))):
1703 _
: _Field
= range(64)
1709 def integer(cls
, value
, byteorder
="little"):
1710 return super().integer(bits
=64, value
=value
, byteorder
=byteorder
)
1713 def pair(cls
, prefix
=0, suffix
=0, byteorder
="little"):
1714 def transform(value
):
1715 return WordInstruction
.integer(value
=value
,
1716 byteorder
=byteorder
)[0:32]
1718 (prefix
, suffix
) = map(transform
, (prefix
, suffix
))
1719 value
= _selectconcat(prefix
, suffix
)
1721 return super().integer(bits
=64, value
=value
)
1724 class Mode(_Mapping
):
1725 _
: _Field
= range(0, 5)
1726 sel
: _Field
= (0, 1)
1729 class Extra(_Mapping
):
1730 _
: _Field
= range(0, 9)
1733 class Extra2(Extra
):
1734 idx0
: _Field
= range(0, 2)
1735 idx1
: _Field
= range(2, 4)
1736 idx2
: _Field
= range(4, 6)
1737 idx3
: _Field
= range(6, 8)
1739 def __getitem__(self
, key
):
1745 _SVExtra
.Idx0
: self
.idx0
,
1746 _SVExtra
.Idx1
: self
.idx1
,
1747 _SVExtra
.Idx2
: self
.idx2
,
1748 _SVExtra
.Idx3
: self
.idx3
,
1751 def __setitem__(self
, key
, value
):
1752 self
[key
].assign(value
)
1755 class Extra3(Extra
):
1756 idx0
: _Field
= range(0, 3)
1757 idx1
: _Field
= range(3, 6)
1758 idx2
: _Field
= range(6, 9)
1760 def __getitem__(self
, key
):
1765 _SVExtra
.Idx0
: self
.idx0
,
1766 _SVExtra
.Idx1
: self
.idx1
,
1767 _SVExtra
.Idx2
: self
.idx2
,
1770 def __setitem__(self
, key
, value
):
1771 self
[key
].assign(value
)
1774 class BaseRM(_Mapping
):
1775 _
: _Field
= range(24)
1776 mmode
: _Field
= (0,)
1777 mask
: _Field
= range(1, 4)
1778 elwidth
: _Field
= range(4, 6)
1779 ewsrc
: _Field
= range(6, 8)
1780 subvl
: _Field
= range(8, 10)
1781 mode
: Mode
.remap(range(19, 24))
1782 smask
: _Field
= range(16, 19)
1783 extra
: Extra
.remap(range(10, 19))
1784 extra2
: Extra2
.remap(range(10, 19))
1785 extra3
: Extra3
.remap(range(10, 19))
1787 def specifiers(self
, record
):
1788 subvl
= int(self
.subvl
)
1796 def disassemble(self
, verbosity
=Verbosity
.NORMAL
):
1797 if verbosity
>= Verbosity
.VERBOSE
:
1799 for (name
, span
) in self
.traverse(path
="RM"):
1800 value
= self
.storage
[span
]
1802 yield f
"{indent}{int(value):0{value.bits}b}"
1803 yield f
"{indent}{', '.join(map(str, span))}"
1806 class FFPRRc1BaseRM(BaseRM
):
1807 def specifiers(self
, record
, mode
):
1808 inv
= _SelectableInt(value
=int(self
.inv
), bits
=1)
1809 CR
= _SelectableInt(value
=int(self
.CR
), bits
=2)
1810 mask
= int(_selectconcat(CR
, inv
))
1811 predicate
= PredicateBaseRM
.predicate(True, mask
)
1812 yield f
"{mode}={predicate}"
1814 yield from super().specifiers(record
=record
)
1817 class FFPRRc0BaseRM(BaseRM
):
1818 def specifiers(self
, record
, mode
):
1820 inv
= "~" if self
.inv
else ""
1821 yield f
"{mode}={inv}RC1"
1823 yield from super().specifiers(record
=record
)
1826 class SatBaseRM(BaseRM
):
1827 def specifiers(self
, record
):
1833 yield from super().specifiers(record
=record
)
1836 class ZZBaseRM(BaseRM
):
1837 def specifiers(self
, record
):
1841 yield from super().specifiers(record
=record
)
1844 class ZZCombinedBaseRM(BaseRM
):
1845 def specifiers(self
, record
):
1846 if self
.sz
and self
.dz
:
1853 yield from super().specifiers(record
=record
)
1856 class DZBaseRM(BaseRM
):
1857 def specifiers(self
, record
):
1861 yield from super().specifiers(record
=record
)
1864 class SZBaseRM(BaseRM
):
1865 def specifiers(self
, record
):
1869 yield from super().specifiers(record
=record
)
1872 class MRBaseRM(BaseRM
):
1873 def specifiers(self
, record
):
1879 yield from super().specifiers(record
=record
)
1882 class ElsBaseRM(BaseRM
):
1883 def specifiers(self
, record
):
1887 yield from super().specifiers(record
=record
)
1890 class WidthBaseRM(BaseRM
):
1892 def width(FP
, width
):
1901 width
= ("fp" + width
)
1904 def specifiers(self
, record
):
1905 # elwidths: use "w=" if same otherwise dw/sw
1906 # FIXME this should consider FP instructions
1908 dw
= WidthBaseRM
.width(FP
, int(self
.elwidth
))
1909 sw
= WidthBaseRM
.width(FP
, int(self
.ewsrc
))
1918 yield from super().specifiers(record
=record
)
1921 class PredicateBaseRM(BaseRM
):
1923 def predicate(CR
, mask
):
1926 (False, 0b001): "1<<r3",
1927 (False, 0b010): "r3",
1928 (False, 0b011): "~r3",
1929 (False, 0b100): "r10",
1930 (False, 0b101): "~r10",
1931 (False, 0b110): "r30",
1932 (False, 0b111): "~r30",
1934 (True, 0b000): "lt",
1935 (True, 0b001): "ge",
1936 (True, 0b010): "gt",
1937 (True, 0b011): "le",
1938 (True, 0b100): "eq",
1939 (True, 0b101): "ne",
1940 (True, 0b110): "so",
1941 (True, 0b111): "ns",
1944 def specifiers(self
, record
):
1945 # predication - single and twin
1946 # use "m=" if same otherwise sm/dm
1947 CR
= (int(self
.mmode
) == 1)
1948 mask
= int(self
.mask
)
1949 sm
= dm
= PredicateBaseRM
.predicate(CR
, mask
)
1950 if record
.svp64
.ptype
is _SVPType
.P2
:
1951 smask
= int(self
.smask
)
1952 sm
= PredicateBaseRM
.predicate(CR
, smask
)
1961 yield from super().specifiers(record
=record
)
1964 class PredicateWidthBaseRM(WidthBaseRM
, PredicateBaseRM
):
1968 class SEABaseRM(BaseRM
):
1969 def specifiers(self
, record
):
1973 yield from super().specifiers(record
=record
)
1976 class VLiBaseRM(BaseRM
):
1977 def specifiers(self
, record
):
1981 yield from super().specifiers(record
=record
)
1984 class NormalBaseRM(PredicateWidthBaseRM
):
1987 https://libre-soc.org/openpower/sv/normal/
1992 class NormalSimpleRM(ZZCombinedBaseRM
, NormalBaseRM
):
1993 """normal: simple mode"""
1997 def specifiers(self
, record
):
1998 yield from super().specifiers(record
=record
)
2001 class NormalMRRM(MRBaseRM
, NormalBaseRM
):
2002 """normal: scalar reduce mode (mapreduce), SUBVL=1"""
2006 class NormalFFRc1RM(FFPRRc1BaseRM
, NormalBaseRM
):
2007 """normal: Rc=1: ffirst CR sel"""
2009 CR
: BaseRM
.mode
[3, 4]
2011 def specifiers(self
, record
):
2012 yield from super().specifiers(record
=record
, mode
="ff")
2015 class NormalFFRc0RM(FFPRRc0BaseRM
, VLiBaseRM
, NormalBaseRM
):
2016 """normal: Rc=0: ffirst z/nonz"""
2021 def specifiers(self
, record
):
2022 yield from super().specifiers(record
=record
, mode
="ff")
2025 class NormalSatRM(SatBaseRM
, ZZCombinedBaseRM
, NormalBaseRM
):
2026 """normal: sat mode: N=0/1 u/s, SUBVL=1"""
2032 class NormalPRRc1RM(FFPRRc1BaseRM
, NormalBaseRM
):
2033 """normal: Rc=1: pred-result CR sel"""
2035 CR
: BaseRM
.mode
[3, 4]
2037 def specifiers(self
, record
):
2038 yield from super().specifiers(record
=record
, mode
="pr")
2041 class NormalPRRc0RM(FFPRRc0BaseRM
, ZZBaseRM
, NormalBaseRM
):
2042 """normal: Rc=0: pred-result z/nonz"""
2049 def specifiers(self
, record
):
2050 yield from super().specifiers(record
=record
, mode
="pr")
2053 class NormalRM(NormalBaseRM
):
2054 simple
: NormalSimpleRM
2056 ffrc1
: NormalFFRc1RM
2057 ffrc0
: NormalFFRc0RM
2059 prrc1
: NormalPRRc1RM
2060 prrc0
: NormalPRRc0RM
2063 class LDSTImmBaseRM(PredicateWidthBaseRM
):
2065 LD/ST Immediate mode
2066 https://libre-soc.org/openpower/sv/ldst/
2071 class LDSTImmSimpleRM(ElsBaseRM
, ZZBaseRM
, LDSTImmBaseRM
):
2072 """ld/st immediate: simple mode"""
2079 class LDSTImmPostRM(LDSTImmBaseRM
):
2080 """ld/st immediate: postinc mode (and load-fault)"""
2081 pi
: BaseRM
.mode
[3] # Post-Increment Mode
2082 lf
: BaseRM
.mode
[4] # Fault-First Mode (not *Data-Dependent* Fail-First)
2084 def specifiers(self
, record
):
2091 class LDSTImmFFRc1RM(FFPRRc1BaseRM
, LDSTImmBaseRM
):
2092 """ld/st immediate: Rc=1: ffirst CR sel"""
2094 CR
: BaseRM
.mode
[3, 4]
2096 def specifiers(self
, record
):
2097 yield from super().specifiers(record
=record
, mode
="ff")
2100 class LDSTImmFFRc0RM(FFPRRc0BaseRM
, ElsBaseRM
, LDSTImmBaseRM
):
2101 """ld/st immediate: Rc=0: ffirst z/nonz"""
2106 def specifiers(self
, record
):
2107 yield from super().specifiers(record
=record
, mode
="ff")
2110 class LDSTImmSatRM(ElsBaseRM
, SatBaseRM
, ZZBaseRM
, LDSTImmBaseRM
):
2111 """ld/st immediate: sat mode: N=0/1 u/s"""
2119 class LDSTImmPRRc1RM(FFPRRc1BaseRM
, LDSTImmBaseRM
):
2120 """ld/st immediate: Rc=1: pred-result CR sel"""
2122 CR
: BaseRM
.mode
[3, 4]
2124 def specifiers(self
, record
):
2125 yield from super().specifiers(record
=record
, mode
="pr")
2128 class LDSTImmPRRc0RM(FFPRRc0BaseRM
, ElsBaseRM
, LDSTImmBaseRM
):
2129 """ld/st immediate: Rc=0: pred-result z/nonz"""
2134 def specifiers(self
, record
):
2135 yield from super().specifiers(record
=record
, mode
="pr")
2138 class LDSTImmRM(LDSTImmBaseRM
):
2139 simple
: LDSTImmSimpleRM
2141 ffrc1
: LDSTImmFFRc1RM
2142 ffrc0
: LDSTImmFFRc0RM
2144 prrc1
: LDSTImmPRRc1RM
2145 prrc0
: LDSTImmPRRc0RM
2148 class LDSTIdxBaseRM(PredicateWidthBaseRM
):
2151 https://libre-soc.org/openpower/sv/ldst/
2156 class LDSTIdxSimpleRM(SEABaseRM
, ZZCombinedBaseRM
, LDSTIdxBaseRM
):
2157 """ld/st index: simple mode"""
2163 class LDSTIdxStrideRM(SEABaseRM
, ZZCombinedBaseRM
, LDSTIdxBaseRM
):
2164 """ld/st index: strided (scalar only source)"""
2169 def specifiers(self
, record
):
2172 yield from super().specifiers(record
=record
)
2175 class LDSTIdxSatRM(SatBaseRM
, ZZCombinedBaseRM
, LDSTIdxBaseRM
):
2176 """ld/st index: sat mode: N=0/1 u/s"""
2182 class LDSTIdxPRRc1RM(LDSTIdxBaseRM
):
2183 """ld/st index: Rc=1: pred-result CR sel"""
2185 CR
: BaseRM
.mode
[3, 4]
2187 def specifiers(self
, record
):
2188 yield from super().specifiers(record
=record
, mode
="pr")
2191 class LDSTIdxPRRc0RM(FFPRRc0BaseRM
, ZZBaseRM
, LDSTIdxBaseRM
):
2192 """ld/st index: Rc=0: pred-result z/nonz"""
2199 def specifiers(self
, record
):
2200 yield from super().specifiers(record
=record
, mode
="pr")
2203 class LDSTIdxRM(LDSTIdxBaseRM
):
2204 simple
: LDSTIdxSimpleRM
2205 stride
: LDSTIdxStrideRM
2207 prrc1
: LDSTIdxPRRc1RM
2208 prrc0
: LDSTIdxPRRc0RM
2212 class CROpBaseRM(BaseRM
):
2215 https://libre-soc.org/openpower/sv/cr_ops/
2220 class CROpSimpleRM(PredicateBaseRM
, ZZCombinedBaseRM
, CROpBaseRM
):
2221 """cr_op: simple mode"""
2226 def specifiers(self
, record
):
2228 yield "rg" # simple CR Mode reports /rg
2230 yield from super().specifiers(record
=record
)
2232 class CROpMRRM(MRBaseRM
, ZZCombinedBaseRM
, CROpBaseRM
):
2233 """cr_op: scalar reduce mode (mapreduce), SUBVL=1"""
2239 class CROpFF3RM(FFPRRc1BaseRM
, VLiBaseRM
, ZZBaseRM
, PredicateBaseRM
, CROpBaseRM
):
2240 """cr_op: ffirst 3-bit mode"""
2248 def specifiers(self
, record
):
2249 yield from super().specifiers(record
=record
, mode
="ff")
2252 class CROpFF5RM(FFPRRc0BaseRM
, PredicateBaseRM
,
2253 VLiBaseRM
, ZZCombinedBaseRM
, CROpBaseRM
):
2254 """cr_op: ffirst 5-bit mode"""
2257 RC1
: BaseRM
[19] # cheat: set RC=1 based on ffirst mode being set
2261 def specifiers(self
, record
):
2262 yield from super().specifiers(record
=record
, mode
="ff")
2265 class CROpRM(CROpBaseRM
):
2266 simple
: CROpSimpleRM
2272 # ********************
2274 # https://libre-soc.org/openpower/sv/branches/
2275 class BranchBaseRM(BaseRM
):
2285 def specifiers(self
, record
):
2297 raise ValueError(self
.sz
)
2309 # Branch modes lack source mask.
2310 # Therefore a custom code is needed.
2311 CR
= (int(self
.mmode
) == 1)
2312 mask
= int(self
.mask
)
2313 m
= PredicateBaseRM
.predicate(CR
, mask
)
2317 yield from super().specifiers(record
=record
)
2320 class BranchSimpleRM(BranchBaseRM
):
2321 """branch: simple mode"""
2325 class BranchVLSRM(BranchBaseRM
):
2326 """branch: VLSET mode"""
2330 def specifiers(self
, record
):
2336 }[int(self
.VSb
), int(self
.VLi
)]
2338 yield from super().specifiers(record
=record
)
2341 class BranchCTRRM(BranchBaseRM
):
2342 """branch: CTR-test mode"""
2345 def specifiers(self
, record
):
2351 yield from super().specifiers(record
=record
)
2354 class BranchCTRVLSRM(BranchVLSRM
, BranchCTRRM
):
2355 """branch: CTR-test+VLSET mode"""
2359 class BranchRM(BranchBaseRM
):
2360 simple
: BranchSimpleRM
2363 ctrvls
: BranchCTRVLSRM
2373 def select(self
, record
):
2377 # the idea behind these tables is that they are now literally
2378 # in identical format to insndb.csv and minor_xx.csv and can
2379 # be done precisely as that. the only thing to watch out for
2380 # is the insertion of Rc=1 as a "mask/value" bit and likewise
2381 # regtype detection (3-bit BF/BFA, 5-bit BA/BB/BT) also inserted
2384 if record
.svp64
.mode
is _SVMode
.NORMAL
:
2385 # concatenate mode 5-bit with Rc (LSB) then do a mask/map search
2386 # mode Rc mask Rc member
2388 (0b000000, 0b111000, "simple"), # simple (no Rc)
2389 (0b001000, 0b111000, "mr"), # mapreduce (no Rc)
2390 (0b010001, 0b110001, "ffrc1"), # ffirst, Rc=1
2391 (0b010000, 0b110001, "ffrc0"), # ffirst, Rc=0
2392 (0b100000, 0b110000, "sat"), # saturation (no Rc)
2393 (0b110000, 0b110001, "prrc0"), # predicate, Rc=0
2394 (0b110001, 0b110001, "prrc1"), # predicate, Rc=1
2397 search
= ((int(rm
.mode
) << 1) | Rc
)
2399 elif record
.svp64
.mode
is _SVMode
.LDST_IMM
:
2400 # concatenate mode 5-bit with Rc (LSB) then do a mask/map search
2401 # mode Rc mask Rc member
2402 # ironically/coincidentally this table is identical to NORMAL
2403 # mode except reserved in place of mr
2405 (0b000000, 0b111000, "simple"), # simple (no Rc)
2406 (0b001000, 0b111000, "post"), # post (no Rc)
2407 (0b010001, 0b110001, "ffrc1"), # ffirst, Rc=1
2408 (0b010000, 0b110001, "ffrc0"), # ffirst, Rc=0
2409 (0b100000, 0b110000, "sat"), # saturation (no Rc)
2410 (0b110001, 0b110001, "prrc1"), # predicate, Rc=1
2411 (0b110000, 0b110001, "prrc0"), # predicate, Rc=0
2414 search
= ((int(rm
.mode
) << 1) | Rc
)
2416 elif record
.svp64
.mode
is _SVMode
.LDST_IDX
:
2417 # concatenate mode 5-bit with Rc (LSB) then do a mask/map search
2418 # mode Rc mask Rc member
2420 (0b000000, 0b110000, "simple"), # simple (no Rc)
2421 (0b010000, 0b110000, "stride"), # strided, (no Rc)
2422 (0b100000, 0b110000, "sat"), # saturation (no Rc)
2423 (0b110001, 0b110001, "prrc1"), # predicate, Rc=1
2424 (0b110000, 0b110001, "prrc0"), # predicate, Rc=0
2427 search
= ((int(rm
.mode
) << 1) | Rc
)
2429 elif record
.svp64
.mode
is _SVMode
.CROP
:
2430 # concatenate mode 5-bit with regtype (LSB) then do mask/map search
2431 # mode 3b mask 3b member
2433 (0b000000, 0b111000, "simple"), # simple
2434 (0b001000, 0b111000, "mr"), # mapreduce
2435 (0b100001, 0b100001, "ff3"), # ffirst, 3-bit CR
2436 (0b100000, 0b100000, "ff5"), # ffirst, 5-bit CR
2439 search
= ((int(rm
.mode
) << 1) |
int(record
.svp64
.cr_3bit
))
2441 elif record
.svp64
.mode
is _SVMode
.BRANCH
:
2445 (0b00, 0b11, "simple"), # simple
2446 (0b01, 0b11, "vls"), # VLset
2447 (0b10, 0b11, "ctr"), # CTR mode
2448 (0b11, 0b11, "ctrvls"), # CTR+VLset mode
2450 # slightly weird: doesn't have a 5-bit "mode" field like others
2452 search
= int(rm
.mode
.sel
)
2455 if table
is not None:
2456 for (value
, mask
, member
) in table
:
2457 if ((value
& mask
) == (search
& mask
)):
2458 rm
= getattr(rm
, member
)
2461 if rm
.__class
__ is self
.__class
__:
2462 raise ValueError(self
)
2467 @_dataclasses.dataclass(eq
=True, frozen
=True)
2472 def match(cls
, desc
, record
):
2473 raise NotImplementedError
2475 def validate(self
, others
):
2478 def assemble(self
, insn
):
2479 raise NotImplementedError
2482 @_dataclasses.dataclass(eq
=True, frozen
=True)
2483 class SpecifierWidth(Specifier
):
2487 def match(cls
, desc
, record
, etalon
):
2488 (mode
, _
, value
) = desc
.partition("=")
2490 value
= value
.strip()
2493 value
= _SVP64Width(value
)
2495 return cls(record
=record
, mode
=mode
, value
=value
)
2498 @_dataclasses.dataclass(eq
=True, frozen
=True)
2499 class SpecifierW(SpecifierWidth
):
2501 def match(cls
, desc
, record
):
2502 return super().match(desc
=desc
, record
=record
, etalon
="w")
2504 def assemble(self
, insn
):
2505 insn
.prefix
.rm
.ewsrc
= int(self
.value
)
2506 insn
.prefix
.rm
.elwidth
= int(self
.value
)
2509 @_dataclasses.dataclass(eq
=True, frozen
=True)
2510 class SpecifierSW(SpecifierWidth
):
2512 def match(cls
, desc
, record
):
2513 return super().match(desc
=desc
, record
=record
, etalon
="sw")
2515 def assemble(self
, insn
):
2516 insn
.prefix
.rm
.ewsrc
= int(self
.value
)
2519 @_dataclasses.dataclass(eq
=True, frozen
=True)
2520 class SpecifierDW(SpecifierWidth
):
2522 def match(cls
, desc
, record
):
2523 return super().match(desc
=desc
, record
=record
, etalon
="dw")
2525 def assemble(self
, insn
):
2526 insn
.prefix
.rm
.elwidth
= int(self
.value
)
2529 @_dataclasses.dataclass(eq
=True, frozen
=True)
2530 class SpecifierSubVL(Specifier
):
2534 def match(cls
, desc
, record
):
2536 value
= _SVP64SubVL(desc
)
2540 return cls(record
=record
, value
=value
)
2542 def assemble(self
, insn
):
2543 insn
.prefix
.rm
.subvl
= int(self
.value
.value
)
2546 @_dataclasses.dataclass(eq
=True, frozen
=True)
2547 class SpecifierPredicate(Specifier
):
2552 def match(cls
, desc
, record
, mode_match
, pred_match
):
2553 (mode
, _
, pred
) = desc
.partition("=")
2556 if not mode_match(mode
):
2559 pred
= _SVP64Pred(pred
.strip())
2560 if not pred_match(pred
):
2561 raise ValueError(pred
)
2563 return cls(record
=record
, mode
=mode
, pred
=pred
)
2566 @_dataclasses.dataclass(eq
=True, frozen
=True)
2567 class SpecifierFFPR(SpecifierPredicate
):
2569 def match(cls
, desc
, record
, mode
):
2570 return super().match(desc
=desc
, record
=record
,
2571 mode_match
=lambda mode_arg
: mode_arg
== mode
,
2572 pred_match
=lambda pred_arg
: pred_arg
.mode
in (
2577 def assemble(self
, insn
):
2579 if rm
.mode
.sel
!= 0:
2580 raise ValueError("cannot override mode")
2582 if self
.record
.svp64
.mode
is _SVMode
.CROP
:
2583 if self
.mode
== "pr":
2584 raise ValueError("crop: 'pr' mode not supported")
2586 if self
.record
.svp64
.cr_3bit
:
2591 if self
.record
.svp64
.mode
is _SVMode
.NORMAL
:
2593 elif self
.record
.svp64
.mode
is _SVMode
.LDST_IMM
:
2595 elif self
.record
.svp64
.mode
is _SVMode
.LDST_IDX
:
2597 if self
.mode
== "ff":
2598 raise ValueError("ld/st idx: 'ff' mode not supported")
2600 raise ValueError(f
"{self.mode!r} not supported")
2602 # These 2-bit values should have bits swapped
2604 return (((value
& 0b10) >> 1) |
((value
& 0b01) << 1))
2607 "ff": bitswap(_SVP64RMMode
.FFIRST
.value
),
2608 "pr": bitswap(_SVP64RMMode
.PREDRES
.value
),
2611 Rc
= int(self
.record
.Rc
)
2612 rm
= getattr(rm
, f
"{self.mode}rc{Rc}")
2613 rm
.inv
= self
.pred
.inv
2615 rm
.CR
= self
.pred
.state
2617 rm
.RC1
= self
.pred
.state
2620 @_dataclasses.dataclass(eq
=True, frozen
=True)
2621 class SpecifierFF(SpecifierFFPR
):
2623 def match(cls
, desc
, record
):
2624 return super().match(desc
=desc
, record
=record
, mode
="ff")
2627 @_dataclasses.dataclass(eq
=True, frozen
=True)
2628 class SpecifierPR(SpecifierFFPR
):
2630 def match(cls
, desc
, record
):
2631 return super().match(desc
=desc
, record
=record
, mode
="pr")
2634 @_dataclasses.dataclass(eq
=True, frozen
=True)
2635 class SpecifierMask(SpecifierPredicate
):
2637 def match(cls
, desc
, record
, mode
):
2638 return super().match(desc
=desc
, record
=record
,
2639 mode_match
=lambda mode_arg
: mode_arg
== mode
,
2640 pred_match
=lambda pred_arg
: pred_arg
.mode
in (
2645 def assemble(self
, insn
):
2646 raise NotImplementedError
2649 @_dataclasses.dataclass(eq
=True, frozen
=True)
2650 class SpecifierM(SpecifierMask
):
2652 def match(cls
, desc
, record
):
2653 return super().match(desc
=desc
, record
=record
, mode
="m")
2655 def validate(self
, others
):
2657 if isinstance(spec
, SpecifierSM
):
2658 raise ValueError("source-mask and predicate mask conflict")
2659 elif isinstance(spec
, SpecifierDM
):
2660 raise ValueError("dest-mask and predicate mask conflict")
2662 def assemble(self
, insn
):
2663 insn
.prefix
.rm
.mask
= int(self
.pred
)
2666 @_dataclasses.dataclass(eq
=True, frozen
=True)
2667 class SpecifierSM(SpecifierMask
):
2669 def match(cls
, desc
, record
):
2670 return super().match(desc
=desc
, record
=record
, mode
="sm")
2672 def validate(self
, others
):
2673 if self
.record
.svp64
.ptype
is _SVPType
.P1
:
2674 raise ValueError("source-mask on non-twin predicate")
2676 if self
.pred
.mode
is _SVP64PredMode
.CR
:
2679 if isinstance(spec
, SpecifierDM
):
2683 raise ValueError("missing dest-mask in CR twin predication")
2684 if self
.pred
!= twin
.pred
:
2685 raise ValueError(f
"predicate masks mismatch: {self!r} vs {twin!r}")
2687 def assemble(self
, insn
):
2688 insn
.prefix
.rm
.smask
= int(self
.pred
)
2691 @_dataclasses.dataclass(eq
=True, frozen
=True)
2692 class SpecifierDM(SpecifierMask
):
2694 def match(cls
, desc
, record
):
2695 return super().match(desc
=desc
, record
=record
, mode
="dm")
2697 def validate(self
, others
):
2698 if self
.record
.svp64
.ptype
is _SVPType
.P1
:
2699 raise ValueError("dest-mask on non-twin predicate")
2701 if self
.pred
.mode
is _SVP64PredMode
.CR
:
2704 if isinstance(spec
, SpecifierSM
):
2708 raise ValueError("missing source-mask in CR twin predication")
2709 if self
.pred
!= twin
.pred
:
2710 raise ValueError(f
"predicate masks mismatch: {self!r} vs {twin!r}")
2712 def assemble(self
, insn
):
2713 insn
.prefix
.rm
.mask
= int(self
.pred
)
2717 @_dataclasses.dataclass(eq
=True, frozen
=True)
2718 class SpecifierZZ(Specifier
):
2720 def match(cls
, desc
, record
):
2724 return cls(record
=record
)
2726 def validate(self
, others
):
2728 # Since m=xx takes precedence (overrides) sm=xx and dm=xx,
2729 # treat them as mutually exclusive.
2730 if isinstance(spec
, (SpecifierSZ
, SpecifierDZ
)):
2731 raise ValueError("mutually exclusive predicate masks")
2733 def assemble(self
, insn
):
2734 rm
= insn
.prefix
.rm
.select(record
=self
.record
)
2735 if hasattr(rm
, "zz"):
2742 @_dataclasses.dataclass(eq
=True, frozen
=True)
2743 class SpecifierXZ(Specifier
):
2745 hint
: str = _dataclasses
.field(repr=False)
2748 def match(cls
, desc
, record
, etalon
, hint
):
2749 if not desc
!= etalon
:
2752 return cls(desc
=desc
, record
=record
, hint
=hint
)
2754 def validate(self
, others
):
2755 if self
.record
.svp64
.ptype
is _SVPType
.P1
:
2756 raise ValueError(f
"{self.hint} on non-twin predicate")
2758 if self
.pred
.mode
is _SVP64PredMode
.CR
:
2761 if isinstance(spec
, SpecifierSM
):
2765 raise ValueError(f
"missing {self.hint} in CR twin predication")
2766 if self
.pred
!= twin
.pred
:
2767 raise ValueError(f
"predicate masks mismatch: {self!r} vs {twin!r}")
2769 def assemble(self
, insn
):
2770 rm
= insn
.prefix
.rm
.select(record
=self
.record
)
2771 setattr(rm
, self
.desc
, 1)
2774 @_dataclasses.dataclass(eq
=True, frozen
=True)
2775 class SpecifierSZ(SpecifierXZ
):
2777 def match(cls
, desc
, record
):
2778 return super().match(desc
=desc
, record
=record
,
2779 etalon
="sz", hint
="source-mask")
2781 def validate(self
, others
):
2783 if isinstance(spec
, SpecifierFF
):
2784 raise ValueError("source-zero not allowed in ff mode")
2785 elif isinstance(spec
, SpecifierPR
):
2786 raise ValueError("source-zero not allowed in pr mode")
2789 @_dataclasses.dataclass(eq
=True, frozen
=True)
2790 class SpecifierDZ(SpecifierXZ
):
2792 def match(cls
, desc
, record
):
2793 return super().match(desc
=desc
, record
=record
,
2794 etalon
="dz", hint
="dest-mask")
2796 def validate(self
, others
):
2798 if (isinstance(spec
, (SpecifierFF
, SpecifierPR
)) and
2799 (spec
.pred
.mode
is _SVP64PredMode
.RC1
)):
2800 mode
= "ff" if isinstance(spec
, SpecifierFF
) else "pr"
2801 raise ValueError(f
"dest-zero not allowed in {mode} mode BO")
2804 @_dataclasses.dataclass(eq
=True, frozen
=True)
2805 class SpecifierEls(Specifier
):
2807 def match(cls
, desc
, record
):
2811 return cls(record
=record
)
2813 def assemble(self
, insn
):
2814 rm
= insn
.prefix
.rm
.select(record
=self
.record
)
2816 if self
.record
.svp64
.mode
is _SVMode
.LDST_IDX
:
2820 @_dataclasses.dataclass(eq
=True, frozen
=True)
2821 class SpecifierSEA(Specifier
):
2823 def match(cls
, desc
, record
):
2827 return cls(record
=record
)
2829 def validate(self
, others
):
2830 if self
.record
.svp64
.mode
is not _SVMode
.LDST_IDX
:
2831 raise ValueError("sea is only valid in ld/st modes")
2834 if isinstance(spec
, SpecifierFF
):
2835 raise ValueError(f
"sea cannot be used in ff mode")
2837 def assemble(self
, insn
):
2838 rm
= insn
.prefix
.rm
.select(record
=self
.record
)
2839 if rm
.mode
.sel
not in (0b00, 0b01):
2840 raise ValueError("sea is only valid for normal and els modes")
2844 @_dataclasses.dataclass(eq
=True, frozen
=True)
2845 class SpecifierSat(Specifier
):
2850 def match(cls
, desc
, record
, etalon
, sign
):
2854 return cls(record
=record
, desc
=desc
, sign
=sign
)
2856 def assemble(self
, insn
):
2857 rm
= insn
.prefix
.rm
.select(record
=self
.record
)
2859 rm
.sat
= 1 if self
.sign
else 0
2862 @_dataclasses.dataclass(eq
=True, frozen
=True)
2863 class SpecifierSatS(Specifier
):
2865 def match(cls
, desc
, record
):
2866 return super().match(desc
=desc
, record
=record
,
2867 etalon
="sats", sign
=True)
2870 @_dataclasses.dataclass(eq
=True, frozen
=True)
2871 class SpecifierSatU(Specifier
):
2873 def match(cls
, desc
, record
):
2874 return super().match(desc
=desc
, record
=record
,
2875 etalon
="satu", sign
=False)
2878 @_dataclasses.dataclass(eq
=True, frozen
=True)
2879 class SpecifierMR(Specifier
):
2881 def match(cls
, desc
, record
):
2885 return cls(record
=record
)
2887 def assemble(self
, insn
):
2888 rm
= insn
.prefix
.rm
.select(record
=self
.record
)
2894 @_dataclasses.dataclass(eq
=True, frozen
=True)
2895 class SpecifierMRR(Specifier
):
2897 def match(cls
, desc
, record
):
2901 return cls(record
=record
)
2903 def assemble(self
, insn
):
2904 rm
= insn
.prefix
.rm
.select(record
=self
.record
)
2910 @_dataclasses.dataclass(eq
=True, frozen
=True)
2911 class SpecifierCRM(Specifier
):
2913 def match(cls
, desc
, record
):
2917 return cls(record
=record
)
2919 def assemble(self
, insn
):
2920 rm
= insn
.prefix
.rm
.select(record
=self
.record
)
2925 @_dataclasses.dataclass(eq
=True, frozen
=True)
2926 class SpecifierBranch(Specifier
):
2928 def match(cls
, desc
, record
, etalon
):
2932 return cls(record
=record
)
2934 def validate(self
, others
):
2935 if self
.record
.svp64
.mode
!= _SVMode
.BRANCH
:
2936 raise ValueError("only branch modes supported")
2939 @_dataclasses.dataclass(eq
=True, frozen
=True)
2940 class SpecifierAll(SpecifierBranch
):
2942 def match(cls
, desc
, record
):
2943 return super().match(desc
=desc
, record
=record
, etalon
="all")
2945 def assemble(self
, insn
):
2946 rm
= insn
.prefix
.rm
.select(record
=self
.record
)
2950 @_dataclasses.dataclass(eq
=True, frozen
=True)
2951 class SpecifierSNZ(SpecifierBranch
):
2953 def match(cls
, desc
, record
):
2954 return super().match(desc
=desc
, record
=record
, etalon
="snz")
2956 def assemble(self
, insn
):
2957 rm
= insn
.prefix
.rm
.select(record
=self
.record
)
2962 @_dataclasses.dataclass(eq
=True, frozen
=True)
2963 class SpecifierSL(SpecifierBranch
):
2965 def match(cls
, desc
, record
):
2966 return super().match(desc
=desc
, record
=record
, etalon
="sl")
2968 def assemble(self
, insn
):
2969 rm
= insn
.prefix
.rm
.select(record
=self
.record
)
2973 @_dataclasses.dataclass(eq
=True, frozen
=True)
2974 class SpecifierSLu(SpecifierBranch
):
2976 def match(cls
, desc
, record
):
2977 return super().match(desc
=desc
, record
=record
, etalon
="slu")
2979 def assemble(self
, insn
):
2980 rm
= insn
.prefix
.rm
.select(record
=self
.record
)
2984 @_dataclasses.dataclass(eq
=True, frozen
=True)
2985 class SpecifierLRu(SpecifierBranch
):
2987 def match(cls
, desc
, record
):
2988 return super().match(desc
=desc
, record
=record
, etalon
="lru")
2990 def assemble(self
, insn
):
2991 rm
= insn
.prefix
.rm
.select(record
=self
.record
)
2995 @_dataclasses.dataclass(eq
=True, frozen
=True)
2996 class SpecifierVS(SpecifierBranch
):
2998 def match(cls
, desc
, record
):
2999 return super().match(desc
=desc
, record
=record
, etalon
="vs")
3001 def assemble(self
, insn
):
3002 rm
= insn
.prefix
.rm
.select(record
=self
.record
)
3008 @_dataclasses.dataclass(eq
=True, frozen
=True)
3009 class SpecifierVSi(SpecifierVS
):
3011 def match(cls
, desc
, record
):
3012 return super().match(desc
=desc
, record
=record
, etalon
="vsi")
3014 def assemble(self
, insn
):
3015 rm
= insn
.prefix
.rm
.select(record
=self
.record
)
3021 @_dataclasses.dataclass(eq
=True, frozen
=True)
3022 class SpecifierVSb(SpecifierVS
):
3024 def match(cls
, desc
, record
):
3025 return super().match(desc
=desc
, record
=record
, etalon
="vsb")
3027 def assemble(self
, insn
):
3028 rm
= insn
.prefix
.rm
.select(record
=self
.record
)
3034 @_dataclasses.dataclass(eq
=True, frozen
=True)
3035 class SpecifierVSbi(SpecifierVS
):
3037 def match(cls
, desc
, record
):
3038 return super().match(desc
=desc
, record
=record
, etalon
="vsbi")
3040 def assemble(self
, insn
):
3041 rm
= insn
.prefix
.rm
.select(record
=self
.record
)
3047 @_dataclasses.dataclass(eq
=True, frozen
=True)
3048 class SpecifierCTR(SpecifierVS
):
3050 def match(cls
, desc
, record
):
3054 return cls(record
=record
)
3056 def assemble(self
, insn
):
3057 rm
= insn
.prefix
.rm
.select(record
=self
.record
)
3061 @_dataclasses.dataclass(eq
=True, frozen
=True)
3062 class SpecifierCTi(SpecifierVS
):
3064 def match(cls
, desc
, record
):
3068 return cls(record
=record
)
3070 def assemble(self
, insn
):
3071 rm
= insn
.prefix
.rm
.select(record
=self
.record
)
3076 @_dataclasses.dataclass(eq
=True, frozen
=True)
3077 class SpecifierPI(Specifier
):
3079 def match(cls
, desc
, record
):
3083 return cls(record
=record
)
3085 def assemble(self
, insn
):
3086 rm
= insn
.prefix
.rm
.select(record
=self
.record
)
3090 @_dataclasses.dataclass(eq
=True, frozen
=True)
3091 class SpecifierLF(Specifier
):
3093 def match(cls
, desc
, record
):
3097 return cls(record
=record
)
3099 def assemble(self
, insn
):
3100 rm
= insn
.prefix
.rm
.select(record
=self
.record
)
3104 class Specifiers(tuple):
3139 def __new__(cls
, items
, record
):
3140 def transform(item
):
3141 for spec_cls
in cls
.SPECS
:
3142 spec
= spec_cls
.match(item
, record
=record
)
3143 if spec
is not None:
3145 raise ValueError(item
)
3147 specs
= tuple(map(transform
, items
))
3148 for (index
, spec
) in enumerate(specs
):
3149 head
= specs
[:index
]
3150 tail
= specs
[index
+ 1:]
3151 spec
.validate(others
=(head
+ tail
))
3153 return super().__new
__(cls
, specs
)
3156 class SVP64Instruction(PrefixedInstruction
):
3157 """SVP64 instruction: https://libre-soc.org/openpower/sv/svp64/"""
3158 class Prefix(PrefixedInstruction
.Prefix
):
3160 rm
: RM
.remap((6, 8) + tuple(range(10, 32)))
3164 def record(self
, db
):
3165 record
= db
[self
.suffix
]
3167 raise KeyError(self
)
3173 for idx
in range(64):
3174 bit
= int(self
[idx
])
3176 return "".join(map(str, bits
))
3179 def assemble(cls
, db
, opcode
, arguments
=None, specifiers
=None):
3180 if arguments
is None:
3182 if specifiers
is None:
3186 insn
= cls
.integer(value
=0)
3188 specifiers
= Specifiers(items
=specifiers
, record
=record
)
3189 for specifier
in specifiers
:
3190 specifier
.assemble(insn
=insn
)
3192 for operand
in record
.static_operands
:
3193 operand
.assemble(insn
=insn
)
3195 dynamic_operands
= tuple(record
.dynamic_operands
)
3196 if len(dynamic_operands
) != len(arguments
):
3197 raise ValueError("operands count mismatch")
3198 for (value
, operand
) in zip(arguments
, dynamic_operands
):
3199 operand
.assemble(value
=value
, insn
=insn
)
3201 insn
.prefix
.PO
= 0x1
3202 insn
.prefix
.id = 0x3
3206 def disassemble(self
, db
,
3208 verbosity
=Verbosity
.NORMAL
):
3210 if verbosity
<= Verbosity
.SHORT
:
3213 blob
= insn
.bytes(byteorder
=byteorder
)
3214 blob
= " ".join(map(lambda byte
: f
"{byte:02x}", blob
))
3217 record
= self
.record(db
=db
)
3218 blob_prefix
= blob(self
.prefix
)
3219 blob_suffix
= blob(self
.suffix
)
3220 if record
is None or record
.svp64
is None:
3221 yield f
"{blob_prefix}.long 0x{int(self.prefix):08x}"
3222 yield f
"{blob_suffix}.long 0x{int(self.suffix):08x}"
3225 name
= f
"sv.{record.name}"
3227 rm
= self
.prefix
.rm
.select(record
=record
)
3229 # convert specifiers to /x/y/z (sorted lexicographically)
3230 specifiers
= sorted(rm
.specifiers(record
=record
))
3231 if specifiers
: # if any add one extra to get the extra "/"
3232 specifiers
= ([""] + specifiers
)
3233 specifiers
= "/".join(specifiers
)
3235 # convert operands to " ,x,y,z"
3236 operands
= tuple(map(_operator
.itemgetter(1),
3237 self
.dynamic_operands(db
=db
, verbosity
=verbosity
)))
3238 operands
= ",".join(operands
)
3239 if len(operands
) > 0: # if any separate with a space
3240 operands
= (" " + operands
)
3242 yield f
"{blob_prefix}{name}{specifiers}{operands}"
3244 yield f
"{blob_suffix}"
3246 if verbosity
>= Verbosity
.VERBOSE
:
3248 binary
= self
.binary
3249 spec
= self
.spec(db
=db
, prefix
="sv.")
3251 yield f
"{indent}spec"
3252 yield f
"{indent}{indent}{spec}"
3253 yield f
"{indent}pcode"
3254 for stmt
in record
.mdwn
.pcode
:
3255 yield f
"{indent}{indent}{stmt}"
3256 yield f
"{indent}binary"
3257 yield f
"{indent}{indent}[0:8] {binary[0:8]}"
3258 yield f
"{indent}{indent}[8:16] {binary[8:16]}"
3259 yield f
"{indent}{indent}[16:24] {binary[16:24]}"
3260 yield f
"{indent}{indent}[24:32] {binary[24:32]}"
3261 yield f
"{indent}{indent}[32:40] {binary[32:40]}"
3262 yield f
"{indent}{indent}[40:48] {binary[40:48]}"
3263 yield f
"{indent}{indent}[48:56] {binary[48:56]}"
3264 yield f
"{indent}{indent}[56:64] {binary[56:64]}"
3265 yield f
"{indent}opcodes"
3266 for opcode
in record
.opcodes
:
3267 yield f
"{indent}{indent}{opcode!r}"
3268 for (cls
, kwargs
) in record
.mdwn
.operands
:
3269 operand
= cls(record
=record
, **kwargs
)
3270 yield from operand
.disassemble(insn
=self
,
3271 verbosity
=verbosity
, indent
=indent
)
3273 yield f
"{indent}{indent}{rm.__doc__}"
3274 for line
in rm
.disassemble(verbosity
=verbosity
):
3275 yield f
"{indent}{indent}{line}"
3279 def parse(stream
, factory
):
3281 return ("TODO" not in frozenset(entry
.values()))
3283 lines
= filter(lambda line
: not line
.strip().startswith("#"), stream
)
3284 entries
= _csv
.DictReader(lines
)
3285 entries
= filter(match
, entries
)
3286 return tuple(map(factory
, entries
))
3289 class MarkdownDatabase
:
3292 for (name
, desc
) in _ISA():
3295 (dynamic
, *static
) = desc
.regs
3296 operands
.extend(dynamic
)
3297 operands
.extend(static
)
3298 pcode
= PCode(iterable
=desc
.pcode
)
3299 operands
= Operands(insn
=name
, iterable
=operands
)
3300 db
[name
] = MarkdownRecord(pcode
=pcode
, operands
=operands
)
3302 self
.__db
= dict(sorted(db
.items()))
3304 return super().__init
__()
3307 yield from self
.__db
.items()
3309 def __contains__(self
, key
):
3310 return self
.__db
.__contains
__(key
)
3312 def __getitem__(self
, key
):
3313 return self
.__db
.__getitem
__(key
)
3316 class FieldsDatabase
:
3319 df
= _DecodeFields()
3321 for (form
, fields
) in df
.instrs
.items():
3322 if form
in {"DQE", "TX"}:
3326 db
[_Form
[form
]] = Fields(fields
)
3330 return super().__init
__()
3332 def __getitem__(self
, key
):
3333 return self
.__db
.__getitem
__(key
)
3337 def __init__(self
, root
, mdwndb
):
3338 # The code below groups the instructions by name:section.
3339 # There can be multiple names for the same instruction.
3340 # The point is to capture different opcodes for the same instruction.
3341 dd
= _collections
.defaultdict
3343 records
= _collections
.defaultdict(set)
3344 path
= (root
/ "insndb.csv")
3345 with
open(path
, "r", encoding
="UTF-8") as stream
:
3346 for section
in sorted(parse(stream
, Section
.CSV
)):
3347 path
= (root
/ section
.path
)
3349 section
.Mode
.INTEGER
: IntegerOpcode
,
3350 section
.Mode
.PATTERN
: PatternOpcode
,
3352 factory
= _functools
.partial(
3353 PPCRecord
.CSV
, opcode_cls
=opcode_cls
)
3354 with
open(path
, "r", encoding
="UTF-8") as stream
:
3355 for insn
in parse(stream
, factory
):
3356 for name
in insn
.names
:
3357 records
[name
].add(insn
)
3358 sections
[name
] = section
3360 items
= sorted(records
.items())
3362 for (name
, multirecord
) in items
:
3363 records
[name
] = PPCMultiRecord(sorted(multirecord
))
3365 def exact_match(name
):
3366 record
= records
.get(name
)
3372 if not name
.endswith("l"):
3374 alias
= exact_match(name
[:-1])
3377 record
= records
[alias
]
3378 if "lk" not in record
.flags
:
3379 raise ValueError(record
)
3383 if not name
.endswith("a"):
3385 alias
= LK_match(name
[:-1])
3388 record
= records
[alias
]
3389 if record
.intop
not in {_MicrOp
.OP_B
, _MicrOp
.OP_BC
}:
3390 raise ValueError(record
)
3391 if "AA" not in mdwndb
[name
].operands
:
3392 raise ValueError(record
)
3396 if not name
.endswith("."):
3398 alias
= exact_match(name
[:-1])
3401 record
= records
[alias
]
3402 if record
.Rc
is _RCOE
.NONE
:
3403 raise ValueError(record
)
3407 matches
= (exact_match
, LK_match
, AA_match
, Rc_match
)
3408 for (name
, _
) in mdwndb
:
3409 if name
.startswith("sv."):
3412 for match
in matches
:
3414 if alias
is not None:
3418 section
= sections
[alias
]
3419 record
= records
[alias
]
3420 db
[name
] = (section
, record
)
3422 self
.__db
= dict(sorted(db
.items()))
3424 return super().__init
__()
3426 @_functools.lru_cache(maxsize
=512, typed
=False)
3427 def __getitem__(self
, key
):
3428 return self
.__db
.get(key
, (None, None))
3431 class SVP64Database
:
3432 def __init__(self
, root
, ppcdb
):
3434 pattern
= _re
.compile(r
"^(?:LDST)?RM-(1P|2P)-.*?\.csv$")
3435 for (prefix
, _
, names
) in _os
.walk(root
):
3436 prefix
= _pathlib
.Path(prefix
)
3437 for name
in filter(lambda name
: pattern
.match(name
), names
):
3438 path
= (prefix
/ _pathlib
.Path(name
))
3439 with
open(path
, "r", encoding
="UTF-8") as stream
:
3440 db
.update(parse(stream
, SVP64Record
.CSV
))
3441 db
= {record
.name
:record
for record
in db
}
3443 self
.__db
= dict(sorted(db
.items()))
3444 self
.__ppcdb
= ppcdb
3446 return super().__init
__()
3448 def __getitem__(self
, key
):
3449 (_
, record
) = self
.__ppcdb
[key
]
3453 for name
in record
.names
:
3454 record
= self
.__db
.get(name
, None)
3455 if record
is not None:
3462 def __init__(self
, root
):
3463 root
= _pathlib
.Path(root
)
3464 mdwndb
= MarkdownDatabase()
3465 fieldsdb
= FieldsDatabase()
3466 ppcdb
= PPCDatabase(root
=root
, mdwndb
=mdwndb
)
3467 svp64db
= SVP64Database(root
=root
, ppcdb
=ppcdb
)
3471 opcodes
= _collections
.defaultdict(
3472 lambda: _collections
.defaultdict(set))
3474 for (name
, mdwn
) in mdwndb
:
3475 if name
.startswith("sv."):
3477 (section
, ppc
) = ppcdb
[name
]
3480 svp64
= svp64db
[name
]
3481 fields
= fieldsdb
[ppc
.form
]
3482 record
= Record(name
=name
,
3483 section
=section
, ppc
=ppc
, svp64
=svp64
,
3484 mdwn
=mdwn
, fields
=fields
)
3486 names
[record
.name
] = record
3490 opcodes
[section
][PO
.value
].add(record
)
3492 self
.__db
= sorted(db
)
3493 self
.__names
= dict(sorted(names
.items()))
3494 self
.__opcodes
= dict(sorted(opcodes
.items()))
3496 return super().__init
__()
3499 return repr(self
.__db
)
3502 yield from self
.__db
3504 @_functools.lru_cache(maxsize
=None)
3505 def __contains__(self
, key
):
3506 return self
.__getitem
__(key
) is not None
3508 @_functools.lru_cache(maxsize
=None)
3509 def __getitem__(self
, key
):
3510 if isinstance(key
, Instruction
):
3513 for (section
, group
) in self
.__opcodes
.items():
3514 for record
in group
[PO
]:
3515 if record
.match(key
=key
):
3520 elif isinstance(key
, str):
3521 return self
.__names
.get(key
)
3523 raise ValueError("instruction or name expected")