src/openpower/decoder/power_insn.py

   1 import collections as _collections
   2 import csv as _csv
   3 import dataclasses as _dataclasses
   4 import enum as _enum
   5 import functools as _functools
   6 import itertools as _itertools
   7 import os as _os
   8 import operator as _operator
   9 import pathlib as _pathlib
  10 import re as _re
  11
  12 try:
  13     from functools import cached_property
  14 except ImportError:
  15     from cached_property import cached_property
  16
  17 from openpower.decoder.power_enums import (
  18     Function as _Function,
  19     MicrOp as _MicrOp,
  20     In1Sel as _In1Sel,
  21     In2Sel as _In2Sel,
  22     In3Sel as _In3Sel,
  23     OutSel as _OutSel,
  24     CRInSel as _CRInSel,
  25     CRIn2Sel as _CRIn2Sel,
  26     CROutSel as _CROutSel,
  27     LDSTLen as _LDSTLen,
  28     LDSTMode as _LDSTMode,
  29     RCOE as _RCOE,
  30     CryIn as _CryIn,
  31     Form as _Form,
  32     SVEtype as _SVEtype,
  33     SVmask_src as _SVmask_src,
  34     SVMode as _SVMode,
  35     SVPtype as _SVPtype,
  36     SVExtra as _SVExtra,
  37     RegType as _RegType,
  38     SVExtraRegType as _SVExtraRegType,
  39     SVExtraReg as _SVExtraReg,
  40 )
  41 from openpower.decoder.selectable_int import (
  42     SelectableInt as _SelectableInt,
  43     selectconcat as _selectconcat,
  44 )
  45 from openpower.decoder.power_fields import (
  46     Field as _Field,
  47     Mapping as _Mapping,
  48     DecodeFields as _DecodeFields,
  49 )
  50 from openpower.decoder.pseudo.pagereader import ISA as _ISA
  51
  52
  53 @_functools.total_ordering
  54 class Verbosity(_enum.Enum):
  55     SHORT = _enum.auto()
  56     NORMAL = _enum.auto()
  57     VERBOSE = _enum.auto()
  58
  59     def __lt__(self, other):
  60         if not isinstance(other, self.__class__):
  61             return NotImplemented
  62         return (self.value < other.value)
  63
  64
  65 def dataclass(cls, record, keymap=None, typemap=None):
  66     if keymap is None:
  67         keymap = {}
  68     if typemap is None:
  69         typemap = {field.name:field.type for field in _dataclasses.fields(cls)}
  70
  71     def transform(key_value):
  72         (key, value) = key_value
  73         key = keymap.get(key, key)
  74         hook = typemap.get(key, lambda value: value)
  75         if hook is bool and value in ("", "0"):
  76             value = False
  77         else:
  78             value = hook(value)
  79         return (key, value)
  80
  81     record = dict(map(transform, record.items()))
  82     for key in frozenset(record.keys()):
  83         if record[key] == "":
  84             record.pop(key)
  85
  86     return cls(**record)
  87
  88
  89 @_functools.total_ordering
  90 @_dataclasses.dataclass(eq=True, frozen=True)
  91 class Opcode:
  92     class Integer(int):
  93         def __new__(cls, value):
  94             if isinstance(value, str):
  95                 value = int(value, 0)
  96             if not isinstance(value, int):
  97                 raise ValueError(value)
  98
  99             if value.bit_length() > 64:
 100                 raise ValueError(value)
 101
 102             return super().__new__(cls, value)
 103
 104         def __str__(self):
 105             return super().__repr__()
 106
 107         def __repr__(self):
 108             return f"{self:0{self.bit_length()}b}"
 109
 110         def bit_length(self):
 111             if super().bit_length() > 32:
 112                 return 64
 113             return 32
 114
 115     class Value(Integer):
 116         pass
 117
 118     class Mask(Integer):
 119         pass
 120
 121     value: Value
 122     mask: Mask
 123
 124     def __lt__(self, other):
 125         if not isinstance(other, Opcode):
 126             return NotImplemented
 127         return ((self.value, self.mask) < (other.value, other.mask))
 128
 129     def __post_init__(self):
 130         if self.value.bit_length() != self.mask.bit_length():
 131             raise ValueError("bit length mismatch")
 132
 133     def __repr__(self):
 134         def pattern(value, mask, bit_length):
 135             for bit in range(bit_length):
 136                 if ((mask & (1 << (bit_length - bit - 1))) == 0):
 137                     yield "-"
 138                 elif (value & (1 << (bit_length - bit - 1))):
 139                     yield "1"
 140                 else:
 141                     yield "0"
 142
 143         return "".join(pattern(self.value, self.mask, self.value.bit_length()))
 144
 145
 146 class IntegerOpcode(Opcode):
 147     def __init__(self, value):
 148         if value.startswith("0b"):
 149            mask = int(("1" * len(value[2:])), 2)
 150         else:
 151             mask = 0b111111
 152
 153         value = Opcode.Value(value)
 154         mask = Opcode.Mask(mask)
 155
 156         return super().__init__(value=value, mask=mask)
 157
 158
 159 class PatternOpcode(Opcode):
 160     def __init__(self, pattern):
 161         if not isinstance(pattern, str):
 162             raise ValueError(pattern)
 163
 164         (value, mask) = (0, 0)
 165         for symbol in pattern:
 166             if symbol not in {"0", "1", "-"}:
 167                 raise ValueError(pattern)
 168             value |= (symbol == "1")
 169             mask |= (symbol != "-")
 170             value <<= 1
 171             mask <<= 1
 172         value >>= 1
 173         mask >>= 1
 174
 175         value = Opcode.Value(value)
 176         mask = Opcode.Mask(mask)
 177
 178         return super().__init__(value=value, mask=mask)
 179
 180
 181 @_dataclasses.dataclass(eq=True, frozen=True)
 182 class PPCRecord:
 183     class FlagsMeta(type):
 184         def __iter__(cls):
 185             yield from (
 186                 "inv A",
 187                 "inv out",
 188                 "cry out",
 189                 "BR",
 190                 "sgn ext",
 191                 "rsrv",
 192                 "32b",
 193                 "sgn",
 194                 "lk",
 195                 "sgl pipe",
 196             )
 197
 198     class Flags(frozenset, metaclass=FlagsMeta):
 199         def __new__(cls, flags=frozenset()):
 200             flags = frozenset(flags)
 201             diff = (flags - frozenset(cls))
 202             if diff:
 203                 raise ValueError(flags)
 204             return super().__new__(cls, flags)
 205
 206     opcode: Opcode
 207     comment: str
 208     flags: Flags = Flags()
 209     comment2: str = ""
 210     function: _Function = _Function.NONE
 211     intop: _MicrOp = _MicrOp.OP_ILLEGAL
 212     in1: _In1Sel = _In1Sel.RA
 213     in2: _In2Sel = _In2Sel.NONE
 214     in3: _In3Sel = _In3Sel.NONE
 215     out: _OutSel = _OutSel.NONE
 216     cr_in: _CRInSel = _CRInSel.NONE
 217     cr_in2: _CRIn2Sel = _CRIn2Sel.NONE
 218     cr_out: _CROutSel = _CROutSel.NONE
 219     cry_in: _CryIn = _CryIn.ZERO
 220     ldst_len: _LDSTLen = _LDSTLen.NONE
 221     upd: _LDSTMode = _LDSTMode.NONE
 222     Rc: _RCOE = _RCOE.NONE
 223     form: _Form = _Form.NONE
 224     conditions: str = ""
 225     unofficial: bool = False
 226
 227     __KEYMAP = {
 228         "unit": "function",
 229         "internal op": "intop",
 230         "CR in": "cr_in",
 231         "CR out": "cr_out",
 232         "cry in": "cry_in",
 233         "ldst len": "ldst_len",
 234         "rc": "Rc",
 235         "CONDITIONS": "conditions",
 236     }
 237
 238     @classmethod
 239     def CSV(cls, record, opcode_cls):
 240         typemap = {field.name:field.type for field in _dataclasses.fields(cls)}
 241         typemap["opcode"] = opcode_cls
 242
 243         if record["CR in"] == "BA_BB":
 244             record["cr_in"] = "BA"
 245             record["cr_in2"] = "BB"
 246             del record["CR in"]
 247
 248         flags = set()
 249         for flag in frozenset(PPCRecord.Flags):
 250             if bool(record.pop(flag, "")):
 251                 flags.add(flag)
 252         record["flags"] = PPCRecord.Flags(flags)
 253
 254         return dataclass(cls, record,
 255             keymap=PPCRecord.__KEYMAP,
 256             typemap=typemap)
 257
 258     @cached_property
 259     def names(self):
 260         return frozenset(self.comment.split("=")[-1].split("/"))
 261
 262
 263 class PPCMultiRecord(tuple):
 264     def __getattr__(self, attr):
 265         if attr == "opcode":
 266             raise AttributeError(attr)
 267         return getattr(self[0], attr)
 268
 269
 270 @_dataclasses.dataclass(eq=True, frozen=True)
 271 class SVP64Record:
 272     class ExtraMap(tuple):
 273         class Extra(tuple):
 274             @_dataclasses.dataclass(eq=True, frozen=True)
 275             class Entry:
 276                 regtype: _SVExtraRegType = _SVExtraRegType.NONE
 277                 reg: _SVExtraReg = _SVExtraReg.NONE
 278
 279                 def __repr__(self):
 280                     return f"{self.regtype.value}:{self.reg.name}"
 281
 282             def __new__(cls, value="0"):
 283                 if isinstance(value, str):
 284                     def transform(value):
 285                         (regtype, reg) = value.split(":")
 286                         regtype = _SVExtraRegType(regtype)
 287                         reg = _SVExtraReg(reg)
 288                         return cls.Entry(regtype=regtype, reg=reg)
 289
 290                     if value == "0":
 291                         value = tuple()
 292                     else:
 293                         value = map(transform, value.split(";"))
 294
 295                 return super().__new__(cls, value)
 296
 297             def __repr__(self):
 298                 return repr(list(self))
 299
 300         def __new__(cls, value=tuple()):
 301             value = tuple(value)
 302             if len(value) == 0:
 303                 value = (("0",) * 4)
 304             return super().__new__(cls, map(cls.Extra, value))
 305
 306         def __repr__(self):
 307             return repr({index:self[index] for index in range(0, 4)})
 308
 309     name: str
 310     ptype: _SVPtype = _SVPtype.NONE
 311     etype: _SVEtype = _SVEtype.NONE
 312     msrc: _SVmask_src = _SVmask_src.NO # MASK_SRC is active
 313     in1: _In1Sel = _In1Sel.NONE
 314     in2: _In2Sel = _In2Sel.NONE
 315     in3: _In3Sel = _In3Sel.NONE
 316     out: _OutSel = _OutSel.NONE
 317     out2: _OutSel = _OutSel.NONE
 318     cr_in: _CRInSel = _CRInSel.NONE
 319     cr_in2: _CRIn2Sel = _CRIn2Sel.NONE
 320     cr_out: _CROutSel = _CROutSel.NONE
 321     extra: ExtraMap = ExtraMap()
 322     conditions: str = ""
 323     mode: _SVMode = _SVMode.NORMAL
 324
 325     __KEYMAP = {
 326         "insn": "name",
 327         "CONDITIONS": "conditions",
 328         "Ptype": "ptype",
 329         "Etype": "etype",
 330         "SM": "msrc",
 331         "CR in": "cr_in",
 332         "CR out": "cr_out",
 333     }
 334
 335     @classmethod
 336     def CSV(cls, record):
 337         for key in frozenset({
 338                     "in1", "in2", "in3", "CR in",
 339                     "out", "out2", "CR out",
 340                 }):
 341             value = record[key]
 342             if value == "0":
 343                 record[key] = "NONE"
 344
 345         if record["CR in"] == "BA_BB":
 346             record["cr_in"] = "BA"
 347             record["cr_in2"] = "BB"
 348             del record["CR in"]
 349
 350         extra = []
 351         for idx in range(0, 4):
 352             extra.append(record.pop(f"{idx}"))
 353
 354         record["extra"] = cls.ExtraMap(extra)
 355
 356         return dataclass(cls, record, keymap=cls.__KEYMAP)
 357
 358     @_functools.lru_cache(maxsize=None)
 359     def extra_idx(self, key):
 360         extra_idx = (
 361             _SVExtra.Idx0,
 362             _SVExtra.Idx1,
 363             _SVExtra.Idx2,
 364             _SVExtra.Idx3,
 365         )
 366
 367         if key not in frozenset({
 368                     "in1", "in2", "in3", "cr_in", "cr_in2",
 369                     "out", "out2", "cr_out",
 370                 }):
 371             raise KeyError(key)
 372
 373         sel = getattr(self, key)
 374         if sel is _CRInSel.BA_BB:
 375             return _SVExtra.Idx_1_2
 376         reg = _SVExtraReg(sel)
 377         if reg is _SVExtraReg.NONE:
 378             return _SVExtra.NONE
 379
 380         extra_map = {
 381             _SVExtraRegType.SRC: {},
 382             _SVExtraRegType.DST: {},
 383         }
 384         for index in range(0, 4):
 385             for entry in self.extra[index]:
 386                 extra_map[entry.regtype][entry.reg] = extra_idx[index]
 387
 388         for regtype in (_SVExtraRegType.SRC, _SVExtraRegType.DST):
 389             extra = extra_map[regtype].get(reg, _SVExtra.NONE)
 390             if extra is not _SVExtra.NONE:
 391                 return extra
 392
 393         return _SVExtra.NONE
 394
 395     extra_idx_in1 = property(_functools.partial(extra_idx, key="in1"))
 396     extra_idx_in2 = property(_functools.partial(extra_idx, key="in2"))
 397     extra_idx_in3 = property(_functools.partial(extra_idx, key="in3"))
 398     extra_idx_out = property(_functools.partial(extra_idx, key="out"))
 399     extra_idx_out2 = property(_functools.partial(extra_idx, key="out2"))
 400     extra_idx_cr_in = property(_functools.partial(extra_idx, key="cr_in"))
 401     extra_idx_cr_out = property(_functools.partial(extra_idx, key="cr_out"))
 402
 403     @_functools.lru_cache(maxsize=None)
 404     def extra_reg(self, key):
 405         return _SVExtraReg(getattr(self, key))
 406
 407     extra_reg_in1 = property(_functools.partial(extra_reg, key="in1"))
 408     extra_reg_in2 = property(_functools.partial(extra_reg, key="in2"))
 409     extra_reg_in3 = property(_functools.partial(extra_reg, key="in3"))
 410     extra_reg_out = property(_functools.partial(extra_reg, key="out"))
 411     extra_reg_out2 = property(_functools.partial(extra_reg, key="out2"))
 412     extra_reg_cr_in = property(_functools.partial(extra_reg, key="cr_in"))
 413     extra_reg_cr_out = property(_functools.partial(extra_reg, key="cr_out"))
 414
 415
 416 class BitSel:
 417     def __init__(self, value=(0, 32)):
 418         if isinstance(value, str):
 419             (start, end) = map(int, value.split(":"))
 420         else:
 421             (start, end) = value
 422         if start < 0 or end < 0 or start >= end:
 423             raise ValueError(value)
 424
 425         self.__start = start
 426         self.__end = end
 427
 428         return super().__init__()
 429
 430     def __repr__(self):
 431         return f"[{self.__start}:{self.__end}]"
 432
 433     def __iter__(self):
 434         yield from range(self.start, (self.end + 1))
 435
 436     def __reversed__(self):
 437         return tuple(reversed(tuple(self)))
 438
 439     @property
 440     def start(self):
 441         return self.__start
 442
 443     @property
 444     def end(self):
 445         return self.__end
 446
 447
 448 @_dataclasses.dataclass(eq=True, frozen=True)
 449 class Section:
 450     class Mode(_enum.Enum):
 451         INTEGER = _enum.auto()
 452         PATTERN = _enum.auto()
 453
 454         @classmethod
 455         def _missing_(cls, value):
 456             if isinstance(value, str):
 457                 return cls[value.upper()]
 458             return super()._missing_(value)
 459
 460     class Suffix(int):
 461         def __new__(cls, value=None):
 462             if isinstance(value, str):
 463                 if value.upper() == "NONE":
 464                     value = None
 465                 else:
 466                     value = int(value, 0)
 467             if value is None:
 468                 value = 0
 469
 470             return super().__new__(cls, value)
 471
 472         def __str__(self):
 473             return repr(self)
 474
 475         def __repr__(self):
 476             return (bin(self) if self else "None")
 477
 478     path: _pathlib.Path
 479     bitsel: BitSel
 480     suffix: Suffix
 481     mode: Mode
 482     opcode: IntegerOpcode = None
 483
 484     @classmethod
 485     def CSV(cls, record):
 486         typemap = {field.name:field.type for field in _dataclasses.fields(cls)}
 487         if record["opcode"] == "NONE":
 488             typemap["opcode"] = lambda _: None
 489
 490         return dataclass(cls, record, typemap=typemap)
 491
 492
 493 class Fields:
 494     def __init__(self, items):
 495         if isinstance(items, dict):
 496             items = items.items()
 497
 498         def transform(item):
 499             (name, bitrange) = item
 500             return (name, tuple(bitrange.values()))
 501
 502         self.__mapping = dict(map(transform, items))
 503
 504         return super().__init__()
 505
 506     def __repr__(self):
 507         return repr(self.__mapping)
 508
 509     def __iter__(self):
 510         yield from self.__mapping.items()
 511
 512     def __contains__(self, key):
 513         return self.__mapping.__contains__(key)
 514
 515     def __getitem__(self, key):
 516         return self.__mapping.get(key, None)
 517
 518
 519 @_dataclasses.dataclass(eq=True, frozen=True)
 520 class Operand:
 521     name: str
 522
 523     def span(self, record):
 524         return record.fields[self.name]
 525
 526     def disassemble(self, insn, record,
 527             verbosity=Verbosity.NORMAL, indent=""):
 528         raise NotImplementedError
 529
 530
 531 class DynamicOperand(Operand):
 532     def disassemble(self, insn, record,
 533             verbosity=Verbosity.NORMAL, indent=""):
 534         span = self.span(record=record)
 535         if isinstance(insn, SVP64Instruction):
 536             span = tuple(map(lambda bit: (bit + 32), span))
 537         value = insn[span]
 538
 539         if verbosity >= Verbosity.VERBOSE:
 540             span = map(str, span)
 541             yield f"{indent}{self.name}"
 542             yield f"{indent}{indent}{int(value):0{value.bits}b}"
 543             yield f"{indent}{indent}{', '.join(span)}"
 544         else:
 545             yield str(int(value))
 546
 547
 548 class SignedOperand(DynamicOperand):
 549     def disassemble(self, insn, record,
 550             verbosity=Verbosity.NORMAL, indent=""):
 551         span = self.span(record=record)
 552         if isinstance(insn, SVP64Instruction):
 553             span = tuple(map(lambda bit: (bit + 32), span))
 554         value = insn[span]
 555
 556         if verbosity >= Verbosity.VERBOSE:
 557             span = map(str, span)
 558             yield f"{indent}{self.name}"
 559             yield f"{indent}{indent}{int(value):0{value.bits}b}"
 560             yield f"{indent}{indent}{', '.join(span)}"
 561         else:
 562             yield str(value.to_signed_int())
 563
 564
 565 @_dataclasses.dataclass(eq=True, frozen=True)
 566 class StaticOperand(Operand):
 567     value: int
 568
 569     def disassemble(self, insn, record,
 570             verbosity=Verbosity.NORMAL, indent=""):
 571         span = self.span(record=record)
 572         if isinstance(insn, SVP64Instruction):
 573             span = tuple(map(lambda bit: (bit + 32), span))
 574         value = insn[span]
 575
 576         if verbosity >= Verbosity.VERBOSE:
 577             span = map(str, span)
 578             yield f"{indent}{self.name}"
 579             yield f"{indent}{indent}{int(value):0{value.bits}b}"
 580             yield f"{indent}{indent}{', '.join(span)}"
 581         else:
 582             yield str(int(value))
 583
 584
 585 class ImmediateOperand(DynamicOperand):
 586     pass
 587
 588
 589 class NonZeroOperand(DynamicOperand):
 590     def disassemble(self, insn, record,
 591             verbosity=Verbosity.NORMAL, indent=""):
 592         span = self.span(record=record)
 593         if isinstance(insn, SVP64Instruction):
 594             span = tuple(map(lambda bit: (bit + 32), span))
 595         value = insn[span]
 596
 597         if verbosity >= Verbosity.VERBOSE:
 598             span = map(str, span)
 599             yield f"{indent}{self.name}"
 600             yield f"{indent}{indent}{int(value):0{value.bits}b}"
 601             yield f"{indent}{indent}{', '.join(span)}"
 602         else:
 603             yield str(int(value) + 1)
 604
 605
 606 class RegisterOperand(DynamicOperand):
 607     def sv_spec_enter(self, value, span):
 608         return (value, span)
 609
 610     def sv_spec_leave(self, value, span, origin_value, origin_span):
 611         return (value, span)
 612
 613     def spec(self, insn, record):
 614         vector = False
 615         span = self.span(record=record)
 616         if isinstance(insn, SVP64Instruction):
 617             span = tuple(map(lambda bit: (bit + 32), span))
 618         value = insn[span]
 619         span = tuple(map(str, span))
 620
 621         if isinstance(insn, SVP64Instruction):
 622             (origin_value, origin_span) = (value, span)
 623             (value, span) = self.sv_spec_enter(value=value, span=span)
 624
 625             extra_idx = self.extra_idx(record=record)
 626             if extra_idx is _SVExtra.NONE:
 627                 return (vector, value, span)
 628
 629             if record.etype is _SVEtype.EXTRA3:
 630                 spec = insn.prefix.rm.extra3[extra_idx]
 631             elif record.etype is _SVEtype.EXTRA2:
 632                 spec = insn.prefix.rm.extra2[extra_idx]
 633             else:
 634                 raise ValueError(record.etype)
 635
 636             if spec != 0:
 637                 vector = bool(spec[0])
 638                 spec_span = spec.__class__
 639                 if record.etype is _SVEtype.EXTRA3:
 640                     spec_span = tuple(map(str, spec_span[1, 2]))
 641                     spec = spec[1, 2]
 642                 elif record.etype is _SVEtype.EXTRA2:
 643                     spec_span = tuple(map(str, spec_span[1,]))
 644                     spec = _SelectableInt(value=spec[1].value, bits=2)
 645                     if vector:
 646                         spec <<= 1
 647                         spec_span = (spec_span + ("{0}",))
 648                     else:
 649                         spec_span = (("{0}",) + spec_span)
 650                 else:
 651                     raise ValueError(record.etype)
 652
 653                 vector_shift = (2 + (5 - value.bits))
 654                 scalar_shift = value.bits
 655                 spec_shift = (5 - value.bits)
 656
 657                 bits = (len(span) + len(spec_span))
 658                 value = _SelectableInt(value=value.value, bits=bits)
 659                 spec = _SelectableInt(value=spec.value, bits=bits)
 660                 if vector:
 661                     value = ((value << vector_shift) | (spec << spec_shift))
 662                     span = (span + spec_span + ((spec_shift * ('{0}',))))
 663                 else:
 664                     value = ((spec << scalar_shift) | value)
 665                     span = ((spec_shift * ('{0}',)) + spec_span + span)
 666
 667             (value, span) = self.sv_spec_leave(value=value, span=span,
 668                 origin_value=origin_value, origin_span=origin_span)
 669
 670         return (vector, value, span)
 671
 672     @property
 673     def extra_reg(self):
 674         return _SVExtraReg(self.name)
 675
 676     def extra_idx(self, record):
 677         for key in frozenset({
 678                     "in1", "in2", "in3", "cr_in", "cr_in2",
 679                     "out", "out2", "cr_out",
 680                 }):
 681             extra_reg = record.svp64.extra_reg(key=key)
 682             if extra_reg is self.extra_reg:
 683                 return record.extra_idx(key=key)
 684
 685         return _SVExtra.NONE
 686
 687     def disassemble(self, insn, record,
 688             verbosity=Verbosity.NORMAL, prefix="", indent=""):
 689         (vector, value, span) = self.spec(insn=insn, record=record)
 690
 691         if verbosity >= Verbosity.VERBOSE:
 692             mode = "vector" if vector else "scalar"
 693             yield f"{indent}{self.name} ({mode})"
 694             yield f"{indent}{indent}{int(value):0{value.bits}b}"
 695             yield f"{indent}{indent}{', '.join(span)}"
 696             if isinstance(insn, SVP64Instruction):
 697                 extra_idx = self.extra_idx(record)
 698                 if record.etype is _SVEtype.NONE:
 699                     yield f"{indent}{indent}extra[none]"
 700                 else:
 701                     etype = repr(record.etype).lower()
 702                     yield f"{indent}{indent}{etype}{extra_idx!r}"
 703         else:
 704             vector = "*" if vector else ""
 705             yield f"{vector}{prefix}{int(value)}"
 706
 707
 708 class GPROperand(RegisterOperand):
 709     def disassemble(self, insn, record,
 710             verbosity=Verbosity.NORMAL, indent=""):
 711         prefix = "" if (verbosity <= Verbosity.SHORT) else "r"
 712         yield from super().disassemble(prefix=prefix,
 713             insn=insn, record=record,
 714             verbosity=verbosity, indent=indent)
 715
 716
 717 class FPROperand(RegisterOperand):
 718     def disassemble(self, insn, record,
 719             verbosity=Verbosity.NORMAL, indent=""):
 720         prefix = "" if (verbosity <= Verbosity.SHORT) else "f"
 721         yield from super().disassemble(prefix=prefix,
 722             insn=insn, record=record,
 723             verbosity=verbosity, indent=indent)
 724
 725
 726 class CR3Operand(RegisterOperand):
 727     pass
 728
 729
 730 class CR5Operand(RegisterOperand):
 731     def sv_spec_enter(self, value, span):
 732         value = _SelectableInt(value=(value.value >> 2), bits=3)
 733         return (value, span)
 734
 735     def sv_spec_leave(self, value, span, origin_value, origin_span):
 736         value = _selectconcat(value, origin_value[3:5])
 737         span += origin_span
 738         return (value, span)
 739
 740
 741 class TargetAddrOperand(RegisterOperand):
 742     def disassemble(self, insn, record, field,
 743             verbosity=Verbosity.NORMAL, indent=""):
 744         span = self.span(record=record)
 745         if isinstance(insn, SVP64Instruction):
 746             span = tuple(map(lambda bit: (bit + 32), span))
 747         value = insn[span]
 748
 749         if verbosity >= Verbosity.VERBOSE:
 750             span = tuple(map(str, span))
 751             yield f"{indent}{self.name} = EXTS({field} || 0b00))"
 752             yield f"{indent}{indent}{field}"
 753             yield f"{indent}{indent}{indent}{int(value):0{value.bits}b}00"
 754             yield f"{indent}{indent}{indent}{', '.join(span + ('{0}', '{0}'))}"
 755         else:
 756             yield hex(_selectconcat(value,
 757                 _SelectableInt(value=0b00, bits=2)).to_signed_int())
 758
 759
 760 class TargetAddrOperandLI(TargetAddrOperand):
 761     def span(self, record):
 762         return record.fields["LI"]
 763
 764     def disassemble(self, insn, record,
 765             verbosity=Verbosity.NORMAL, indent=""):
 766         return super().disassemble(field="LI",
 767             insn=insn, record=record,
 768             verbosity=verbosity, indent=indent)
 769
 770
 771 class TargetAddrOperandBD(TargetAddrOperand):
 772     def span(self, record):
 773         return record.fields["BD"]
 774
 775     def disassemble(self, insn, record,
 776             verbosity=Verbosity.NORMAL, indent=""):
 777         return super().disassemble(field="BD",
 778             insn=insn, record=record,
 779             verbosity=verbosity, indent=indent)
 780
 781
 782 class DOperandDX(SignedOperand):
 783     def span(self, record):
 784         operands = map(DynamicOperand, ("d0", "d1", "d2"))
 785         spans = map(lambda operand: operand.span(record=record), operands)
 786         return sum(spans, tuple())
 787
 788     def disassemble(self, insn, record,
 789             verbosity=Verbosity.NORMAL, indent=""):
 790         span = self.span(record=record)
 791         if isinstance(insn, SVP64Instruction):
 792             span = tuple(map(lambda bit: (bit + 32), span))
 793         value = insn[span]
 794
 795         if verbosity >= Verbosity.VERBOSE:
 796             yield f"{indent}D"
 797             mapping = {
 798                 "d0": "[0:9]",
 799                 "d1": "[10:15]",
 800                 "d2": "[16]",
 801             }
 802             for (subname, subspan) in mapping.items():
 803                 operand = DynamicOperand(name=subname)
 804                 span = operand.span(record=record)
 805                 if isinstance(insn, SVP64Instruction):
 806                     span = tuple(map(lambda bit: (bit + 32), span))
 807                 value = insn[span]
 808                 span = map(str, span)
 809                 yield f"{indent}{indent}{operand.name} = D{subspan}"
 810                 yield f"{indent}{indent}{indent}{int(value):0{value.bits}b}"
 811                 yield f"{indent}{indent}{indent}{', '.join(span)}"
 812         else:
 813             yield str(value.to_signed_int())
 814
 815
 816 class Operands(tuple):
 817     def __new__(cls, insn, iterable):
 818         custom_insns = {
 819             "b": {"target_addr": TargetAddrOperandLI},
 820             "ba": {"target_addr": TargetAddrOperandLI},
 821             "bl": {"target_addr": TargetAddrOperandLI},
 822             "bla": {"target_addr": TargetAddrOperandLI},
 823             "bc": {"target_addr": TargetAddrOperandBD},
 824             "bca": {"target_addr": TargetAddrOperandBD},
 825             "bcl": {"target_addr": TargetAddrOperandBD},
 826             "bcla": {"target_addr": TargetAddrOperandBD},
 827             "addpcis": {"D": DOperandDX},
 828             "fishmv": {"D": DOperandDX},
 829             "fmvis": {"D": DOperandDX},
 830         }
 831         custom_fields = {
 832             "SVi": NonZeroOperand,
 833             "SVd": NonZeroOperand,
 834             "SVxd": NonZeroOperand,
 835             "SVyd": NonZeroOperand,
 836             "SVzd": NonZeroOperand,
 837             "BD": SignedOperand,
 838             "D": SignedOperand,
 839             "DQ": SignedOperand,
 840             "DS": SignedOperand,
 841             "SI": SignedOperand,
 842             "IB": SignedOperand,
 843             "LI": SignedOperand,
 844             "SIM": SignedOperand,
 845             "SVD": SignedOperand,
 846             "SVDS": SignedOperand,
 847         }
 848
 849         operands = []
 850         for operand in iterable:
 851             dynamic_cls = DynamicOperand
 852             static_cls = StaticOperand
 853
 854             if "=" in operand:
 855                 (name, value) = operand.split("=")
 856                 operand = static_cls(name=name, value=int(value))
 857                 operands.append(operand)
 858             else:
 859                 if operand.endswith(")"):
 860                     operand = operand.replace("(", " ").replace(")", "")
 861                     (immediate, _, operand) = operand.partition(" ")
 862                 else:
 863                     immediate = None
 864
 865                 if immediate is not None:
 866                     operands.append(ImmediateOperand(name=immediate))
 867
 868                 if operand in custom_fields:
 869                     dynamic_cls = custom_fields[operand]
 870                 if insn in custom_insns and operand in custom_insns[insn]:
 871                     dynamic_cls = custom_insns[insn][operand]
 872
 873                 if operand in _RegType.__members__:
 874                     regtype = _RegType[operand]
 875                     if regtype is _RegType.GPR:
 876                         dynamic_cls = GPROperand
 877                     elif regtype is _RegType.FPR:
 878                         dynamic_cls = FPROperand
 879                     if regtype is _RegType.CR_BIT: # 5-bit
 880                         dynamic_cls = CR5Operand
 881                     if regtype is _RegType.CR_REG: # actually CR Field, 3-bit
 882                         dynamic_cls = CR3Operand
 883
 884                 operand = dynamic_cls(name=operand)
 885                 operands.append(operand)
 886
 887         return super().__new__(cls, operands)
 888
 889     def __contains__(self, key):
 890         return self.__getitem__(key) is not None
 891
 892     def __getitem__(self, key):
 893         for operand in self:
 894             if operand.name == key:
 895                 return operand
 896
 897         return None
 898
 899     @property
 900     def dynamic(self):
 901         for operand in self:
 902             if isinstance(operand, DynamicOperand):
 903                 yield operand
 904
 905     @property
 906     def static(self):
 907         for operand in self:
 908             if isinstance(operand, StaticOperand):
 909                 yield operand
 910
 911
 912 class PCode:
 913     def __init__(self, iterable):
 914         self.__pcode = tuple(iterable)
 915         return super().__init__()
 916
 917     def __iter__(self):
 918         yield from self.__pcode
 919
 920     def __repr__(self):
 921         return self.__pcode.__repr__()
 922
 923
 924 @_dataclasses.dataclass(eq=True, frozen=True)
 925 class MarkdownRecord:
 926     pcode: PCode
 927     operands: Operands
 928
 929
 930 @_functools.total_ordering
 931 @_dataclasses.dataclass(eq=True, frozen=True)
 932 class Record:
 933     name: str
 934     section: Section
 935     ppc: PPCRecord
 936     fields: Fields
 937     mdwn: MarkdownRecord
 938     svp64: SVP64Record = None
 939
 940     def __lt__(self, other):
 941         if not isinstance(other, Record):
 942             return NotImplemented
 943         return (min(self.opcodes) < min(other.opcodes))
 944
 945     @property
 946     def opcodes(self):
 947         def opcode(ppc):
 948             value = ([0] * 32)
 949             mask = ([0] * 32)
 950
 951             PO = self.section.opcode
 952             if PO is not None:
 953                 for (src, dst) in enumerate(reversed(BitSel((0, 5)))):
 954                     value[dst] = int((PO.value & (1 << src)) != 0)
 955                     mask[dst] = int((PO.mask & (1 << src)) != 0)
 956
 957             XO = ppc.opcode
 958             for (src, dst) in enumerate(reversed(self.section.bitsel)):
 959                 value[dst] = int((XO.value & (1 << src)) != 0)
 960                 mask[dst] = int((XO.mask & (1 << src)) != 0)
 961
 962             for operand in self.mdwn.operands.static:
 963                 for (src, dst) in enumerate(reversed(operand.span(record=self))):
 964                     value[dst] = int((operand.value & (1 << src)) != 0)
 965                     mask[dst] = 1
 966
 967             value = Opcode.Value(int(("".join(map(str, value))), 2))
 968             mask = Opcode.Mask(int(("".join(map(str, mask))), 2))
 969
 970             return Opcode(value=value, mask=mask)
 971
 972         return tuple(sorted(map(opcode, self.ppc)))
 973
 974     def match(self, key):
 975         for opcode in self.opcodes:
 976             if ((opcode.value & opcode.mask) ==
 977                     (key & opcode.mask)):
 978                 return True
 979         return False
 980
 981     @property
 982     def function(self):
 983         return self.ppc.function
 984
 985     @property
 986     def in1(self):
 987         return self.ppc.in1
 988
 989     @property
 990     def in2(self):
 991         return self.ppc.in2
 992
 993     @property
 994     def in3(self):
 995         return self.ppc.in3
 996
 997     @property
 998     def out(self):
 999         return self.ppc.out
1000
1001     @property
1002     def out2(self):
1003         if self.svp64 is None:
1004             return _OutSel.NONE
1005         return self.ppc.out
1006
1007     @property
1008     def cr_in(self):
1009         return self.ppc.cr_in
1010
1011     @property
1012     def cr_in2(self):
1013         return self.ppc.cr_in2
1014
1015     @property
1016     def cr_out(self):
1017         return self.ppc.cr_out
1018
1019     ptype = property(lambda self: self.svp64.ptype)
1020     etype = property(lambda self: self.svp64.etype)
1021
1022     def extra_idx(self, key):
1023         return self.svp64.extra_idx(key)
1024
1025     extra_idx_in1 = property(lambda self: self.svp64.extra_idx_in1)
1026     extra_idx_in2 = property(lambda self: self.svp64.extra_idx_in2)
1027     extra_idx_in3 = property(lambda self: self.svp64.extra_idx_in3)
1028     extra_idx_out = property(lambda self: self.svp64.extra_idx_out)
1029     extra_idx_out2 = property(lambda self: self.svp64.extra_idx_out2)
1030     extra_idx_cr_in = property(lambda self: self.svp64.extra_idx_cr_in)
1031     extra_idx_cr_out = property(lambda self: self.svp64.extra_idx_cr_out)
1032
1033
1034 class Instruction(_Mapping):
1035     @classmethod
1036     def integer(cls, value=0, bits=None, byteorder="little"):
1037         if isinstance(value, (int, bytes)) and not isinstance(bits, int):
1038             raise ValueError(bits)
1039
1040         if isinstance(value, bytes):
1041             if ((len(value) * 8) != bits):
1042                 raise ValueError(f"bit length mismatch")
1043             value = int.from_bytes(value, byteorder=byteorder)
1044
1045         if isinstance(value, int):
1046             value = _SelectableInt(value=value, bits=bits)
1047         elif isinstance(value, Instruction):
1048             value = value.storage
1049
1050         if not isinstance(value, _SelectableInt):
1051             raise ValueError(value)
1052         if bits is None:
1053             bits = len(cls)
1054         if len(value) != bits:
1055             raise ValueError(value)
1056
1057         value = _SelectableInt(value=value, bits=bits)
1058
1059         return cls(storage=value)
1060
1061     def __hash__(self):
1062         return hash(int(self))
1063
1064     def __getitem__(self, key):
1065         return self.storage.__getitem__(key)
1066
1067     def __setitem__(self, key, value):
1068         return self.storage.__setitem__(key, value)
1069
1070     def bytes(self, byteorder="little"):
1071         nr_bytes = (self.storage.bits // 8)
1072         return int(self).to_bytes(nr_bytes, byteorder=byteorder)
1073
1074     def record(self, db):
1075         record = db[self]
1076         if record is None:
1077             raise KeyError(self)
1078         return record
1079
1080     def spec(self, db, prefix):
1081         record = self.record(db=db)
1082
1083         dynamic_operands = tuple(map(_operator.itemgetter(0),
1084             self.dynamic_operands(db=db)))
1085
1086         static_operands = []
1087         for (name, value) in self.static_operands(db=db):
1088             static_operands.append(f"{name}={value}")
1089
1090         operands = ""
1091         if dynamic_operands:
1092             operands += f" {','.join(dynamic_operands)}"
1093         if static_operands:
1094             operands += f" ({' '.join(static_operands)})"
1095
1096         return f"{prefix}{record.name}{operands}"
1097
1098     def dynamic_operands(self, db, verbosity=Verbosity.NORMAL):
1099         record = self.record(db=db)
1100
1101         imm = False
1102         imm_name = ""
1103         imm_value = ""
1104         for operand in record.mdwn.operands.dynamic:
1105             name = operand.name
1106             dis = operand.disassemble(insn=self, record=record,
1107                 verbosity=min(verbosity, Verbosity.NORMAL))
1108             value = " ".join(dis)
1109             if imm:
1110                 name = f"{imm_name}({name})"
1111                 value = f"{imm_value}({value})"
1112                 imm = False
1113             if isinstance(operand, ImmediateOperand):
1114                 imm_name = name
1115                 imm_value = value
1116                 imm = True
1117             if not imm:
1118                 yield (name, value)
1119
1120     def static_operands(self, db):
1121         record = self.record(db=db)
1122         for operand in record.mdwn.operands.static:
1123             yield (operand.name, operand.value)
1124
1125     def disassemble(self, db,
1126             byteorder="little",
1127             verbosity=Verbosity.NORMAL):
1128         raise NotImplementedError
1129
1130
1131 class WordInstruction(Instruction):
1132     _: _Field = range(0, 32)
1133     po: _Field = range(0, 6)
1134
1135     @classmethod
1136     def integer(cls, value, byteorder="little"):
1137         return super().integer(bits=32, value=value, byteorder=byteorder)
1138
1139     @property
1140     def binary(self):
1141         bits = []
1142         for idx in range(32):
1143             bit = int(self[idx])
1144             bits.append(bit)
1145         return "".join(map(str, bits))
1146
1147     def disassemble(self, db,
1148             byteorder="little",
1149             verbosity=Verbosity.NORMAL):
1150         integer = int(self)
1151         if verbosity <= Verbosity.SHORT:
1152             blob = ""
1153         else:
1154             blob = integer.to_bytes(length=4, byteorder=byteorder)
1155             blob = " ".join(map(lambda byte: f"{byte:02x}", blob))
1156             blob += "    "
1157
1158         record = db[self]
1159         if record is None:
1160             yield f"{blob}.long 0x{integer:08x}"
1161             return
1162
1163         operands = tuple(map(_operator.itemgetter(1),
1164             self.dynamic_operands(db=db, verbosity=verbosity)))
1165         if operands:
1166             yield f"{blob}{record.name} {','.join(operands)}"
1167         else:
1168             yield f"{blob}{record.name}"
1169
1170         if verbosity >= Verbosity.VERBOSE:
1171             indent = (" " * 4)
1172             binary = self.binary
1173             spec = self.spec(db=db, prefix="")
1174             yield f"{indent}spec"
1175             yield f"{indent}{indent}{spec}"
1176             yield f"{indent}pcode"
1177             for stmt in record.mdwn.pcode:
1178                 yield f"{indent}{indent}{stmt}"
1179             yield f"{indent}binary"
1180             yield f"{indent}{indent}[0:8]   {binary[0:8]}"
1181             yield f"{indent}{indent}[8:16]  {binary[8:16]}"
1182             yield f"{indent}{indent}[16:24] {binary[16:24]}"
1183             yield f"{indent}{indent}[24:32] {binary[24:32]}"
1184             yield f"{indent}opcodes"
1185             for opcode in record.opcodes:
1186                 yield f"{indent}{indent}{opcode!r}"
1187             for operand in record.mdwn.operands:
1188                 yield from operand.disassemble(insn=self, record=record,
1189                     verbosity=verbosity, indent=indent)
1190             yield ""
1191
1192
1193 class PrefixedInstruction(Instruction):
1194     class Prefix(WordInstruction.remap(range(0, 32))):
1195         pass
1196
1197     class Suffix(WordInstruction.remap(range(32, 64))):
1198         pass
1199
1200     _: _Field = range(64)
1201     prefix: Prefix
1202     suffix: Suffix
1203     po: Suffix.po
1204
1205     @classmethod
1206     def integer(cls, value, byteorder="little"):
1207         return super().integer(bits=64, value=value, byteorder=byteorder)
1208
1209     @classmethod
1210     def pair(cls, prefix=0, suffix=0, byteorder="little"):
1211         def transform(value):
1212             return WordInstruction.integer(value=value,
1213                 byteorder=byteorder)[0:32]
1214
1215         (prefix, suffix) = map(transform, (prefix, suffix))
1216         value = _selectconcat(prefix, suffix)
1217
1218         return super().integer(bits=64, value=value)
1219
1220
1221 class Mode(_Mapping):
1222     _: _Field = range(0, 5)
1223
1224
1225 class Extra(_Mapping):
1226     _: _Field = range(0, 9)
1227
1228
1229 class Extra2(Extra):
1230     idx0: _Field = range(0, 2)
1231     idx1: _Field = range(2, 4)
1232     idx2: _Field = range(4, 6)
1233     idx3: _Field = range(6, 8)
1234
1235     def __getitem__(self, key):
1236         return {
1237             0: self.idx0,
1238             1: self.idx1,
1239             2: self.idx2,
1240             3: self.idx3,
1241             _SVExtra.Idx0: self.idx0,
1242             _SVExtra.Idx1: self.idx1,
1243             _SVExtra.Idx2: self.idx2,
1244             _SVExtra.Idx3: self.idx3,
1245         }[key]
1246
1247     def __setitem__(self, key, value):
1248         self[key].assign(value)
1249
1250
1251 class Extra3(Extra):
1252     idx0: _Field = range(0, 3)
1253     idx1: _Field = range(3, 6)
1254     idx2: _Field = range(6, 9)
1255
1256     def __getitem__(self, key):
1257         return {
1258             0: self.idx0,
1259             1: self.idx1,
1260             2: self.idx2,
1261             _SVExtra.Idx0: self.idx0,
1262             _SVExtra.Idx1: self.idx1,
1263             _SVExtra.Idx2: self.idx2,
1264         }[key]
1265
1266     def __setitem__(self, key, value):
1267         self[key].assign(value)
1268
1269
1270 class BaseRM(_Mapping):
1271     _: _Field = range(24)
1272     mmode: _Field = (0,)
1273     mask: _Field = range(1, 4)
1274     elwidth: _Field = range(4, 6)
1275     ewsrc: _Field = range(6, 8)
1276     subvl: _Field = range(8, 10)
1277     mode: Mode.remap(range(19, 24))
1278     smask: _Field = range(16, 19)
1279
1280     extra: Extra.remap(range(10, 19))
1281     extra2: Extra2.remap(range(10, 19))
1282     extra3: Extra3.remap(range(10, 19))
1283
1284     @property
1285     def specifiers(self):
1286         subvl = int(self.subvl)
1287         if subvl > 0:
1288             yield {
1289                 1: "vec2",
1290                 2: "vec3",
1291                 3: "vec4",
1292             }[subvl]
1293
1294     def disassemble(self, verbosity=Verbosity.NORMAL):
1295         if verbosity >= Verbosity.VERBOSE:
1296             indent = (" " * 4)
1297             for (name, value, members) in self.traverse(path="RM"):
1298                 yield f"{name}"
1299                 yield f"{indent}{int(value):0{value.bits}b}"
1300                 yield f"{indent}{', '.join(map(str, members))}"
1301
1302
1303 class NormalLDSTBaseRM(BaseRM):
1304     @property
1305     def specifiers(self):
1306         width = {
1307             0b11: "8",
1308             0b10: "16",
1309             0b01: "32",
1310         }
1311
1312         dw = int(self.elwidth)
1313         sw = int(self.ewsrc)
1314         if all((dw, sw)) and dw == sw:
1315             yield f"w={width[dw]}"
1316         else:
1317             if dw != 0b00:
1318                 yield f"dw={width[dw]}"
1319             if sw != 0b00:
1320                 yield f"sw={width[sw]}"
1321
1322         yield from super().specifiers
1323
1324
1325 class NormalBaseRM(NormalLDSTBaseRM):
1326     pass
1327
1328
1329 class NormalSimpleRM(NormalBaseRM):
1330     """normal: simple mode"""
1331     dz: BaseRM.mode[3]
1332     sz: BaseRM.mode[4]
1333
1334     @property
1335     def specifiers(self):
1336         if self.dz:
1337             yield f"dz"
1338         if self.sz:
1339             yield f"sz"
1340         yield from super().specifiers
1341
1342
1343 class NormalScalarReduceRM(NormalBaseRM):
1344     """normal: scalar reduce mode (mapreduce), SUBVL=1"""
1345     RG: BaseRM.mode[4]
1346
1347     @property
1348     def specifiers(self):
1349         if self.RG:
1350             yield "mrr"
1351
1352         yield from super().specifiers
1353
1354
1355 class NormalReservedRM(NormalBaseRM):
1356     """normal: reserved"""
1357     pass
1358
1359
1360 class NormalFailFirstRc1RM(NormalBaseRM):
1361     """normal: Rc=1: ffirst CR sel"""
1362     inv: BaseRM.mode[2]
1363     CR: BaseRM.mode[3, 4]
1364
1365
1366 class NormalFailFirstRc0RM(NormalBaseRM):
1367     """normal: Rc=0: ffirst z/nonz"""
1368     inv: BaseRM.mode[2]
1369     VLi: BaseRM.mode[3]
1370     RC1: BaseRM.mode[4]
1371
1372
1373 class NormalSaturationRM(NormalBaseRM):
1374     """normal: sat mode: N=0/1 u/s, SUBVL=1"""
1375     N: BaseRM.mode[2]
1376     dz: BaseRM.mode[3]
1377     sz: BaseRM.mode[4]
1378
1379     @property
1380     def specifiers(self):
1381         if self.dz:
1382             yield f"dz"
1383         if self.sz:
1384             yield f"sz"
1385         if self.N:
1386             yield "sats"
1387         else:
1388             yield "satu"
1389         yield from super().specifiers
1390
1391
1392 class NormalPredResultRc1RM(NormalBaseRM):
1393     """normal: Rc=1: pred-result CR sel"""
1394     inv: BaseRM.mode[2]
1395     CR: BaseRM.mode[3, 4]
1396
1397
1398 class NormalPredResultRc0RM(NormalBaseRM):
1399     """normal: Rc=0: pred-result z/nonz"""
1400     inv: BaseRM.mode[2]
1401     zz: BaseRM.mode[3]
1402     RC1: BaseRM.mode[4]
1403     dz: BaseRM.mode[3]
1404     sz: BaseRM.mode[3]
1405
1406     @property
1407     def specifiers(self):
1408         if self.zz:
1409             yield f"zz"
1410         yield from super().specifiers
1411
1412
1413 class NormalRM(NormalBaseRM):
1414     simple: NormalSimpleRM
1415     smr: NormalScalarReduceRM
1416     reserved: NormalReservedRM
1417     ffrc1: NormalFailFirstRc1RM
1418     ffrc0: NormalFailFirstRc0RM
1419     sat: NormalSaturationRM
1420     prrc1: NormalPredResultRc1RM
1421     prrc0: NormalPredResultRc0RM
1422
1423
1424 class LDSTImmBaseRM(NormalLDSTBaseRM):
1425     pass
1426
1427
1428 class LDSTImmSimpleRM(LDSTImmBaseRM):
1429     """ld/st immediate: simple mode"""
1430     zz: BaseRM.mode[3]
1431     els: BaseRM.mode[4]
1432     dz: BaseRM.mode[3]
1433     sz: BaseRM.mode[3]
1434
1435     @property
1436     def specifiers(self):
1437         if self.zz:
1438             yield f"zz"
1439         yield from super().specifiers
1440
1441
1442 class LDSTImmReservedRM(LDSTImmBaseRM):
1443     """ld/st immediate: reserved"""
1444     pass
1445
1446
1447 class LDSTImmFailFirstRc1RM(LDSTImmBaseRM):
1448     """ld/st immediate: Rc=1: ffirst CR sel"""
1449     inv: BaseRM.mode[2]
1450     CR: BaseRM.mode[3, 4]
1451
1452
1453 class LDSTImmFailFirstRc0RM(LDSTImmBaseRM):
1454     """ld/st immediate: Rc=0: ffirst z/nonz"""
1455     inv: BaseRM.mode[2]
1456     els: BaseRM.mode[3]
1457     RC1: BaseRM.mode[4]
1458
1459
1460 class LDSTImmSaturationRM(LDSTImmBaseRM):
1461     """ld/st immediate: sat mode: N=0/1 u/s"""
1462     N: BaseRM.mode[2]
1463     zz: BaseRM.mode[3]
1464     els: BaseRM.mode[4]
1465     dz: BaseRM.mode[3]
1466     sz: BaseRM.mode[3]
1467
1468     @property
1469     def specifiers(self):
1470         if self.zz:
1471             yield f"zz"
1472         if self.N:
1473             yield "sats"
1474         else:
1475             yield "satu"
1476         yield from super().specifiers
1477
1478
1479 class LDSTImmPredResultRc1RM(LDSTImmBaseRM):
1480     """ld/st immediate: Rc=1: pred-result CR sel"""
1481     inv: BaseRM.mode[2]
1482     CR: BaseRM.mode[3, 4]
1483
1484
1485 class LDSTImmPredResultRc0RM(LDSTImmBaseRM):
1486     """ld/st immediate: Rc=0: pred-result z/nonz"""
1487     inv: BaseRM.mode[2]
1488     els: BaseRM.mode[3]
1489     RC1: BaseRM.mode[4]
1490
1491
1492 class LDSTImmRM(LDSTImmBaseRM):
1493     simple: LDSTImmSimpleRM
1494     reserved: LDSTImmReservedRM
1495     ffrc1: LDSTImmFailFirstRc1RM
1496     ffrc0: LDSTImmFailFirstRc0RM
1497     sat: LDSTImmSaturationRM
1498     prrc1: LDSTImmPredResultRc1RM
1499     prrc0: LDSTImmPredResultRc0RM
1500
1501
1502 class LDSTIdxBaseRM(NormalLDSTBaseRM):
1503     pass
1504
1505
1506 class LDSTIdxSimpleRM(LDSTIdxBaseRM):
1507     """ld/st index: simple mode"""
1508     SEA: BaseRM.mode[2]
1509     sz: BaseRM.mode[3]
1510     dz: BaseRM.mode[3]
1511
1512     @property
1513     def specifiers(self):
1514         if self.dz:
1515             yield f"dz"
1516         if self.sz:
1517             yield f"sz"
1518         yield from super().specifiers
1519
1520
1521 class LDSTIdxStrideRM(LDSTIdxBaseRM):
1522     """ld/st index: strided (scalar only source)"""
1523     SEA: BaseRM.mode[2]
1524     dz: BaseRM.mode[3]
1525     sz: BaseRM.mode[4]
1526
1527     @property
1528     def specifiers(self):
1529         if self.dz:
1530             yield f"dz"
1531         if self.sz:
1532             yield f"sz"
1533         yield from super().specifiers
1534
1535
1536 class LDSTIdxSaturationRM(LDSTIdxBaseRM):
1537     """ld/st index: sat mode: N=0/1 u/s"""
1538     N: BaseRM.mode[2]
1539     dz: BaseRM.mode[3]
1540     sz: BaseRM.mode[4]
1541
1542     @property
1543     def specifiers(self):
1544         if self.dz:
1545             yield f"dz"
1546         if self.sz:
1547             yield f"sz"
1548         if self.N:
1549             yield "sats"
1550         else:
1551             yield "satu"
1552         yield from super().specifiers
1553
1554
1555 class LDSTIdxPredResultRc1RM(LDSTIdxBaseRM):
1556     """ld/st index: Rc=1: pred-result CR sel"""
1557     inv: BaseRM.mode[2]
1558     CR: BaseRM.mode[3, 4]
1559
1560
1561 class LDSTIdxPredResultRc0RM(LDSTIdxBaseRM):
1562     """ld/st index: Rc=0: pred-result z/nonz"""
1563     inv: BaseRM.mode[2]
1564     zz: BaseRM.mode[3]
1565     RC1: BaseRM.mode[4]
1566     dz: BaseRM.mode[3]
1567     sz: BaseRM.mode[3]
1568
1569     @property
1570     def specifiers(self):
1571         if self.zz:
1572             yield f"zz"
1573         yield from super().specifiers
1574
1575
1576 class LDSTIdxRM(LDSTIdxBaseRM):
1577     simple: LDSTIdxSimpleRM
1578     stride: LDSTIdxStrideRM
1579     sat: LDSTIdxSaturationRM
1580     prrc1: LDSTIdxPredResultRc1RM
1581     prrc0: LDSTIdxPredResultRc0RM
1582
1583
1584 class CROpBaseRM(BaseRM):
1585     pass
1586
1587
1588 class CROpSimpleRM(CROpBaseRM):
1589     """cr_op: simple mode"""
1590     sz: BaseRM[6]
1591     SNZ: BaseRM[7]
1592     RG: BaseRM[20]
1593     dz: BaseRM[22]
1594
1595     @property
1596     def specifiers(self):
1597         if self.dz:
1598             yield f"dz"
1599         if self.sz:
1600             yield f"sz"
1601         if self.RG:
1602             yield "mrr"
1603
1604         yield from super().specifiers
1605
1606
1607 class CROpScalarReduceRM(CROpBaseRM):
1608     """cr_op: scalar reduce mode (mapreduce), SUBVL=1"""
1609     sz: BaseRM[6]
1610     SNZ: BaseRM[7]
1611     RG: BaseRM[20]
1612
1613     @property
1614     def specifiers(self):
1615         if self.sz:
1616             yield f"sz"
1617         if self.RG:
1618             yield "mrr"
1619
1620         yield from super().specifiers
1621
1622
1623 class CROpReservedRM(CROpBaseRM):
1624     """cr_op: reserved"""
1625     zz: BaseRM[6]
1626     SNZ: BaseRM[7]
1627     RG: BaseRM[20]
1628     dz: BaseRM[6]
1629     sz: BaseRM[6]
1630
1631     @property
1632     def specifiers(self):
1633         if self.zz:
1634             yield f"zz"
1635         if self.RG:
1636             yield "mrr"
1637
1638         yield from super().specifiers
1639
1640
1641 class CROpFailFirst3RM(CROpBaseRM):
1642     """cr_op: ffirst 3-bit mode"""
1643     zz: BaseRM[6]
1644     SNZ: BaseRM[7]
1645     VLI: BaseRM[20]
1646     inv: BaseRM[21]
1647     CR: BaseRM[22, 23]
1648     dz: BaseRM[6]
1649     sz: BaseRM[6]
1650
1651     @property
1652     def specifiers(self):
1653         if self.zz:
1654             yield f"zz"
1655         yield from super().specifiers
1656
1657
1658 class CROpFailFirst5RM(CROpBaseRM):
1659     """cr_op: ffirst 5-bit mode"""
1660     sz: BaseRM[6]
1661     SNZ: BaseRM[7]
1662     VLI: BaseRM[20]
1663     inv: BaseRM[21]
1664     dz: BaseRM[22]
1665
1666     @property
1667     def specifiers(self):
1668         if self.dz:
1669             yield f"dz"
1670         if self.sz:
1671             yield f"sz"
1672         yield from super().specifiers
1673
1674
1675 class CROpRM(CROpBaseRM):
1676     simple: CROpSimpleRM
1677     smr: CROpScalarReduceRM
1678     reserved: CROpReservedRM
1679     ff3: CROpFailFirst3RM
1680     ff5: CROpFailFirst5RM
1681
1682
1683 class BranchBaseRM(BaseRM):
1684     ALL: BaseRM[4]
1685     SNZ: BaseRM[5]
1686     SL: BaseRM[17]
1687     SLu: BaseRM[18]
1688     LRu: BaseRM[22]
1689     sz: BaseRM[23]
1690
1691
1692 class BranchSimpleRM(BranchBaseRM):
1693     """branch: simple mode"""
1694     pass
1695
1696
1697 class BranchVLSRM(BranchBaseRM):
1698     """branch: VLSET mode"""
1699     VSb: BaseRM[7]
1700     VLI: BaseRM[21]
1701
1702
1703 class BranchCTRRM(BranchBaseRM):
1704     """branch: CTR-test mode"""
1705     CTi: BaseRM[6]
1706
1707
1708 class BranchCTRVLSRM(BranchVLSRM, BranchCTRRM):
1709     """branch: CTR-test+VLSET mode"""
1710     pass
1711
1712
1713 class BranchRM(BranchBaseRM):
1714     simple: BranchSimpleRM
1715     vls: BranchVLSRM
1716     ctr: BranchCTRRM
1717     ctrvls: BranchCTRVLSRM
1718
1719
1720 class RM(BaseRM):
1721     normal: NormalRM
1722     ldst_imm: LDSTImmRM
1723     ldst_idx: LDSTIdxRM
1724     cr_op: CROpRM
1725
1726     def select(self, record, Rc):
1727         rm = self
1728
1729         if record.svp64.mode is _SVMode.NORMAL:
1730             # concatenate mode 5-bit with Rc (LSB) then do a mask/map search
1731             #         mode   Rc   mask Rc  action(getattr)
1732             table = [(0b000000, 0b111000, "simple"), # simple    (no Rc)
1733                      (0b001000, 0b111000, "smr"),    # mapreduce (no Rc)
1734                      (0b010000, 0b110001, "ffrc0"),  # ffirst,    Rc=0
1735                      (0b010001, 0b110001, "ffrc1"),  # ffirst,    Rc=1
1736                      (0b100000, 0b110000, "sat"),    # saturation(no Rc)
1737                      (0b110000, 0b110001, "prrc0"),  # predicate, Rc=0
1738                      (0b110001, 0b110001, "prrc1"),  # predicate, Rc=1
1739                     ]
1740
1741             rm = rm.normal
1742             search = (int(rm.mode) << 1) | Rc
1743             for (val, mask, action) in table:
1744                 if (val&search) == (mask&search):
1745                     rm = getattr(rm, action)
1746                     break
1747
1748         elif record.svp64.mode is _SVMode.LDST_IMM:
1749             # concatenate mode 5-bit with Rc (LSB) then do a mask/map search
1750             #         mode   Rc   mask Rc  action(getattr)
1751             # ironically/coincidentally this table is identical to NORMAL
1752             # mode except reserved in place of smr
1753             table = [(0b000000, 0b111000, "simple"), # simple    (no Rc)
1754                      (0b001000, 0b111000, "reserved"), # rsvd (no Rc)
1755                      (0b010000, 0b110001, "ffrc0"),  # ffirst,    Rc=0
1756                      (0b010001, 0b110001, "ffrc1"),  # ffirst,    Rc=1
1757                      (0b100000, 0b110000, "sat"),    # saturation(no Rc)
1758                      (0b110000, 0b110001, "prrc0"),  # predicate, Rc=0
1759                      (0b110001, 0b110001, "prrc1"),  # predicate, Rc=1
1760                     ]
1761             rm = rm.ldst_imm
1762             search = (int(rm.mode) << 1) | Rc
1763             for (val, mask, action) in table:
1764                 if (val&search) == (mask&search):
1765                     rm = getattr(rm, action)
1766                     break
1767
1768         elif record.svp64.mode is _SVMode.LDST_IMM:
1769             rm = rm.ldst_idx
1770             if rm.mode[0:2] == 0b00:
1771                 rm = rm.simple
1772             elif rm.mode[0:2] == 0b01:
1773                 rm = rm.stride
1774             elif rm.mode[0:2] == 0b10:
1775                 rm = rm.sat
1776             elif rm.mode[0:2] == 0b11:
1777                 if Rc:
1778                     rm = rm.prrc1
1779                 else:
1780                     rm = rm.prrc0
1781
1782         elif record.svp64.mode is _SVMode.CROP:
1783             rm = rm.cr_op
1784             if rm[19] == 0b0:
1785                 if rm[21] == 0b0:
1786                     rm = rm.simple
1787                 else:
1788                     rm = rm.smr
1789             else:
1790                 regtype = None
1791                 for idx in range(0, 4):
1792                     for entry in record.svp64.extra[idx]:
1793                         if entry.regtype is _SVExtraRegType.DST:
1794                             if regtype is not None:
1795                                 raise ValueError(record.svp64)
1796                             regtype = _RegType(entry.reg)
1797                 if regtype is _RegType.CR_REG:
1798                     rm = rm.ff5
1799                 elif regtype is _RegType.CR_BIT:
1800                     rm = rm.ff3
1801                 else:
1802                     raise ValueError(record.svp64)
1803
1804         elif record.svp64.mode is _SVMode.BRANCH:
1805             if rm[19] == 0b0:
1806                 if rm[20] == 0b0:
1807                     rm = rm.simple
1808                 else:
1809                     rm = rm.vls
1810             else:
1811                 if rm[20] == 0b0:
1812                     rm = rm.ctr
1813                 else:
1814                     rm = rm.ctrvls
1815
1816         if rm.__class__ is self.__class__:
1817             raise ValueError(self)
1818
1819         return rm
1820
1821
1822 class SVP64Instruction(PrefixedInstruction):
1823     """SVP64 instruction: https://libre-soc.org/openpower/sv/svp64/"""
1824     class Prefix(PrefixedInstruction.Prefix):
1825         id: _Field = (7, 9)
1826         rm: RM.remap((6, 8) + tuple(range(10, 32)))
1827
1828     prefix: Prefix
1829
1830     def record(self, db):
1831         record = db[self.suffix]
1832         if record is None:
1833             raise KeyError(self)
1834         return record
1835
1836     @property
1837     def binary(self):
1838         bits = []
1839         for idx in range(64):
1840             bit = int(self[idx])
1841             bits.append(bit)
1842         return "".join(map(str, bits))
1843
1844     def disassemble(self, db,
1845             byteorder="little",
1846             verbosity=Verbosity.NORMAL):
1847         def blob(integer):
1848             if verbosity <= Verbosity.SHORT:
1849                 return ""
1850             else:
1851                 blob = integer.to_bytes(length=4, byteorder=byteorder)
1852                 blob = " ".join(map(lambda byte: f"{byte:02x}", blob))
1853                 return f"{blob}    "
1854
1855         record = self.record(db=db)
1856         blob_prefix = blob(int(self.prefix))
1857         blob_suffix = blob(int(self.suffix))
1858         if record is None or record.svp64 is None:
1859             yield f"{blob_prefix}.long 0x{int(self.prefix):08x}"
1860             yield f"{blob_suffix}.long 0x{int(self.suffix):08x}"
1861             return
1862
1863         name = f"sv.{record.name}"
1864
1865         Rc = False
1866         if record.mdwn.operands["Rc"] is not None:
1867             Rc = bool(self.suffix[record.fields["Rc"]])
1868         rm = self.prefix.rm.select(record=record, Rc=Rc)
1869
1870         specifiers = tuple(rm.specifiers)
1871         if specifiers:
1872             specifiers = f"/{'/'.join(specifiers)}"
1873         else:
1874             specifiers = ""
1875
1876         operands = tuple(map(_operator.itemgetter(1),
1877             self.dynamic_operands(db=db, verbosity=verbosity)))
1878         if operands:
1879             operands = f" {','.join(operands)}"
1880         else:
1881             operands = ""
1882
1883         yield f"{blob_prefix}{name}{specifiers}{operands}"
1884         if blob_suffix:
1885             yield f"{blob_suffix}"
1886
1887         if verbosity >= Verbosity.VERBOSE:
1888             indent = (" " * 4)
1889             binary = self.binary
1890             spec = self.spec(db=db, prefix="sv.")
1891
1892             yield f"{indent}spec"
1893             yield f"{indent}{indent}{spec}"
1894             yield f"{indent}pcode"
1895             for stmt in record.mdwn.pcode:
1896                 yield f"{indent}{indent}{stmt}"
1897             yield f"{indent}binary"
1898             yield f"{indent}{indent}[0:8]   {binary[0:8]}"
1899             yield f"{indent}{indent}[8:16]  {binary[8:16]}"
1900             yield f"{indent}{indent}[16:24] {binary[16:24]}"
1901             yield f"{indent}{indent}[24:32] {binary[24:32]}"
1902             yield f"{indent}{indent}[32:40] {binary[32:40]}"
1903             yield f"{indent}{indent}[40:48] {binary[40:48]}"
1904             yield f"{indent}{indent}[48:56] {binary[48:56]}"
1905             yield f"{indent}{indent}[56:64] {binary[56:64]}"
1906             yield f"{indent}opcodes"
1907             for opcode in record.opcodes:
1908                 yield f"{indent}{indent}{opcode!r}"
1909             for operand in record.mdwn.operands:
1910                 yield from operand.disassemble(insn=self, record=record,
1911                     verbosity=verbosity, indent=indent)
1912             yield f"{indent}RM"
1913             yield f"{indent}{indent}{rm.__doc__}"
1914             for line in rm.disassemble(verbosity=verbosity):
1915                 yield f"{indent}{indent}{line}"
1916             yield ""
1917
1918
1919 def parse(stream, factory):
1920     def match(entry):
1921         return ("TODO" not in frozenset(entry.values()))
1922
1923     lines = filter(lambda line: not line.strip().startswith("#"), stream)
1924     entries = _csv.DictReader(lines)
1925     entries = filter(match, entries)
1926     return tuple(map(factory, entries))
1927
1928
1929 class MarkdownDatabase:
1930     def __init__(self):
1931         db = {}
1932         for (name, desc) in _ISA():
1933             operands = []
1934             if desc.regs:
1935                 (dynamic, *static) = desc.regs
1936                 operands.extend(dynamic)
1937                 operands.extend(static)
1938             pcode = PCode(iterable=desc.pcode)
1939             operands = Operands(insn=name, iterable=operands)
1940             db[name] = MarkdownRecord(pcode=pcode, operands=operands)
1941
1942         self.__db = db
1943
1944         return super().__init__()
1945
1946     def __iter__(self):
1947         yield from self.__db.items()
1948
1949     def __contains__(self, key):
1950         return self.__db.__contains__(key)
1951
1952     def __getitem__(self, key):
1953         return self.__db.__getitem__(key)
1954
1955
1956 class FieldsDatabase:
1957     def __init__(self):
1958         db = {}
1959         df = _DecodeFields()
1960         df.create_specs()
1961         for (form, fields) in df.instrs.items():
1962             if form in {"DQE", "TX"}:
1963                 continue
1964             if form == "all":
1965                 form = "NONE"
1966             db[_Form[form]] = Fields(fields)
1967
1968         self.__db = db
1969
1970         return super().__init__()
1971
1972     def __getitem__(self, key):
1973         return self.__db.__getitem__(key)
1974
1975
1976 class PPCDatabase:
1977     def __init__(self, root, mdwndb):
1978         # The code below groups the instructions by section:identifier.
1979         # We use the comment as an identifier, there's nothing better.
1980         # The point is to capture different opcodes for the same instruction.
1981         dd = _collections.defaultdict
1982         records = dd(lambda: dd(set))
1983         path = (root / "insndb.csv")
1984         with open(path, "r", encoding="UTF-8") as stream:
1985             for section in parse(stream, Section.CSV):
1986                 path = (root / section.path)
1987                 opcode_cls = {
1988                     section.Mode.INTEGER: IntegerOpcode,
1989                     section.Mode.PATTERN: PatternOpcode,
1990                 }[section.mode]
1991                 factory = _functools.partial(
1992                     PPCRecord.CSV, opcode_cls=opcode_cls)
1993                 with open(path, "r", encoding="UTF-8") as stream:
1994                     for insn in parse(stream, factory):
1995                         records[section][insn.comment].add(insn)
1996
1997         sections = dd(set)
1998         for (section, group) in records.items():
1999             for records in group.values():
2000                 sections[section].add(PPCMultiRecord(records))
2001
2002         db = {}
2003         for (section, records) in sections.items():
2004             for record in records:
2005                 def exact_match(names):
2006                     for name in names:
2007                         if name in mdwndb:
2008                             yield name
2009
2010                 def Rc_match(names):
2011                     for name in names:
2012                         if f"{name}." in mdwndb:
2013                             yield f"{name}."
2014                         yield name
2015
2016                 def LK_match(names):
2017                     if "lk" not in record.flags:
2018                         yield from names
2019                         return
2020
2021                     for name in names:
2022                         if f"{name}l" in mdwndb:
2023                             yield f"{name}l"
2024                         yield name
2025
2026                 def AA_match(names):
2027                     if record.intop not in {_MicrOp.OP_B, _MicrOp.OP_BC}:
2028                         yield from names
2029                         return
2030
2031                     for name in names:
2032                         operands = mdwndb[name].operands["AA"]
2033                         if ((operands is not None) and
2034                                 (f"{name}a" in mdwndb)):
2035                             yield f"{name}a"
2036                         yield name
2037
2038                 def reductor(names, match):
2039                     return match(names)
2040
2041                 matches = (exact_match, Rc_match, LK_match, AA_match)
2042
2043                 names = _functools.reduce(reductor, matches, record.names)
2044                 for name in names:
2045                     db[name] = (section, record)
2046
2047         self.__db = db
2048         self.__mdwndb = mdwndb
2049
2050         return super().__init__()
2051
2052     @_functools.lru_cache(maxsize=512, typed=False)
2053     def __getitem__(self, key):
2054         return self.__db.get(key, (None, None))
2055
2056
2057 class SVP64Database:
2058     def __init__(self, root, ppcdb):
2059         db = set()
2060         pattern = _re.compile(r"^(?:LDST)?RM-(1P|2P)-.*?\.csv$")
2061         for (prefix, _, names) in _os.walk(root):
2062             prefix = _pathlib.Path(prefix)
2063             for name in filter(lambda name: pattern.match(name), names):
2064                 path = (prefix / _pathlib.Path(name))
2065                 with open(path, "r", encoding="UTF-8") as stream:
2066                     db.update(parse(stream, SVP64Record.CSV))
2067
2068         self.__db = {record.name:record for record in db}
2069         self.__ppcdb = ppcdb
2070
2071         return super().__init__()
2072
2073     def __getitem__(self, key):
2074         (_, record) = self.__ppcdb[key]
2075         if record is None:
2076             return None
2077
2078         for name in record.names:
2079             record = self.__db.get(name, None)
2080             if record is not None:
2081                 return record
2082
2083         return None
2084
2085
2086 class Database:
2087     def __init__(self, root):
2088         root = _pathlib.Path(root)
2089         mdwndb = MarkdownDatabase()
2090         fieldsdb = FieldsDatabase()
2091         ppcdb = PPCDatabase(root=root, mdwndb=mdwndb)
2092         svp64db = SVP64Database(root=root, ppcdb=ppcdb)
2093
2094         db = set()
2095         names = {}
2096         opcodes = _collections.defaultdict(set)
2097
2098         for (name, mdwn) in mdwndb:
2099             (section, ppc) = ppcdb[name]
2100             if ppc is None:
2101                 continue
2102             svp64 = svp64db[name]
2103             fields = fieldsdb[ppc.form]
2104             record = Record(name=name,
2105                 section=section, ppc=ppc, svp64=svp64,
2106                 mdwn=mdwn, fields=fields)
2107             db.add(record)
2108             names[record.name] = record
2109             PO = section.opcode
2110             if PO is None:
2111                 PO = ppc[0].opcode
2112             opcodes[PO.value].add(record)
2113
2114         self.__db = db
2115         self.__names = names
2116         self.__opcodes = opcodes
2117
2118         return super().__init__()
2119
2120     def __repr__(self):
2121         return repr(self.__db)
2122
2123     def __iter__(self):
2124         yield from self.__db
2125
2126     @_functools.lru_cache(maxsize=None)
2127     def __contains__(self, key):
2128         return self.__getitem__(key) is not None
2129
2130     @_functools.lru_cache(maxsize=None)
2131     def __getitem__(self, key):
2132         if isinstance(key, (int, Instruction)):
2133             key = int(key)
2134             XO = int(_SelectableInt(value=int(key), bits=32)[0:6])
2135             for record in self.__opcodes[XO]:
2136                 if record.match(key=key):
2137                    return record
2138
2139         elif isinstance(key, str):
2140             return self.__names[key]
2141
2142         return None