src/openpower/decoder/power_pseudo.py

   1 # Based on GardenSnake - a parser generator demonstration program
   2 # GardenSnake was released into the Public Domain by Andrew Dalke.
   3
   4 # Portions of this work are derived from Python's Grammar definition
   5 # and may be covered under the Python copyright and license
   6 #
   7 #          Andrew Dalke / Dalke Scientific Software, LLC
   8 #             30 August 2006 / Cape Town, South Africa
   9
  10 # Modifications for inclusion in PLY distribution
  11 import sys
  12 from pprint import pprint
  13 from copy import copy
  14 from ply import lex, yacc
  15 import astor
  16 import ast
  17
  18 from openpower.decoder.power_decoder import create_pdecode
  19 from nmigen.back.pysim import Simulator, Delay
  20 from nmigen import Module, Signal
  21
  22 from openpower.decoder.pseudo.parser import GardenSnakeCompiler
  23 from openpower.decoder.selectable_int import SelectableInt, selectconcat
  24 from openpower.decoder.isa.caller import GPR, Mem
  25
  26
  27 ####### Test code #######
  28
  29 bpermd = r"""
  30 perm <- [0] * 8
  31 if index < 64:
  32     index <- (RS)[8*i:8*i+7]
  33 RA <- [0]*56 || perm[0:7]
  34 print (RA)
  35 """
  36
  37 bpermd = r"""
  38 if index < 64 then index <- 0
  39 else index <- 5
  40 do while index < 5
  41     index <- 0
  42     leave
  43 for i = 0 to 7
  44     index <- 0
  45 """
  46
  47 _bpermd = r"""
  48 for i = 0 to 7
  49    index <- (RS)[8*i:8*i+7]
  50    if index < 64 then
  51         permi <- (RB)[index]
  52    else
  53         permi <- 0
  54 RA <- [0]*56|| perm[0:7]
  55 """
  56
  57 cnttzd = """
  58 n  <- 0
  59 do while n < 64
  60     print (n)
  61     if (RS)[63-n] = 0b1 then
  62         leave
  63     n  <- n + 1
  64 RA <- EXTZ64(n)
  65 print (RA)
  66 """
  67
  68 cmpi = """
  69 if      a < EXTS(SI) then
  70     c <- 0b100
  71 else if a > EXTS(SI) then
  72     c <- 0b010
  73 """
  74
  75 cmpi = """
  76 RA[0:1] <- 0b11
  77 """
  78
  79 cmpi = """
  80 in_range <-  ((x | y) &
  81               (a | b))
  82 in_range <-  (x + y) - (a + b)
  83 """
  84
  85 cmpi = """
  86 (RA)[0:1] <- 1
  87 src1    <- EXTZ((RA)[56:63])
  88 CR[4*BF+32] <- 0b0
  89 in_range <- src21lo  <= src1 & src1 <=  src21hi
  90 """
  91
  92 cmpeqb = """
  93 src1 <- GPR[RA]
  94 src1 <- src1[0:56]
  95 """
  96
  97 addpcis = """
  98 D <- d0||d1||d2
  99 """
 100
 101 testmul = """
 102 x <- [0] * 16
 103 RT <- (RA) + EXTS(SI || [0]*16)
 104 """
 105
 106 testgetzero = """
 107 RS <- (RA|0)
 108 RS <- RS + 1
 109 print(RS)
 110 """
 111
 112 testcat = """
 113 RT <- (load_data[56:63] || load_data[48:55]
 114     || load_data[40:47] || load_data[32:39]
 115     || load_data[24:31] || load_data[16:23]
 116     || load_data[8:15]  || load_data[0:7])
 117 """
 118
 119 testgpr = """
 120 GPR(5) <- x
 121 """
 122 testmem = """
 123 a <- (RA|0)
 124 b <- (RB|0)
 125 RA <- MEM(RB, 2)
 126 EA <- a + 1
 127 MEM(EA, 1) <- (RS)[56:63]
 128 RB <- RA
 129 RA <- EA
 130 """
 131
 132 testgprslice = """
 133 MEM(EA, 4) <- GPR(r)[32:63]
 134 #x <- x[0][32:63]
 135 """
 136
 137 testdo = r"""
 138 do i = 0 to 7
 139     print(i)
 140 """
 141
 142 testcond = """
 143 ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
 144 cond_ok <- BO[0] | ¬(CR[BI+32] ^  BO[1])
 145 """
 146
 147 lswx = """
 148 if RA = 0 then EA <- 0
 149 else           EA <- (RA)
 150 if NB = 0 then n <-  32
 151 else           n <-  NB
 152 r <- RT - 1
 153 i <- 32
 154 do while n > 0
 155     if i = 32 then
 156         r <- (r + 1) % 32
 157         GPR(r) <- 0
 158     GPR(r)[i:i+7] <- MEM(EA, 1)
 159     i <- i + 8
 160     if i = 64 then i <- 32
 161     EA <- EA + 1
 162     n <- n - 1
 163 """
 164
 165 _lswx = """
 166 GPR(r)[x] <- 1
 167 """
 168
 169 switchtest = """
 170 switch (n)
 171     case(1): x <- 5
 172     case(2): fallthrough
 173     case(3):
 174         x <- 3
 175     case(4): fallthrough
 176     default:
 177         x <- 9
 178 """
 179
 180 hextest = """
 181 RT <- 0x0001_a000_0000_0000
 182 """
 183
 184 SVSTATE_next = """
 185 SVSTATE_NEXT(5)
 186 """
 187
 188 logictest = """
 189 x <- (y * 5) + 3
 190 y <- (z + 5) * 3
 191 """
 192
 193 code = logictest
 194 #code = SVSTATE_next
 195 #code = hextest
 196 #code = lswx
 197 #code = testcond
 198 #code = testdo
 199 #code = _bpermd
 200 #code = testmul
 201 #code = testgetzero
 202 #code = testcat
 203 #code = testgpr
 204 #code = testmem
 205 #code = testgprslice
 206 #code = testreg
 207 #code = cnttzd
 208 #code = cmpi
 209 #code = cmpeqb
 210 #code = addpcis
 211 #code = bpermd
 212
 213
 214 def tolist(num):
 215     l = []
 216     for i in range(64):
 217         l.append(1 if (num & (1 << i)) else 0)
 218     l.reverse()
 219     return l
 220
 221
 222 def get_reg_hex(reg):
 223     return hex(reg.value)
 224
 225
 226 def convert_to_pure_python(pcode):
 227
 228     gsc = GardenSnakeCompiler(form=None, incl_carry=False)
 229
 230     tree = gsc.compile(pcode, mode="exec", filename="string")
 231     tree = ast.fix_missing_locations(tree)
 232     return astor.to_source(tree)
 233
 234
 235 def convert_to_python(pcode, form, incl_carry):
 236
 237     print("form", form)
 238     gsc = GardenSnakeCompiler(form=form, incl_carry=incl_carry)
 239
 240     tree = gsc.compile(pcode, mode="exec", filename="string")
 241     tree = ast.fix_missing_locations(tree)
 242     regsused = {'read_regs': gsc.parser.read_regs,
 243                 'write_regs': gsc.parser.write_regs,
 244                 'uninit_regs': gsc.parser.uninit_regs,
 245                 'special_regs': gsc.parser.special_regs,
 246                 'op_fields': gsc.parser.op_fields}
 247     return astor.to_source(tree), regsused
 248
 249
 250 def test():
 251
 252     gsc = GardenSnakeCompiler(debug=True)
 253
 254     gsc.regfile = {}
 255     for i in range(32):
 256         gsc.regfile[i] = i
 257     gsc.gpr = GPR(None, None, None, gsc.regfile)
 258     gsc.mem = Mem()
 259
 260     _compile = gsc.compile
 261
 262     tree = _compile(code, mode="single", filename="string")
 263     tree = ast.fix_missing_locations(tree)
 264     print(ast.dump(tree))
 265
 266     print("astor dump")
 267     print(astor.dump_tree(tree))
 268     print("to source")
 269     source = astor.to_source(tree)
 270     print(source)
 271
 272     # sys.exit(0)
 273
 274     # Set up the GardenSnake run-time environment
 275     def print_(*args):
 276         print("args", args)
 277         print("-->", " ".join(map(str, args)))
 278
 279     from openpower.decoder.helpers import (EXTS64, EXTZ64, ROTL64, ROTL32, MASK,
 280                                      trunc_div, trunc_rem)
 281
 282     d = {}
 283     d["print"] = print_
 284     d["EXTS64"] = EXTS64
 285     d["EXTZ64"] = EXTZ64
 286     d["trunc_div"] = trunc_div
 287     d["trunc_rem"] = trunc_rem
 288     d["SelectableInt"] = SelectableInt
 289     d["concat"] = selectconcat
 290     d["GPR"] = gsc.gpr
 291     d["MEM"] = gsc.mem
 292     d["memassign"] = gsc.mem.memassign
 293
 294     form = 'X'
 295     gsc.gpr.set_form(form)
 296     getform = gsc.parser.sd.sigforms[form]._asdict()
 297     #print ("getform", form)
 298     # for k, f in getform.items():
 299     #print (k, f)
 300     #d[k] = getform[k]
 301
 302     compiled_code = compile(source, mode="exec", filename="<string>")
 303
 304     m = Module()
 305     comb = m.d.comb
 306     instruction = Signal(32)
 307
 308     m.submodules.decode = decode = gsc.parser.sd
 309     comb += decode.raw_opcode_in.eq(instruction)
 310     sim = Simulator(m)
 311
 312     instr = [0x11111117]
 313
 314     def process():
 315         for ins in instr:
 316             print("0x{:X}".format(ins & 0xffffffff))
 317
 318             # ask the decoder to decode this binary data (endian'd)
 319             yield decode.bigendian.eq(0)  # little / big?
 320             yield instruction.eq(ins)          # raw binary instr.
 321             yield Delay(1e-6)
 322
 323             # uninitialised regs, drop them into dict for function
 324             for rname in gsc.parser.uninit_regs:
 325                 d[rname] = SelectableInt(0, 64)  # uninitialised (to zero)
 326                 print("uninitialised", rname, hex(d[rname].value))
 327
 328             # read regs, drop them into dict for function
 329             for rname in gsc.parser.read_regs:
 330                 regidx = yield getattr(decode.sigforms['X'], rname)
 331                 d[rname] = gsc.gpr[regidx]  # contents of regfile
 332                 d["_%s" % rname] = regidx  # actual register value
 333                 print("read reg", rname, regidx, hex(d[rname].value))
 334
 335             exec(compiled_code, d)  # code gets executed here in dict "d"
 336             print("Done")
 337
 338             print(d.keys())  # shows the variables that may have been created
 339
 340             print(decode.sigforms['X'])
 341             x = yield decode.sigforms['X'].RS
 342             ra = yield decode.sigforms['X'].RA
 343             rb = yield decode.sigforms['X'].RB
 344             print("RA", ra, d['RA'])
 345             print("RB", rb, d['RB'])
 346             print("RS", x)
 347
 348             for wname in gsc.parser.write_regs:
 349                 reg = getform[wname]
 350                 regidx = yield reg
 351                 print("write regs", regidx, wname, d[wname], reg)
 352                 gsc.gpr[regidx] = d[wname]
 353
 354     sim.add_process(process)
 355     with sim.write_vcd("simulator.vcd", "simulator.gtkw",
 356                        traces=decode.ports()):
 357         sim.run()
 358
 359     gsc.gpr.dump()
 360
 361     for i in range(0, len(gsc.mem.mem), 16):
 362         hexstr = []
 363         for j in range(16):
 364             hexstr.append("%02x" % gsc.mem.mem[i+j])
 365         hexstr = ' '.join(hexstr)
 366         print("mem %4x" % i, hexstr)
 367
 368
 369 if __name__ == '__main__':
 370     test()