src/openpower/decoder/power_svp64.py

   1 # SPDX-License-Identifier: LGPLv3+
   2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3 # Funded by NLnet http://nlnet.nl
   4
   5 from openpower.decoder.power_enums import get_csv, find_wiki_dir
   6 import os
   7
   8 # identifies register by type
   9 def is_CR_3bit(regname):
  10     return regname in ['BF', 'BFA']
  11
  12 def is_CR_5bit(regname):
  13     return regname in ['BA', 'BB', 'BC', 'BI', 'BT']
  14
  15 def is_GPR(regname):
  16     return regname in ['RA', 'RB', 'RC', 'RS', 'RT']
  17
  18 def is_FPR(regname):
  19     return regname in ['FRA', 'FRB', 'FRC', 'FRS', 'FRT']
  20
  21 def get_regtype(regname):
  22     if is_CR_3bit(regname):
  23         return "CR_3bit"
  24     if is_CR_5bit(regname):
  25         return "CR_5bit"
  26     if is_GPR(regname):
  27         return "GPR"
  28     if is_FPR(regname):
  29         return "FPR"
  30
  31
  32 def decode_extra(rm, prefix='', verbose=True):
  33     # first turn the svp64 rm into a "by name" dict, recording
  34     # which position in the RM EXTRA it goes into
  35     # also: record if the src or dest was a CR, for sanity-checking
  36     # (elwidth overrides on CRs are banned)
  37     dest_reg_cr, src_reg_cr = False, False
  38     svp64_srcreg_byname = {}
  39     svp64_destreg_byname = {}
  40     if verbose:
  41         print ("decode_extra RM", rm)
  42     for i in range(4):
  43         rfield = rm[prefix+str(i)]
  44         if not rfield or rfield == '0':
  45             continue
  46         if verbose:
  47             print ("EXTRA field", i, rfield)
  48         rfield = rfield.split(";") # s:RA;d:CR1 etc.
  49         for r in rfield:
  50             rtype = r[0]
  51             # TODO: ignoring s/d makes it impossible to do
  52             # LD/ST-with-update.
  53             r = r[2:] # ignore s: and d:
  54             if rtype == 'd':
  55                 svp64_destreg_byname[r] = i # dest reg in EXTRA position 0-3
  56             else:
  57                 svp64_srcreg_byname[r] = i # src reg in EXTRA position 0-3
  58             # check the regtype (if CR, record that)
  59             regtype = get_regtype(r)
  60             if regtype in ['CR_3bit', 'CR_5bit']:
  61                 if rtype == 'd':
  62                     dest_reg_cr = True
  63                 if rtype == 's':
  64                     src_reg_cr = True
  65
  66     return dest_reg_cr, src_reg_cr, svp64_srcreg_byname, svp64_destreg_byname
  67
  68
  69 # gets SVP64 ReMap information
  70 class SVP64RM:
  71     def __init__(self, microwatt_format=False):
  72         """SVP64RM: gets micro-opcode information
  73
  74         microwatt_format: moves RS to in1 (to match decode1.vhdl)
  75         """
  76         self.instrs = {}
  77         self.svp64_instrs = {}
  78         self.verbose = False
  79         pth = find_wiki_dir()
  80         for fname in os.listdir(pth):
  81             if fname.startswith("RM") or fname.startswith("LDSTRM"):
  82                 for entry in get_csv(fname):
  83                     if microwatt_format:
  84                         # move RS from position 1 to position 3, to match
  85                         # microwatt decode1.vhdl format
  86                         if entry['in1'] == 'RS' and entry['in3'] == 'NONE':
  87                             entry['in1'] = 'NONE'
  88                             entry['in3'] = 'RS'
  89                     self.instrs[entry['insn']] = entry
  90
  91
  92     def get_svp64_csv(self, fname):
  93         # first get the v3.0B entries
  94         v30b = get_csv(fname)
  95
  96         # now add the RM fields (for each instruction)
  97         for entry in v30b:
  98             # *sigh* create extra field "out2" based on LD/ST update
  99             # KEEP TRACK HERE https://bugs.libre-soc.org/show_bug.cgi?id=619
 100             entry['out2'] = 'NONE'
 101             if entry['upd'] == '1':
 102                 entry['out2'] = 'RA'
 103
 104             # dummy (blank) fields, first
 105             entry.update({'EXTRA0': '0', 'EXTRA1': '0', 'EXTRA2': '0',
 106                           'EXTRA3': '0',
 107                           'SV_Ptype': 'NONE', 'SV_Etype': 'NONE',
 108                           'sv_cr_in': 'NONE', 'sv_cr_out': 'NONE'})
 109             for fname in ['in1', 'in2', 'in3', 'out', 'out2']:
 110                 entry['sv_%s' % fname] = 'NONE'
 111
 112             # is this SVP64-augmented?
 113             asmcode = entry['comment']
 114             if asmcode not in self.instrs:
 115                 continue
 116
 117             # start updating the fields, merge relevant info
 118             svp64 = self.instrs[asmcode]
 119             for k, v in {'EXTRA0': '0', 'EXTRA1': '1', 'EXTRA2': '2',
 120                           'EXTRA3': '3',
 121                           'SV_Ptype': 'Ptype', 'SV_Etype': 'Etype'}.items():
 122                 entry[k] = svp64[v]
 123
 124             # hmm, we need something more useful: a cross-association
 125             # of the in1/2/3 and CR in/out with the EXTRA0-3 fields
 126             decode = decode_extra(entry, "EXTRA", self.verbose)
 127             dest_reg_cr, src_reg_cr, svp64_src, svp64_dest = decode
 128
 129             # now examine in1/2/3/out, create sv_in1/2/3/out
 130             for fname in ['in1', 'in2', 'in3', 'out', 'out2']:
 131                 regfield = entry[fname]
 132                 extra_index = None
 133                 if regfield == 'RA_OR_ZERO':
 134                     regfield = 'RA'
 135                 if self.verbose:
 136                     print (asmcode, regfield, fname, svp64_dest, svp64_src)
 137                 # find the reg in the SVP64 extra map
 138                 if (fname in ['out', 'out2'] and regfield in svp64_dest):
 139                     extra_index = svp64_dest[regfield]
 140                 if (fname not in ['out', 'out2'] and regfield in svp64_src):
 141                     extra_index = svp64_src[regfield]
 142                 # ta-daa, we know in1/2/3/out's bit-offset
 143                 if extra_index is not None:
 144                     entry['sv_%s' % fname] = "Idx"+str(extra_index)
 145
 146             # TODO: CRs a little tricky, the power_enums.CRInSel is a bit odd.
 147             # ignore WHOLE_REG for now
 148             cr_in = entry['CR in']
 149             extra_index = 'NONE'
 150             if cr_in in svp64_src:
 151                 entry['sv_cr_in'] = "Idx"+str(svp64_src[cr_in])
 152             elif cr_in == 'BA_BB':
 153                 index1 = svp64_src.get('BA', None)
 154                 index2 = svp64_src.get('BB', None)
 155                 entry['sv_cr_in'] = "Idx_%d_%d" % (index1, index2)
 156
 157             # CRout a lot easier.  ignore WHOLE_REG for now
 158             cr_out = entry['CR out']
 159             extra_index = svp64_dest.get(cr_out, None)
 160             if extra_index is not None:
 161                 entry['sv_cr_out'] = 'Idx%d' % extra_index
 162
 163             # more enum-friendly Ptype names.  should have done this in
 164             # sv_analysis.py, oh well
 165             if entry['SV_Ptype'] == '1P':
 166                 entry['SV_Ptype'] = 'P1'
 167             if entry['SV_Ptype'] == '2P':
 168                 entry['SV_Ptype'] = 'P2'
 169             self.svp64_instrs[asmcode] = entry
 170
 171         return v30b
 172
 173 if __name__ == '__main__':
 174     isa = SVP64RM()
 175     minor_31 = isa.get_svp64_csv("minor_31.csv")
 176     for entry in minor_31:
 177         if entry['comment'].startswith('ldu'):
 178             print ("entry", entry)
 179     minor_19 = isa.get_svp64_csv("minor_19.csv")
 180     for entry in minor_19:
 181         if entry['comment'].startswith('cr'):
 182             print (entry)
 183     minor_31 = isa.get_svp64_csv("minor_31.csv")
 184     for entry in minor_31:
 185         print (entry)