src/openpower/decoder/power_svp64_rm.py

   1 # SPDX-License-Identifier: LGPLv3+
   2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3 # Funded by NLnet http://nlnet.nl
   4 """SVP64 RM (Remap) Record.
   5
   6 https://libre-soc.org/openpower/sv/svp64/
   7
   8 | Field Name  | Field bits | Description                            |
   9 |-------------|------------|----------------------------------------|
  10 | MASKMODE    | `0`        | Execution (predication) Mask Kind      |
  11 | MASK        | `1:3`      | Execution Mask                         |
  12 | ELWIDTH     | `4:5`      | Element Width                          |
  13 | ELWIDTH_SRC | `6:7`      | Element Width for Source               |
  14 | SUBVL       | `8:9`      | Sub-vector length                      |
  15 | EXTRA       | `10:18`    | context-dependent extra                |
  16 | MODE        | `19:23`    | changes Vector behaviour               |
  17 """
  18
  19 from nmigen import Elaboratable, Module, Signal, Const
  20 from openpower.decoder.power_enums import (SVP64RMMode, Function, SVPtype,
  21                                     SVP64PredMode, SVP64sat, SVP64LDSTmode,
  22                                     SVP64BCPredMode, SVP64BCVLSETMode,
  23                                     SVP64BCGate, SVP64BCCTRMode,
  24                                     SVP64width
  25                                     )
  26 from openpower.consts import EXTRA3, SVP64MODE
  27 from openpower.sv.svp64 import SVP64Rec
  28 from nmutil.util import sel
  29
  30 # a list of fields which need to be added to input records in order
  31 # pass on vital information needed by each pipeline.
  32 # make sure to keep these the same as SVP64RMModeDecode, in fact,
  33 # TODO, make SVP64RMModeDecode *use* this as a Record!
  34 sv_input_record_layout = [
  35         ('sv_pred_sz', 1), # predicate source zeroing
  36         ('sv_pred_dz', 1), # predicate dest zeroing
  37         ('sv_saturate', SVP64sat),
  38         ('sv_ldstmode', SVP64LDSTmode),
  39         ('SV_Ptype', SVPtype),
  40         #('sv_RC1', 1),
  41     ]
  42
  43 """RM Mode
  44 there are four Mode variants, two for LD/ST, one for Branch-Conditional,
  45 and one for everything else
  46 https://libre-soc.org/openpower/sv/svp64/
  47 https://libre-soc.org/openpower/sv/ldst/
  48 https://libre-soc.org/openpower/sv/branches/
  49
  50 LD/ST immed:
  51 00      0       zz els  normal mode (with element-stride option)
  52 00      1       zz els  Pack/unpack (with element-stride option)
  53 01      inv     CR-bit  Rc=1: ffirst CR sel
  54 01      inv     els RC1 Rc=0: ffirst z/nonz
  55 10      N       zz els  sat mode: N=0/1 u/s
  56 11      inv     CR-bit  Rc=1: pred-result CR sel
  57 11      inv     els RC1 Rc=0: pred-result z/nonz
  58
  59 LD/ST indexed:
  60 00      0       sz dz   normal mode
  61 00      1       rsvd    reserved
  62 01      inv     CR-bit  Rc=1: ffirst CR sel
  63 01      inv     dz RC1  Rc=0: ffirst z/nonz
  64 10      N       sz dz   sat mode: N=0/1 u/s
  65 11      inv     CR-bit  Rc=1: pred-result CR sel
  66 11      inv     zz RC1  Rc=0: pred-result z/nonz
  67
  68 Arithmetic:
  69 00      0   dz sz       normal mode
  70 00      1   0 RG        scalar reduce mode (mapreduce), SUBVL=1
  71 00      1   1 /         parallel reduce mode (mapreduce), SUBVL=1
  72 00      1   SVM 0       subvector reduce mode, SUBVL>1
  73 00      1   SVM 1       Pack/Unpack mode, SUBVL>1
  74 01      inv CR-bit      Rc=1: ffirst CR sel
  75 01      inv VLi RC1     Rc=0: ffirst z/nonz
  76 10      N   dz sz       sat mode: N=0/1 u/s
  77 11      inv CR-bit      Rc=1: pred-result CR sel
  78 11      inv zz RC1      Rc=0: pred-result z/nonz
  79
  80 Branch Conditional:
  81 note that additional BC modes are in *other bits*, specifically
  82 the element-width fields: SVP64Rec.ewsrc and SVP64Rec.elwidth
  83
  84 elwidth   ewsrc    mode
  85 4   5     6   7    19 20    21  22  23
  86 ALL LRu   /   /     0  0        /       SNZ sz  normal mode
  87 ALL LRu   /   VSb   0  1        VLI     SNZ sz         VLSET mode
  88 ALL LRu   BRc /     1  0        /       SNZ sz  svstep       mode
  89 ALL LRu   BRc VSb   1  1        VLI     SNZ sz  svstep VLSET mode
  90 """
  91
  92
  93 class SVP64RMModeDecode(Elaboratable):
  94     def __init__(self, name=None):
  95         ##### inputs #####
  96         self.rm_in = SVP64Rec(name=name)
  97         self.fn_in = Signal(Function) # LD/ST and Branch is different
  98         self.svp64_vf_in = Signal()  # Vertical-First Mode
  99         self.ptype_in = Signal(SVPtype)
 100         self.rc_in = Signal()
 101         self.ldst_ra_vec = Signal() # set when RA is vec, indicate Index mode
 102         self.ldst_imz_in = Signal() # set when LD/ST immediate is zero
 103
 104         ##### outputs #####
 105
 106         # main mode (normal, reduce, saturate, ffirst, pred-result, branch)
 107         self.mode = Signal(SVP64RMMode)
 108
 109         # Branch Conditional Modes
 110         self.bc_vlset = Signal(SVP64BCVLSETMode) # Branch-Conditional VLSET
 111         self.bc_ctrtest = Signal(SVP64BCCTRMode) # Branch-Conditional CTR-Test
 112         self.bc_pred = Signal(SVP64BCPredMode) # BC predicate mode
 113         self.bc_vsb = Signal()                 # BC VLSET-branch (like BO[1])
 114         self.bc_gate = Signal(SVP64BCGate)     # BC ALL or ANY gate
 115         self.bc_lru  = Signal()                # BC Link Register Update
 116
 117         # predication
 118         self.predmode = Signal(SVP64PredMode)
 119         self.srcpred = Signal(3) # source predicate
 120         self.dstpred = Signal(3) # destination predicate
 121         self.pred_sz = Signal(1) # predicate source zeroing
 122         self.pred_dz = Signal(1) # predicate dest zeroing
 123
 124         # Modes n stuff
 125         self.ew_src = Signal(SVP64width) # source elwidth
 126         self.ew_dst = Signal(SVP64width) # dest elwidth
 127         self.pack = Signal() # pack mode
 128         self.unpack = Signal() # unpack mode
 129         self.saturate = Signal(SVP64sat)
 130         self.RC1 = Signal()
 131         self.cr_sel = Signal(2)  # bit of CR to test (index 0-3)
 132         self.inv = Signal(1)     # and whether it's inverted (like branch BO)
 133         self.map_evm = Signal(1)
 134         self.map_crm = Signal(1)
 135         self.reverse_gear = Signal(1)  # elements to go VL-1..0
 136         self.ldstmode = Signal(SVP64LDSTmode) # LD/ST Mode (strided type)
 137
 138     def elaborate(self, platform):
 139         m = Module()
 140         comb = m.d.comb
 141         mode = self.rm_in.mode
 142
 143         # decode pieces of mode
 144         is_ldst = Signal()
 145         is_bc = Signal()
 146         do_pu = Signal() # whether to decode pack/unpack
 147         comb += is_ldst.eq(self.fn_in == Function.LDST)
 148         comb += is_bc.eq(self.fn_in == Function.BRANCH)
 149         mode2 = sel(m, mode, SVP64MODE.MOD2)
 150
 151         with m.If(is_bc):
 152             # Branch-Conditional is completely different
 153             # Counter-Test Mode.
 154             with m.If(mode[SVP64MODE.BC_CTRTEST]):
 155                 with m.If(self.rm_in.ewsrc[0]):
 156                     comb += self.bc_ctrtest.eq(SVP64BCCTRMode.TEST_INV)
 157                 with m.Else():
 158                     comb += self.bc_ctrtest.eq(SVP64BCCTRMode.TEST)
 159             # VLSET mode
 160             with m.If(mode[SVP64MODE.BC_VLSET]):
 161                 with m.If(mode[SVP64MODE.BC_VLI]):
 162                     comb += self.bc_vlset.eq(SVP64BCVLSETMode.VL_INCL)
 163                 with m.Else():
 164                     comb += self.bc_vlset.eq(SVP64BCVLSETMode.VL_EXCL)
 165             # BC Mode ALL or ANY (Great-Big-AND-gate or Great-Big-OR-gate)
 166             comb += self.bc_gate.eq(self.rm_in.elwidth[0])
 167             # Link-Register Update
 168             comb += self.bc_lru.eq(self.rm_in.elwidth[1])
 169             comb += self.bc_vsb.eq(self.rm_in.ewsrc[1])
 170
 171         with m.Else():
 172             # combined arith / ldst decoding due to similarity
 173             with m.Switch(mode2):
 174                 with m.Case(0): # needs further decoding (LDST no mapreduce)
 175                     with m.If(is_ldst):
 176                         comb += self.mode.eq(SVP64RMMode.NORMAL)
 177                         comb += do_pu.eq(mode[SVP64MODE.LDST_PACK]) # Pack mode
 178                     with m.Elif(mode[SVP64MODE.REDUCE]):
 179                         comb += self.mode.eq(SVP64RMMode.MAPREDUCE)
 180                         # Pack only active if SVM=1 & SUBVL>1 & Mode[4]=1
 181                         with m.If(self.rm_in.subvl != Const(0, 2)): # active
 182                             comb += do_pu.eq(mode[SVP64MODE.ARITH_PACK])
 183                     with m.Else():
 184                         comb += self.mode.eq(SVP64RMMode.NORMAL)
 185                 with m.Case(1):
 186                     comb += self.mode.eq(SVP64RMMode.FFIRST) # fail-first
 187                 with m.Case(2):
 188                     comb += self.mode.eq(SVP64RMMode.SATURATE) # saturate
 189                 with m.Case(3):
 190                     comb += self.mode.eq(SVP64RMMode.PREDRES) # pred result
 191
 192             # extract "reverse gear" for mapreduce mode
 193             with m.If((~is_ldst) &                     # not for LD/ST
 194                         (mode2 == 0) &                 # first 2 bits == 0
 195                         mode[SVP64MODE.REDUCE] &       # bit 2 == 1
 196                        (~mode[SVP64MODE.PARALLEL])):   # not parallel mapreduce
 197                 comb += self.reverse_gear.eq(mode[SVP64MODE.RG]) # finally whew
 198
 199             # extract zeroing
 200             with m.Switch(mode2):
 201                 with m.Case(0): # needs further decoding (LDST no mapreduce)
 202                     with m.If(is_ldst):
 203                         # XXX TODO, work out which of these is most
 204                         # appropriate set both? or just the one?
 205                         # or one if LD, the other if ST?
 206                         comb += self.pred_sz.eq(mode[SVP64MODE.DZ])
 207                         comb += self.pred_dz.eq(mode[SVP64MODE.DZ])
 208                     with m.Elif(mode[SVP64MODE.REDUCE]):
 209                         with m.If(self.rm_in.subvl == Const(0, 2)): # no SUBVL
 210                             comb += self.pred_dz.eq(mode[SVP64MODE.DZ])
 211                     with m.Else():
 212                         comb += self.pred_sz.eq(mode[SVP64MODE.SZ])
 213                         comb += self.pred_dz.eq(mode[SVP64MODE.DZ])
 214                 with m.Case(1, 3):
 215                     with m.If(is_ldst):
 216                         with m.If(~self.ldst_ra_vec):
 217                             comb += self.pred_dz.eq(mode[SVP64MODE.DZ])
 218                     with m.Elif(self.rc_in):
 219                         comb += self.pred_dz.eq(mode[SVP64MODE.DZ])
 220                 with m.Case(2):
 221                     with m.If(is_ldst & ~self.ldst_ra_vec):
 222                         comb += self.pred_dz.eq(mode[SVP64MODE.DZ])
 223                     with m.Else():
 224                         comb += self.pred_sz.eq(mode[SVP64MODE.SZ])
 225                         comb += self.pred_dz.eq(mode[SVP64MODE.DZ])
 226
 227             # extract saturate
 228             with m.Switch(mode2):
 229                 with m.Case(2):
 230                     with m.If(mode[SVP64MODE.N]):
 231                         comb += self.saturate.eq(SVP64sat.UNSIGNED)
 232                     with m.Else():
 233                         comb += self.saturate.eq(SVP64sat.SIGNED)
 234                 with m.Default():
 235                     comb += self.saturate.eq(SVP64sat.NONE)
 236
 237             # extract pack/unpack, actually just ELWIDTH_SRC, so
 238             # do elwidth/elwidth_src at same time
 239             with m.If(do_pu):
 240                 comb += self.pack.eq(self.rm_in.ewsrc[0])
 241                 comb += self.unpack.eq(self.rm_in.ewsrc[1])
 242                 comb += self.ew_src.eq(self.rm_in.elwidth) # make same as elwid
 243             with m.Else():
 244                 comb += self.ew_src.eq(self.rm_in.ewsrc)
 245             comb += self.ew_dst.eq(self.rm_in.elwidth)
 246
 247             # extract els (element strided mode bit)
 248             # see https://libre-soc.org/openpower/sv/ldst/
 249             els = Signal()
 250             with m.If(is_ldst):
 251                 with m.Switch(mode2):
 252                     with m.Case(0):
 253                         comb += els.eq(mode[SVP64MODE.ELS_NORMAL])
 254                     with m.Case(2):
 255                         comb += els.eq(mode[SVP64MODE.ELS_SAT])
 256                     with m.Case(1, 3):
 257                         with m.If(self.rc_in):
 258                             comb += els.eq(mode[SVP64MODE.ELS_FFIRST_PRED])
 259
 260                 # RA is vectorised
 261                 with m.If(self.ldst_ra_vec):
 262                     comb += self.ldstmode.eq(SVP64LDSTmode.INDEXED)
 263                 # not element-strided, therefore unit...
 264                 with m.Elif(~els):
 265                     comb += self.ldstmode.eq(SVP64LDSTmode.UNITSTRIDE)
 266                 # but if the LD/ST immediate is zero, allow cache-inhibited
 267                 # loads from same location, therefore don't do element-striding
 268                 with m.Elif(~self.ldst_imz_in):
 269                     comb += self.ldstmode.eq(SVP64LDSTmode.ELSTRIDE)
 270
 271         # extract src/dest predicate.  use EXTRA3.MASK because EXTRA2.MASK
 272         # is in exactly the same bits
 273         srcmask = sel(m, self.rm_in.extra, EXTRA3.MASK)
 274         dstmask = self.rm_in.mask
 275         with m.If(self.ptype_in == SVPtype.P2):
 276             comb += self.srcpred.eq(srcmask)
 277         with m.Else():
 278             comb += self.srcpred.eq(dstmask)
 279         comb += self.dstpred.eq(dstmask)
 280
 281         # identify predicate mode
 282         with m.If(self.rm_in.mmode == 1):
 283             comb += self.predmode.eq(SVP64PredMode.CR) # CR Predicate
 284         with m.Elif((self.srcpred == 0) & (self.dstpred == 0)):
 285             comb += self.predmode.eq(SVP64PredMode.ALWAYS) # No predicate
 286         with m.Else():
 287             comb += self.predmode.eq(SVP64PredMode.INT) # non-zero src: INT
 288
 289         # TODO: detect zeroing mode, saturation mode, a few more.
 290
 291         return m
 292