src/openpower/decoder/power_svp64_rm.py

   1 # SPDX-License-Identifier: LGPLv3+
   2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3 # Funded by NLnet http://nlnet.nl
   4 """SVP64 RM (Remap) Record.
   5
   6 https://libre-soc.org/openpower/sv/svp64/
   7
   8 | Field Name  | Field bits | Description                            |
   9 |-------------|------------|----------------------------------------|
  10 | MASKMODE    | `0`        | Execution (predication) Mask Kind      |
  11 | MASK        | `1:3`      | Execution Mask                         |
  12 | ELWIDTH     | `4:5`      | Element Width                          |
  13 | ELWIDTH_SRC | `6:7`      | Element Width for Source               |
  14 | SUBVL       | `8:9`      | Sub-vector length                      |
  15 | EXTRA       | `10:18`    | context-dependent extra                |
  16 | MODE        | `19:23`    | changes Vector behaviour               |
  17 """
  18
  19 from nmigen import Elaboratable, Module, Signal, Const
  20 from openpower.decoder.power_enums import (SVP64RMMode, Function, SVPtype,
  21                                     SVP64PredMode, SVP64sat, SVP64LDSTmode,
  22                                     SVP64BCPredMode, SVP64BCVLSETMode,
  23                                     SVP64BCGate, SVP64BCCTRMode,
  24                                     SVP64width
  25                                     )
  26 from openpower.consts import EXTRA3, SVP64MODE
  27 from openpower.sv.svp64 import SVP64Rec
  28 from nmutil.util import sel
  29
  30 # a list of fields which need to be added to input records in order
  31 # pass on vital information needed by each pipeline.
  32 # make sure to keep these the same as SVP64RMModeDecode, in fact,
  33 # TODO, make SVP64RMModeDecode *use* this as a Record!
  34 sv_input_record_layout = [
  35         ('sv_pred_sz', 1), # predicate source zeroing
  36         ('sv_pred_dz', 1), # predicate dest zeroing
  37         ('sv_saturate', SVP64sat),
  38         ('sv_ldstmode', SVP64LDSTmode),
  39         ('SV_Ptype', SVPtype),
  40         #('sv_RC1', 1),
  41     ]
  42
  43 """RM Mode
  44 there are four Mode variants, two for LD/ST, one for Branch-Conditional,
  45 and one for everything else
  46 https://libre-soc.org/openpower/sv/svp64/
  47 https://libre-soc.org/openpower/sv/ldst/
  48 https://libre-soc.org/openpower/sv/branches/
  49
  50 LD/ST immed:
  51 00      0       zz els  normal mode (with element-stride option)
  52 00      1       zz els  Pack/unpack (with element-stride option)
  53 01      inv     CR-bit  Rc=1: ffirst CR sel
  54 01      inv     els RC1 Rc=0: ffirst z/nonz
  55 10      N       zz els  sat mode: N=0/1 u/s
  56 11      inv     CR-bit  Rc=1: pred-result CR sel
  57 11      inv     els RC1 Rc=0: pred-result z/nonz
  58
  59 LD/ST indexed:
  60 00      0       sz dz   normal mode
  61 00      1       rsvd    reserved
  62 01      inv     CR-bit  Rc=1: ffirst CR sel
  63 01      inv     dz RC1  Rc=0: ffirst z/nonz
  64 10      N       sz dz   sat mode: N=0/1 u/s
  65 11      inv     CR-bit  Rc=1: pred-result CR sel
  66 11      inv     zz RC1  Rc=0: pred-result z/nonz
  67
  68 Arithmetic:
  69 | 0-1 |  2  |  3   4  |  description              |
  70 | --- | --- |---------|-------------------------- |
  71 | 00  |   0 |  dz  sz | simple mode                      |
  72 | 00  |   1 | 0  RG   | scalar reduce mode (mapreduce), SUBVL=1 |
  73 | 00  |   1 | SVM 0   | subvector reduce mode, SUBVL>1   |
  74 | 00  |   1 | SVM 1   | Pack/Unpack mode, SUBVL>1   |
  75 | 01  | inv | CR-bit  | Rc=1: ffirst CR sel              |
  76 | 01  | inv | VLi RC1 |  Rc=0: ffirst z/nonz |
  77 | 10  |   N | dz   sz |  sat mode: N=0/1 u/s, SUBVL=1 |
  78 | 10  |   N | zz   0  |  sat mode: N=0/1 u/s, SUBVL>1 |
  79 | 10  |   N | zz   1  |  Pack/Unpack sat mode: N=0/1 u/s, SUBVL>1 |
  80 | 11  | inv | CR-bit  |  Rc=1: pred-result CR sel |
  81 | 11  | inv | zz  RC1 |  Rc=0: pred-result z/nonz |
  82
  83 Branch Conditional:
  84 note that additional BC modes are in *other bits*, specifically
  85 the element-width fields: SVP64Rec.ewsrc and SVP64Rec.elwidth
  86
  87 elwidth   ewsrc    mode
  88 4   5     6   7    19 20    21  22  23
  89 ALL LRu   /   /     0  0        /       SNZ sz  normal mode
  90 ALL LRu   /   VSb   0  1        VLI     SNZ sz         VLSET mode
  91 ALL LRu   BRc /     1  0        /       SNZ sz  svstep       mode
  92 ALL LRu   BRc VSb   1  1        VLI     SNZ sz  svstep VLSET mode
  93 """
  94
  95
  96 class SVP64RMModeDecode(Elaboratable):
  97     def __init__(self, name=None):
  98         ##### inputs #####
  99         self.rm_in = SVP64Rec(name=name)
 100         self.fn_in = Signal(Function) # LD/ST and Branch is different
 101         self.svp64_vf_in = Signal()  # Vertical-First Mode
 102         self.ptype_in = Signal(SVPtype)
 103         self.rc_in = Signal()
 104         self.ldst_ra_vec = Signal() # set when RA is vec, indicate Index mode
 105         self.ldst_imz_in = Signal() # set when LD/ST immediate is zero
 106
 107         ##### outputs #####
 108
 109         # main mode (normal, reduce, saturate, ffirst, pred-result, branch)
 110         self.mode = Signal(SVP64RMMode)
 111
 112         # Branch Conditional Modes
 113         self.bc_vlset = Signal(SVP64BCVLSETMode) # Branch-Conditional VLSET
 114         self.bc_ctrtest = Signal(SVP64BCCTRMode) # Branch-Conditional CTR-Test
 115         self.bc_pred = Signal(SVP64BCPredMode) # BC predicate mode
 116         self.bc_vsb = Signal()                 # BC VLSET-branch (like BO[1])
 117         self.bc_gate = Signal(SVP64BCGate)     # BC ALL or ANY gate
 118         self.bc_lru  = Signal()                # BC Link Register Update
 119
 120         # predication
 121         self.predmode = Signal(SVP64PredMode)
 122         self.srcpred = Signal(3) # source predicate
 123         self.dstpred = Signal(3) # destination predicate
 124         self.pred_sz = Signal(1) # predicate source zeroing
 125         self.pred_dz = Signal(1) # predicate dest zeroing
 126
 127         # Modes n stuff
 128         self.ew_src = Signal(SVP64width) # source elwidth
 129         self.ew_dst = Signal(SVP64width) # dest elwidth
 130         self.pack = Signal() # pack mode
 131         self.unpack = Signal() # unpack mode
 132         self.saturate = Signal(SVP64sat)
 133         self.RC1 = Signal()
 134         self.cr_sel = Signal(2)  # bit of CR to test (index 0-3)
 135         self.inv = Signal(1)     # and whether it's inverted (like branch BO)
 136         self.map_evm = Signal(1)
 137         self.map_crm = Signal(1)
 138         self.reverse_gear = Signal(1)  # elements to go VL-1..0
 139         self.ldstmode = Signal(SVP64LDSTmode) # LD/ST Mode (strided type)
 140
 141     def elaborate(self, platform):
 142         m = Module()
 143         comb = m.d.comb
 144         mode = self.rm_in.mode
 145
 146         # decode pieces of mode
 147         is_ldst = Signal()
 148         is_bc = Signal()
 149         do_pu = Signal() # whether to decode pack/unpack
 150         comb += is_ldst.eq(self.fn_in == Function.LDST)
 151         comb += is_bc.eq(self.fn_in == Function.BRANCH)
 152         mode2 = sel(m, mode, SVP64MODE.MOD2)
 153
 154         with m.If(is_bc):
 155             # Branch-Conditional is completely different
 156             # Counter-Test Mode.
 157             with m.If(mode[SVP64MODE.BC_CTRTEST]):
 158                 with m.If(self.rm_in.ewsrc[0]):
 159                     comb += self.bc_ctrtest.eq(SVP64BCCTRMode.TEST_INV)
 160                 with m.Else():
 161                     comb += self.bc_ctrtest.eq(SVP64BCCTRMode.TEST)
 162             # VLSET mode
 163             with m.If(mode[SVP64MODE.BC_VLSET]):
 164                 with m.If(mode[SVP64MODE.BC_VLI]):
 165                     comb += self.bc_vlset.eq(SVP64BCVLSETMode.VL_INCL)
 166                 with m.Else():
 167                     comb += self.bc_vlset.eq(SVP64BCVLSETMode.VL_EXCL)
 168             # BC Mode ALL or ANY (Great-Big-AND-gate or Great-Big-OR-gate)
 169             comb += self.bc_gate.eq(self.rm_in.elwidth[0])
 170             # Link-Register Update
 171             comb += self.bc_lru.eq(self.rm_in.elwidth[1])
 172             comb += self.bc_vsb.eq(self.rm_in.ewsrc[1])
 173
 174         with m.Else():
 175             # combined arith / ldst decoding due to similarity
 176             with m.Switch(mode2):
 177                 with m.Case(0): # needs further decoding (LDST no mapreduce)
 178                     with m.If(is_ldst):
 179                         comb += self.mode.eq(SVP64RMMode.NORMAL)
 180                         comb += do_pu.eq(mode[SVP64MODE.LDST_PACK]) # Pack mode
 181                     with m.Elif(mode[SVP64MODE.REDUCE]):
 182                         comb += self.mode.eq(SVP64RMMode.MAPREDUCE)
 183                         # Pack only active if SVM=1 & SUBVL>1 & Mode[4]=1
 184                         with m.If(self.rm_in.subvl != Const(0, 2)): # active
 185                             comb += do_pu.eq(mode[SVP64MODE.ARITH_PACK])
 186                     with m.Else():
 187                         comb += self.mode.eq(SVP64RMMode.NORMAL)
 188                 with m.Case(1):
 189                     comb += self.mode.eq(SVP64RMMode.FFIRST) # fail-first
 190                 with m.Case(2):
 191                     comb += self.mode.eq(SVP64RMMode.SATURATE) # saturate
 192                 with m.Case(3):
 193                     comb += self.mode.eq(SVP64RMMode.PREDRES) # pred result
 194
 195             # extract "reverse gear" for mapreduce mode
 196             with m.If((~is_ldst) &                     # not for LD/ST
 197                         (mode2 == 0) &                 # first 2 bits == 0
 198                         mode[SVP64MODE.REDUCE] &       # bit 2 == 1
 199                        (~mode[SVP64MODE.MOD3])):       # bit 3 == 0
 200                 comb += self.reverse_gear.eq(mode[SVP64MODE.RG]) # finally whew
 201
 202             # extract zeroing
 203             with m.Switch(mode2):
 204                 with m.Case(0): # needs further decoding (LDST no mapreduce)
 205                     with m.If(is_ldst):
 206                         # XXX TODO, work out which of these is most
 207                         # appropriate set both? or just the one?
 208                         # or one if LD, the other if ST?
 209                         comb += self.pred_sz.eq(mode[SVP64MODE.DZ])
 210                         comb += self.pred_dz.eq(mode[SVP64MODE.DZ])
 211                     with m.Elif(mode[SVP64MODE.REDUCE]):
 212                         with m.If(self.rm_in.subvl == Const(0, 2)): # no SUBVL
 213                             comb += self.pred_dz.eq(mode[SVP64MODE.DZ])
 214                     with m.Else():
 215                         comb += self.pred_sz.eq(mode[SVP64MODE.SZ])
 216                         comb += self.pred_dz.eq(mode[SVP64MODE.DZ])
 217                 with m.Case(1, 3):
 218                     with m.If(is_ldst):
 219                         with m.If(~self.ldst_ra_vec):
 220                             comb += self.pred_dz.eq(mode[SVP64MODE.DZ])
 221                     with m.Elif(self.rc_in):
 222                         comb += self.pred_dz.eq(mode[SVP64MODE.DZ])
 223                 with m.Case(2):
 224                     with m.If(is_ldst & ~self.ldst_ra_vec):
 225                         comb += self.pred_dz.eq(mode[SVP64MODE.DZ])
 226                     with m.Else():
 227                         comb += self.pred_sz.eq(mode[SVP64MODE.SZ])
 228                         comb += self.pred_dz.eq(mode[SVP64MODE.DZ])
 229
 230             # extract saturate
 231             with m.Switch(mode2):
 232                 with m.Case(2):
 233                     with m.If(mode[SVP64MODE.N]):
 234                         comb += self.saturate.eq(SVP64sat.UNSIGNED)
 235                     with m.Else():
 236                         comb += self.saturate.eq(SVP64sat.SIGNED)
 237                 with m.Default():
 238                     comb += self.saturate.eq(SVP64sat.NONE)
 239
 240             # extract pack/unpack, actually just ELWIDTH_SRC, so
 241             # do elwidth/elwidth_src at same time
 242             with m.If(do_pu):
 243                 comb += self.pack.eq(self.rm_in.ewsrc[0])
 244                 comb += self.unpack.eq(self.rm_in.ewsrc[1])
 245                 comb += self.ew_src.eq(self.rm_in.elwidth) # make same as elwid
 246             with m.Else():
 247                 comb += self.ew_src.eq(self.rm_in.ewsrc)
 248             comb += self.ew_dst.eq(self.rm_in.elwidth)
 249
 250             # extract els (element strided mode bit)
 251             # see https://libre-soc.org/openpower/sv/ldst/
 252             els = Signal()
 253             with m.If(is_ldst):
 254                 with m.Switch(mode2):
 255                     with m.Case(0):
 256                         comb += els.eq(mode[SVP64MODE.ELS_NORMAL])
 257                     with m.Case(2):
 258                         comb += els.eq(mode[SVP64MODE.ELS_SAT])
 259                     with m.Case(1, 3):
 260                         with m.If(self.rc_in):
 261                             comb += els.eq(mode[SVP64MODE.ELS_FFIRST_PRED])
 262
 263                 # RA is vectorised
 264                 with m.If(self.ldst_ra_vec):
 265                     comb += self.ldstmode.eq(SVP64LDSTmode.INDEXED)
 266                 # not element-strided, therefore unit...
 267                 with m.Elif(~els):
 268                     comb += self.ldstmode.eq(SVP64LDSTmode.UNITSTRIDE)
 269                 # but if the LD/ST immediate is zero, allow cache-inhibited
 270                 # loads from same location, therefore don't do element-striding
 271                 with m.Elif(~self.ldst_imz_in):
 272                     comb += self.ldstmode.eq(SVP64LDSTmode.ELSTRIDE)
 273
 274         # extract src/dest predicate.  use EXTRA3.MASK because EXTRA2.MASK
 275         # is in exactly the same bits
 276         srcmask = sel(m, self.rm_in.extra, EXTRA3.MASK)
 277         dstmask = self.rm_in.mask
 278         with m.If(self.ptype_in == SVPtype.P2):
 279             comb += self.srcpred.eq(srcmask)
 280         with m.Else():
 281             comb += self.srcpred.eq(dstmask)
 282         comb += self.dstpred.eq(dstmask)
 283
 284         # identify predicate mode
 285         with m.If(self.rm_in.mmode == 1):
 286             comb += self.predmode.eq(SVP64PredMode.CR) # CR Predicate
 287         with m.Elif((self.srcpred == 0) & (self.dstpred == 0)):
 288             comb += self.predmode.eq(SVP64PredMode.ALWAYS) # No predicate
 289         with m.Else():
 290             comb += self.predmode.eq(SVP64PredMode.INT) # non-zero src: INT
 291
 292         # TODO: detect zeroing mode, saturation mode, a few more.
 293
 294         return m
 295