src/openpower/decoder/power_svp64_rm.py

   1 # SPDX-License-Identifier: LGPLv3+
   2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3 # Funded by NLnet http://nlnet.nl
   4 """SVP64 RM (Remap) Record.
   5
   6 https://libre-soc.org/openpower/sv/svp64/
   7
   8 | Field Name  | Field bits | Description                            |
   9 |-------------|------------|----------------------------------------|
  10 | MASKMODE    | `0`        | Execution (predication) Mask Kind      |
  11 | MASK        | `1:3`      | Execution Mask                         |
  12 | ELWIDTH     | `4:5`      | Element Width                          |
  13 | ELWIDTH_SRC | `6:7`      | Element Width for Source               |
  14 | SUBVL       | `8:9`      | Sub-vector length                      |
  15 | EXTRA       | `10:18`    | context-dependent extra                |
  16 | MODE        | `19:23`    | changes Vector behaviour               |
  17 """
  18
  19 from nmigen import Elaboratable, Module, Signal, Const
  20 from openpower.decoder.power_enums import (SVP64RMMode, Function, SVPtype,
  21                                     SVMode,
  22                                     SVP64PredMode, SVP64sat, SVP64LDSTmode,
  23                                     SVP64BCPredMode, SVP64BCVLSETMode,
  24                                     SVP64BCGate, SVP64BCCTRMode,
  25                                     SVP64width
  26                                     )
  27 from openpower.consts import EXTRA3, SVP64MODE
  28 from openpower.sv.svp64 import SVP64Rec
  29 from nmutil.util import sel
  30
  31 # a list of fields which need to be added to input records in order
  32 # pass on vital information needed by each pipeline.
  33 # make sure to keep these the same as SVP64RMModeDecode, in fact,
  34 # TODO, make SVP64RMModeDecode *use* this as a Record!
  35 sv_input_record_layout = [
  36         ('sv_pred_sz', 1), # predicate source zeroing
  37         ('sv_pred_dz', 1), # predicate dest zeroing
  38         ('sv_saturate', SVP64sat),
  39         ('sv_ldstmode', SVP64LDSTmode),
  40         ('SV_Ptype', SVPtype),
  41         ('SV_mode', SVMode),
  42         #('sv_RC1', 1),
  43     ]
  44
  45 """RM Mode
  46 there are four Mode variants, two for LD/ST, one for Branch-Conditional,
  47 and one for everything else
  48 https://libre-soc.org/openpower/sv/svp64/
  49 https://libre-soc.org/openpower/sv/ldst/
  50 https://libre-soc.org/openpower/sv/branches/
  51
  52 LD/ST immed:
  53 00      0       zz els  normal mode (with element-stride option)
  54 01      inv     CR-bit  Rc=1: ffirst CR sel
  55 01      inv     els RC1 Rc=0: ffirst z/nonz
  56 10      N       zz els  sat mode: N=0/1 u/s
  57 11      inv     CR-bit  Rc=1: pred-result CR sel
  58 11      inv     els RC1 Rc=0: pred-result z/nonz
  59
  60 LD/ST indexed:
  61 00      0       sz dz   normal mode
  62 00      1       rsvd    reserved
  63 01      inv     CR-bit  Rc=1: ffirst CR sel
  64 01      inv     dz RC1  Rc=0: ffirst z/nonz
  65 10      N       sz dz   sat mode: N=0/1 u/s
  66 11      inv     CR-bit  Rc=1: pred-result CR sel
  67 11      inv     zz RC1  Rc=0: pred-result z/nonz
  68
  69 Arithmetic:
  70 | 0-1 |  2  |  3   4  |  description              |
  71 | --- | --- |---------|-------------------------- |
  72 | 00  |   0 |  dz  sz | simple mode                      |
  73 | 00  |   1 | 0  RG   | scalar reduce mode (mapreduce), SUBVL=1 |
  74 | 00  |   1 | SVM 0   | subvector reduce mode, SUBVL>1   |
  75 | 00  |   1 | /   1   | reserved |
  76 | 01  | inv | CR-bit  | Rc=1: ffirst CR sel              |
  77 | 01  | inv | VLi RC1 |  Rc=0: ffirst z/nonz |
  78 | 10  |   N | dz   sz |  sat mode: N=0/1 u/s, SUBVL=1 |
  79 | 10  |   N | zz   0  |  sat mode: N=0/1 u/s, SUBVL>1 |
  80 | 10  |   N | /    1  |  reserved |
  81 | 11  | inv | CR-bit  |  Rc=1: pred-result CR sel |
  82 | 11  | inv | zz  RC1 |  Rc=0: pred-result z/nonz |
  83
  84 Branch Conditional:
  85 note that additional BC modes are in *other bits*, specifically
  86 the element-width fields: SVP64Rec.ewsrc and SVP64Rec.elwidth
  87
  88 elwidth   ewsrc    mode
  89 4   5     6   7    19 20    21  22  23
  90 ALL LRu   /   /     0  0        /       SNZ sz  normal mode
  91 ALL LRu   /   VSb   0  1        VLI     SNZ sz         VLSET mode
  92 ALL LRu   BRc /     1  0        /       SNZ sz  svstep       mode
  93 ALL LRu   BRc VSb   1  1        VLI     SNZ sz  svstep VLSET mode
  94 """
  95
  96
  97 class SVP64RMModeDecode(Elaboratable):
  98     def __init__(self, name=None):
  99         ##### inputs #####
 100         self.rm_in = SVP64Rec(name=name)
 101         self.fn_in = Signal(Function) # LD/ST and Branch is different
 102         self.sv_mode = Signal(SVMode) # BRANCH/LDST_IMM/CROP etc.
 103         self.svp64_vf_in = Signal()  # Vertical-First Mode
 104         self.ptype_in = Signal(SVPtype)
 105         self.rc_in = Signal()
 106         self.cr_5bit_in = Signal()  # if CR field was 5-bit
 107         self.cr_2bit_in = Signal()  # bottom 2 bits of CR field
 108         self.ldst_ra_vec = Signal() # set when RA is vec, indicate Index mode
 109         self.ldst_imz_in = Signal() # set when LD/ST immediate is zero
 110
 111         ##### outputs #####
 112
 113         # main mode (normal, reduce, saturate, ffirst, pred-result, branch)
 114         self.mode = Signal(SVP64RMMode)
 115
 116         # Branch Conditional Modes
 117         self.bc_vlset = Signal(SVP64BCVLSETMode) # Branch-Conditional VLSET
 118         self.bc_ctrtest = Signal(SVP64BCCTRMode) # Branch-Conditional CTR-Test
 119         self.bc_pred = Signal(SVP64BCPredMode) # BC predicate mode
 120         self.bc_vsb = Signal()                 # BC VLSET-branch (like BO[1])
 121         self.bc_gate = Signal(SVP64BCGate)     # BC ALL or ANY gate
 122         self.bc_lru  = Signal()                # BC Link Register Update
 123
 124         # predication
 125         self.predmode = Signal(SVP64PredMode)
 126         self.srcpred = Signal(3) # source predicate
 127         self.dstpred = Signal(3) # destination predicate
 128         self.pred_sz = Signal(1) # predicate source zeroing
 129         self.pred_dz = Signal(1) # predicate dest zeroing
 130
 131         # Modes n stuff
 132         self.ew_src = Signal(SVP64width) # source elwidth
 133         self.ew_dst = Signal(SVP64width) # dest elwidth
 134         self.subvl= Signal(2) # subvl
 135         self.saturate = Signal(SVP64sat)
 136         self.RC1 = Signal()
 137         self.vli = Signal()
 138         self.cr_sel = Signal(2)  # bit of CR to test (index 0-3)
 139         self.inv = Signal(1)     # and whether it's inverted (like branch BO)
 140         self.map_evm = Signal(1)
 141         self.map_crm = Signal(1)
 142         self.reverse_gear = Signal(1)  # elements to go VL-1..0
 143         self.ldstmode = Signal(SVP64LDSTmode) # LD/ST Mode (strided type)
 144
 145     def elaborate(self, platform):
 146         m = Module()
 147         comb = m.d.comb
 148         mode = self.rm_in.mode
 149
 150         # decode pieces of mode
 151         is_ldst = Signal()
 152         is_bc = Signal()
 153         is_cr = Signal()
 154         comb += is_ldst.eq(self.fn_in == Function.LDST)
 155         comb += is_bc.eq(self.fn_in == Function.BRANCH) # XXX TODO use SV Mode
 156         comb += is_cr.eq(self.sv_mode == SVMode.CROP.value)
 157         mode2 = sel(m, mode, SVP64MODE.MOD2)
 158         cr = sel(m, mode, SVP64MODE.CR)
 159
 160         with m.If(is_bc):
 161             # Branch-Conditional is completely different
 162             # Counter-Test Mode.
 163             with m.If(mode[SVP64MODE.BC_CTRTEST]):
 164                 with m.If(self.rm_in.ewsrc[1]):
 165                     comb += self.bc_ctrtest.eq(SVP64BCCTRMode.TEST_INV)
 166                 with m.Else():
 167                     comb += self.bc_ctrtest.eq(SVP64BCCTRMode.TEST)
 168
 169             # BC Mode ALL or ANY (Great-Big-AND-gate or Great-Big-OR-gate)
 170             comb += self.bc_gate.eq(self.rm_in.elwidth[1])
 171             # Link-Register Update
 172             comb += self.bc_lru.eq(self.rm_in.elwidth[0])
 173             comb += self.bc_vsb.eq(self.rm_in.ewsrc[0])
 174
 175         with m.Elif(is_cr):
 176             with m.Switch(mode2):
 177                 with m.Case(0, 1): # needs further decoding (LDST no mapreduce)
 178                     with m.If(mode[SVP64MODE.REDUCE]):
 179                         comb += self.mode.eq(SVP64RMMode.MAPREDUCE)
 180                     with m.Else():
 181                         comb += self.mode.eq(SVP64RMMode.NORMAL)
 182                 with m.Case(2,3):
 183                     comb += self.mode.eq(SVP64RMMode.FFIRST) # fail-first
 184
 185             # extract failfirst
 186             with m.If(self.mode == SVP64RMMode.FFIRST): # fail-first
 187                 comb += self.inv.eq(mode[SVP64MODE.INV])
 188                 comb += self.vli.eq(mode[SVP64MODE.BC_VLSET])
 189                 with m.If(self.cr_5bit_in):
 190                     comb += self.cr_sel.eq(0b10) # EQ bit index is implicit
 191                 with m.Else():
 192                     comb += self.cr_sel.eq(cr)
 193
 194         with m.Else():
 195             # combined arith / ldst decoding due to similarity
 196             with m.Switch(mode2):
 197                 with m.Case(0): # needs further decoding (LDST no mapreduce)
 198                     with m.If(is_ldst):
 199                         comb += self.mode.eq(SVP64RMMode.NORMAL)
 200                     with m.Elif(mode[SVP64MODE.REDUCE]):
 201                         comb += self.mode.eq(SVP64RMMode.MAPREDUCE)
 202                     with m.Else():
 203                         comb += self.mode.eq(SVP64RMMode.NORMAL)
 204                 with m.Case(1):
 205                     comb += self.mode.eq(SVP64RMMode.FFIRST) # fail-first
 206                 with m.Case(2):
 207                     comb += self.mode.eq(SVP64RMMode.SATURATE) # saturate
 208                 with m.Case(3):
 209                     comb += self.mode.eq(SVP64RMMode.PREDRES) # pred result
 210
 211             # extract "reverse gear" for mapreduce mode
 212             with m.If((~is_ldst) &                     # not for LD/ST
 213                         (mode2 == 0) &                 # first 2 bits == 0
 214                         mode[SVP64MODE.REDUCE] &       # bit 2 == 1
 215                        (~mode[SVP64MODE.MOD3])):       # bit 3 == 0
 216                 comb += self.reverse_gear.eq(mode[SVP64MODE.RG]) # finally whew
 217
 218             # extract zeroing
 219             with m.Switch(mode2):
 220                 with m.Case(0): # needs further decoding (LDST no mapreduce)
 221                     with m.If(is_ldst):
 222                         # XXX TODO, work out which of these is most
 223                         # appropriate set both? or just the one?
 224                         # or one if LD, the other if ST?
 225                         comb += self.pred_sz.eq(mode[SVP64MODE.DZ])
 226                         comb += self.pred_dz.eq(mode[SVP64MODE.DZ])
 227                     with m.Elif(mode[SVP64MODE.REDUCE]):
 228                         with m.If(self.rm_in.subvl == Const(0, 2)): # no SUBVL
 229                             comb += self.pred_dz.eq(mode[SVP64MODE.DZ])
 230                     with m.Else():
 231                         comb += self.pred_sz.eq(mode[SVP64MODE.SZ])
 232                         comb += self.pred_dz.eq(mode[SVP64MODE.DZ])
 233                 with m.Case(1, 3):
 234                     with m.If(is_ldst):
 235                         with m.If(~self.ldst_ra_vec):
 236                             comb += self.pred_dz.eq(mode[SVP64MODE.DZ])
 237                     with m.Elif(self.rc_in):
 238                         comb += self.pred_dz.eq(mode[SVP64MODE.DZ])
 239                 with m.Case(2):
 240                     with m.If(is_ldst & ~self.ldst_ra_vec):
 241                         comb += self.pred_dz.eq(mode[SVP64MODE.DZ])
 242                     with m.Else():
 243                         comb += self.pred_sz.eq(mode[SVP64MODE.SZ])
 244                         comb += self.pred_dz.eq(mode[SVP64MODE.DZ])
 245
 246             # extract failfirst
 247             with m.If(self.mode == SVP64RMMode.FFIRST): # fail-first
 248                 comb += self.inv.eq(mode[SVP64MODE.INV])
 249                 with m.If(self.rc_in):
 250                     comb += self.cr_sel.eq(cr)
 251                 with m.Else():
 252                     # only when Rc=0
 253                     comb += self.RC1.eq(mode[SVP64MODE.RC1])
 254                     comb += self.vli.eq(mode[SVP64MODE.VLI])
 255                     comb += self.cr_sel.eq(0b10) # EQ bit index is implicit
 256
 257             # extract saturate
 258             with m.Switch(mode2):
 259                 with m.Case(2):
 260                     with m.If(mode[SVP64MODE.N]):
 261                         comb += self.saturate.eq(SVP64sat.UNSIGNED)
 262                     with m.Else():
 263                         comb += self.saturate.eq(SVP64sat.SIGNED)
 264                 with m.Default():
 265                     comb += self.saturate.eq(SVP64sat.NONE)
 266
 267             # do elwidth/elwidth_src extract
 268             comb += self.ew_src.eq(self.rm_in.ewsrc)
 269             comb += self.ew_dst.eq(self.rm_in.elwidth)
 270             comb += self.subvl.eq(self.rm_in.subvl)
 271
 272             # extract els (element strided mode bit)
 273             # see https://libre-soc.org/openpower/sv/ldst/
 274             els = Signal()
 275             with m.If(is_ldst):
 276                 with m.Switch(mode2):
 277                     with m.Case(0):
 278                         comb += els.eq(mode[SVP64MODE.ELS_NORMAL])
 279                     with m.Case(2):
 280                         comb += els.eq(mode[SVP64MODE.ELS_SAT])
 281                     with m.Case(1, 3):
 282                         with m.If(self.rc_in):
 283                             comb += els.eq(mode[SVP64MODE.ELS_FFIRST_PRED])
 284
 285                 # RA is vectorised
 286                 with m.If(self.ldst_ra_vec):
 287                     comb += self.ldstmode.eq(SVP64LDSTmode.INDEXED)
 288                 # not element-strided, therefore unit...
 289                 with m.Elif(~els):
 290                     comb += self.ldstmode.eq(SVP64LDSTmode.UNITSTRIDE)
 291                 # but if the LD/ST immediate is zero, allow cache-inhibited
 292                 # loads from same location, therefore don't do element-striding
 293                 with m.Elif(~self.ldst_imz_in):
 294                     comb += self.ldstmode.eq(SVP64LDSTmode.ELSTRIDE)
 295
 296         # extract src/dest predicate.  use EXTRA3.MASK because EXTRA2.MASK
 297         # is in exactly the same bits
 298         srcmask = sel(m, self.rm_in.extra, EXTRA3.MASK)
 299         dstmask = self.rm_in.mask
 300         with m.If(self.ptype_in == SVPtype.P2):
 301             comb += self.srcpred.eq(srcmask)
 302         with m.Else():
 303             comb += self.srcpred.eq(dstmask)
 304         comb += self.dstpred.eq(dstmask)
 305
 306         # identify predicate mode
 307         with m.If(self.rm_in.mmode == 1):
 308             comb += self.predmode.eq(SVP64PredMode.CR) # CR Predicate
 309         with m.Elif((self.srcpred == 0) & (self.dstpred == 0)):
 310             comb += self.predmode.eq(SVP64PredMode.ALWAYS) # No predicate
 311         with m.Else():
 312             comb += self.predmode.eq(SVP64PredMode.INT) # non-zero src: INT
 313
 314         # TODO: detect zeroing mode, saturation mode, a few more.
 315
 316         return m
 317