1 from nmigen
import Module
, Signal
3 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
4 # Also, check out the cxxsim nmigen branch, and latest yosys from git
5 from nmutil
.sim_tmp_alternative
import Simulator
, Delay
, Settle
6 # to be renamed for a c-based module.
7 from openpower
.decoder
.test
.pysim
import PySimEngine
9 from nmutil
.formaltest
import FHDLTestCase
10 from nmigen
.cli
import rtlil
14 from openpower
.decoder
.power_decoder2
import PowerDecode2
15 from openpower
.decoder
.power_enums
import (Function
, MicrOp
,
16 In1Sel
, In2Sel
, In3Sel
,
18 OutSel
, LdstLen
, CryIn
,
20 get_signal_name
, get_csv
)
21 from openpower
.decoder
.decode2execute1
import IssuerDecode2ToOperand
22 from openpower
.decoder
.decode2execute1
import Data
23 from openpower
.state
import CoreState
26 class Decoder2TestCase(FHDLTestCase
):
28 def run_tst(self
, raw_opcode
):
33 comb
+= bigendian
.eq(0)
35 # copied this from issuer.py
36 cur_state
= CoreState("cur") # current state (MSR/PC/SVSTATE)
37 m
.submodules
.dut
= dut
= PowerDecode2(None, state
=cur_state
,
38 opkls
=IssuerDecode2ToOperand
,
42 comb
+= [dut
.dec
.raw_opcode_in
.eq(opcode
),
43 dut
.dec
.bigendian
.eq(bigendian
),
47 # Use the below line instead to run the work-in-progress C simulator.
48 sim
= Simulator(m
, engine
=PySimEngine
)
49 # for test purposes repeat the simulation to get performance stats
53 tic
= time
.perf_counter()
54 for i
in range(repeat_times
):
55 yield opcode
.eq(raw_opcode
)
59 #self.assertEqual(expected, result, msg)
60 ticend
= time
.perf_counter()
61 print ("time taken:", ticend
- tic
)
63 sim
.add_process(process
)
64 prefix
= "test_power_decoder2"
65 with sim
.write_vcd("%s.vcd" % prefix
, "%s.gtkw" % prefix
, traces
=[
71 self
.run_tst(0xe8c20000) # LD operation
73 if __name__
== "__main__":