src/openpower/simulator/test_div_sim.py

   1 import unittest
   2 from nmutil.formaltest import FHDLTestCase
   3 from openpower.simulator.program import Program
   4 from openpower.simulator.qemu import run_program
   5 from openpower.decoder.isa.all import ISA
   6 from openpower.test.common import TestCase
   7 from openpower.simulator.test_sim import DecoderBase
   8 from openpower.endian import bigendian
   9
  10
  11
  12 class DivTestCases(FHDLTestCase):
  13     test_data = []
  14
  15     def __init__(self, name="div"):
  16         super().__init__(name)
  17         self.test_name = name
  18
  19     def test_0_divw(self):
  20         lst = ["addi 1, 0, 0x5678",
  21                "addi 2, 0, 0x1234",
  22                "divw  3, 1, 2",
  23                ]
  24         with Program(lst, bigendian) as program:
  25             self.run_tst_program(program, [1, 2, 3])
  26
  27     def test_1_divw_(self):
  28         lst = ["addi 1, 0, 0x5678",
  29                "addi 2, 0, 0x1234",
  30                "divw.  3, 1, 2",
  31                ]
  32         with Program(lst, bigendian) as program:
  33             self.run_tst_program(program, [1, 2, 3])
  34
  35     def test_2_divw_(self):
  36         lst = ["addi 1, 0, 0x1234",
  37                "addi 2, 0, 0x5678",
  38                "divw.  3, 1, 2",
  39                ]
  40         with Program(lst, bigendian) as program:
  41             self.run_tst_program(program, [1, 2, 3])
  42
  43     def test_1_divwe(self):
  44         lst = ["addi 1, 0, 0x5678",
  45                "addi 2, 0, 0x1234",
  46                "divwe  3, 1, 2",
  47                ]
  48         with Program(lst, bigendian) as program:
  49             self.run_tst_program(program, [1, 2, 3])
  50
  51     def test_2_divweu(self):
  52         lst = ["addi 1, 0, 0x5678",
  53                "addi 2, 0, 0x1234",
  54                "divweu  3, 1, 2",
  55                ]
  56         with Program(lst, bigendian) as program:
  57             self.run_tst_program(program, [1, 2, 3])
  58
  59     def test_4_moduw(self):
  60         lst = ["addi 1, 0, 0x5678",
  61                "addi 2, 0, 0x1234",
  62                "moduw  3, 1, 2",
  63                ]
  64         with Program(lst, bigendian) as program:
  65             self.run_tst_program(program, [1, 2, 3])
  66
  67     def test_5_div_regression(self):
  68         lst = ["addi 1, 0, 0x4",
  69                "addi 2, 0, 0x2",
  70                "neg 2, 2",
  71                "neg 1, 1",
  72                "divwo  3, 1, 2",
  73                ]
  74         with Program(lst, bigendian) as program:
  75             self.run_tst_program(program, [1, 2, 3])
  76
  77     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
  78                                     initial_mem=None):
  79         initial_regs = [0] * 32
  80         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs, 0,
  81                                             initial_mem, 0)
  82         self.test_data.append(tc)
  83
  84
  85 class DivZeroTestCases(FHDLTestCase):
  86     test_data = []
  87
  88     def __init__(self, name="divbyzero"):
  89         super().__init__(name)
  90         self.test_name = name
  91
  92     def test_0_divw(self):
  93         lst = ["addi 1, 0, 0x5678",
  94                "addi 2, 0, 0x0",
  95                "divw  3, 1, 2",
  96                ]
  97         with Program(lst, bigendian) as program:
  98             self.run_tst_program(program, [1, 2, 3])
  99
 100     def test_1_divwe(self):
 101         lst = ["addi 1, 0, 0x5678",
 102                "addi 2, 0, 0x0",
 103                "divwe  3, 1, 2",
 104                ]
 105         with Program(lst, bigendian) as program:
 106             self.run_tst_program(program, [1, 2, 3])
 107
 108     def test_2_divweu(self):
 109         lst = ["addi 1, 0, 0x5678",
 110                "addi 2, 0, 0x0",
 111                "divweu  3, 1, 2",
 112                ]
 113         with Program(lst, bigendian) as program:
 114             self.run_tst_program(program, [1, 2, 3])
 115
 116     def test_4_moduw(self):
 117         lst = ["addi 1, 0, 0x5678",
 118                "addi 2, 0, 0x0",
 119                "moduw  3, 1, 2",
 120                ]
 121         with Program(lst, bigendian) as program:
 122             self.run_tst_program(program, [1, 2, 3])
 123
 124     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
 125                                     initial_mem=None):
 126         initial_regs = [0] * 32
 127         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs, 0,
 128                                             initial_mem, 0)
 129         self.test_data.append(tc)
 130
 131
 132
 133 class DivDecoderTestCase(DecoderBase, DivTestCases):
 134     pass
 135
 136 class DivZeroDecoderTestCase(DecoderBase, DivZeroTestCases):
 137     pass
 138
 139 if __name__ == "__main__":
 140     unittest.main()