src/openpower/simulator/test_mul_sim.py

   1 import unittest
   2 from nmutil.formaltest import FHDLTestCase
   3 from openpower.simulator.program import Program
   4 from openpower.simulator.qemu import run_program
   5 from openpower.test.common import TestCase
   6 from openpower.simulator.test_sim import DecoderBase
   7 from openpower.endian import bigendian
   8
   9
  10
  11 class MulTestCases(FHDLTestCase):
  12     test_data = []
  13
  14     def __init__(self, name="div"):
  15         super().__init__(name)
  16         self.test_name = name
  17
  18     def tst_mullw(self):
  19         lst = ["addi 1, 0, 0x5678",
  20                "addi 2, 0, 0x1234",
  21                "mullw 3, 1, 2"]
  22         self.run_tst_program(Program(lst, bigendian), [3])
  23
  24     def test_mullwo(self):
  25         lst = ["addi 1, 0, 0x5678",
  26                "neg 1, 1",
  27                "addi 2, 0, 0x1234",
  28                "neg 2, 2",
  29                "mullwo 3, 1, 2"]
  30         self.run_tst_program(Program(lst, bigendian), [3])
  31
  32     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
  33                                     initial_mem=None):
  34         initial_regs = [0] * 32
  35         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs, 0,
  36                                             initial_mem, 0)
  37         self.test_data.append(tc)
  38
  39
  40 class MulDecoderTestCase(DecoderBase, MulTestCases):
  41     pass
  42
  43
  44 if __name__ == "__main__":
  45     unittest.main()