set srcstep/dststep to zero in StepLoop (ISACaller) at loopend
[openpower-isa.git] / src / openpower / simulator / test_shift_sim.py
1 import unittest
2 from nmutil.formaltest import FHDLTestCase
3 from openpower.simulator.program import Program
4 from openpower.simulator.qemu import run_program
5 from openpower.decoder.isa.all import ISA
6 from openpower.test.common import TestCase
7 from openpower.simulator.test_sim import DecoderBase
8 from openpower.endian import bigendian
9
10
11
12 class MulTestCases(FHDLTestCase):
13 test_data = []
14
15 def __init__(self, name="div"):
16 super().__init__(name)
17 self.test_name = name
18
19 def test_1_extswsli(self):
20 lst = ["addi 1, 0, 0x5678",
21 "extswsli 3, 1, 34"]
22 self.run_tst_program(Program(lst, bigendian), [3])
23
24 def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
25 initial_mem=None):
26 initial_regs = [0] * 32
27 tc = TestCase(prog, self.test_name, initial_regs, initial_sprs, 0,
28 initial_mem, 0)
29 self.test_data.append(tc)
30
31
32 class MulDecoderTestCase(DecoderBase, MulTestCases):
33 pass
34
35
36 if __name__ == "__main__":
37 unittest.main()