2 from nmutil
.formaltest
import FHDLTestCase
3 from openpower
.simulator
.program
import Program
4 from openpower
.simulator
.qemu
import run_program
5 from openpower
.decoder
.isa
.all
import ISA
6 from openpower
.test
.common
import TestCase
7 from openpower
.simulator
.test_sim
import DecoderBase
8 from openpower
.endian
import bigendian
12 class MulTestCases(FHDLTestCase
):
15 def __init__(self
, name
="div"):
16 super().__init
__(name
)
19 def test_1_extswsli(self
):
20 lst
= ["addi 1, 0, 0x5678",
22 self
.run_tst_program(Program(lst
, bigendian
), [3])
24 def run_tst_program(self
, prog
, initial_regs
=None, initial_sprs
=None,
26 initial_regs
= [0] * 32
27 tc
= TestCase(prog
, self
.test_name
, initial_regs
, initial_sprs
, 0,
29 self
.test_data
.append(tc
)
32 class MulDecoderTestCase(DecoderBase
, MulTestCases
):
36 if __name__
== "__main__":