1 from nmutil
.formaltest
import FHDLTestCase
3 from openpower
.simulator
.program
import Program
4 from openpower
.simulator
.qemu
import run_program
5 from openpower
.test
.common
import TestCase
6 from openpower
.simulator
.test_sim
import DecoderBase
7 from openpower
.endian
import bigendian
#XXX HACK!
10 class TrapSimTestCases(FHDLTestCase
):
13 def __init__(self
, name
="div"):
14 super().__init
__(name
)
17 def test_0_not_twi(self
):
18 lst
= ["addi 1, 0, 0x5678",
21 with
Program(lst
, bigendian
) as program
:
22 self
.run_tst_program(program
, [1])
24 def test_1_twi_eq(self
):
25 lst
= ["addi 1, 0, 0x5678",
28 with
Program(lst
, bigendian
) as program
:
29 self
.run_tst_program(program
, [1])
31 def run_tst_program(self
, prog
, initial_regs
=None, initial_sprs
=None,
33 initial_regs
= [0] * 32
34 tc
= TestCase(prog
, self
.test_name
, initial_regs
, initial_sprs
, 0,
36 self
.test_data
.append(tc
)
39 class TrapDecoderTestCase(DecoderBase
, TrapSimTestCases
):
43 if __name__
== "__main__":