src/openpower/sv/sv_analysis.py

   1 #!/usr/bin/env python2
   2 #
   3 # NOTE that this program is python2 compatible, please do not stop it
   4 # from working by adding syntax that prevents that.
   5 #
   6 # Initial version written by lkcl Oct 2020
   7 # This program analyses the Power 9 op codes and looks at in/out register uses
   8 # The results are displayed:
   9 #       https://libre-soc.org/openpower/opcode_regs_deduped/
  10 #
  11 # It finds .csv files in the directory isatables/
  12 # then goes through the categories and creates svp64 CSV augmentation
  13 # tables on a per-opcode basis
  14 #
  15 # NOTE: this program is effectively part of the Simple-V Specification.
  16 # it encapsulates the relationships of what can be SVP64-encoded and
  17 # holds all of the information on how to encode and decode SVP64.
  18 # By auto-generating tables that go into the Simple-V Specification
  19 # this program *is* the specification. do not be confused just because
  20 # it is in python: if you do not understand please ask questions and
  21 # help create patches with explanatory comments.
  22
  23 import argparse
  24 import csv
  25 import enum
  26 import os
  27 from os.path import dirname, join
  28 from glob import glob
  29 from collections import defaultdict
  30 from collections import OrderedDict
  31 from openpower.decoder.power_svp64 import SVP64RM
  32 from openpower.decoder.power_enums import find_wiki_file, get_csv
  33 from openpower.util import log
  34
  35
  36 # Ignore those containing: valid test sprs
  37 def glob_valid_csvs(root):
  38     def check_csv(fname):
  39         _, name = os.path.split(fname)
  40         if '-' in name:
  41             return False
  42         if 'valid' in fname:
  43             return False
  44         if 'test' in fname:
  45             return False
  46         if fname.endswith('insndb.csv'):
  47             return False
  48         if fname.endswith('sprs.csv'):
  49             return False
  50         if fname.endswith('minor_19_valid.csv'):
  51             return False
  52         if 'RM' in fname:
  53             return False
  54         return True
  55
  56     yield from filter(check_csv, glob(root))
  57
  58
  59 # Write an array of dictionaries to the CSV file name:
  60 def write_csv(name, items, headers):
  61     file_path = find_wiki_file(name)
  62     with open(file_path, 'w') as csvfile:
  63         writer = csv.DictWriter(csvfile, headers, lineterminator="\n")
  64         writer.writeheader()
  65         writer.writerows(items)
  66
  67 # This will return True if all values are true.
  68 # Not sure what this is about
  69
  70
  71 def blank_key(row):
  72     # for v in row.values():
  73     #    if 'SPR' in v: # skip all SPRs
  74     #        return True
  75     for v in row.values():
  76         if v:
  77             return False
  78     return True
  79
  80 # General purpose registers have names like: RA, RT, R1, ...
  81 # Floating point registers names like: FRT, FRA, FR1, ..., FRTp, ...
  82 # Return True if field is a register
  83
  84
  85 def isreg(field):
  86     return (field.startswith('R') or field.startswith('FR') or
  87             field == 'SPR')
  88
  89
  90 # These are the attributes of the instructions,
  91 # register names
  92 keycolumns = ['unit', 'in1', 'in2', 'in3', 'out', 'CR in', 'CR out',
  93               ]  # don't think we need these: 'ldst len', 'rc', 'lk']
  94
  95 tablecols = ['unit', 'in', 'outcnt', 'CR in', 'CR out', 'imm'
  96              ]  # don't think we need these: 'ldst len', 'rc', 'lk']
  97
  98
  99 def create_key(row):
 100     """ create an equivalent of a database key by which it is possible
 101     to easily categorise an instruction.  later this category is used
 102     to decide what kind of EXTRA encoding is to be done because the
 103     key contains the total number of input and output registers
 104     """
 105     res = OrderedDict()
 106     #print ("row", row)
 107     for key in keycolumns:
 108         # registers IN - special-case: count number of regs RA/RB/RC/RS
 109         if key in ['in1', 'in2', 'in3']:
 110             if 'in' not in res:
 111                 res['in'] = 0
 112             if row['unit'] == 'BRANCH':  # branches must not include Vector SPRs
 113                 continue
 114             if isreg(row[key]):
 115                 res['in'] += 1
 116
 117         # registers OUT
 118         if key == 'out':
 119             # If upd is 1 then increment the count of outputs
 120             if 'outcnt' not in res:
 121                 res['outcnt'] = 0
 122             if isreg(row[key]):
 123                 res['outcnt'] += 1
 124             if row['upd'] == '1':
 125                 res['outcnt'] += 1
 126
 127         # CRs (Condition Register) (CR0 .. CR7)
 128         if key.startswith('CR'):
 129             if row[key].startswith('NONE'):
 130                 res[key] = '0'
 131             else:
 132                 res[key] = '1'
 133             if row['comment'].startswith('cr'):
 134                 res['crop'] = '1'
 135         # unit
 136         if key == 'unit':
 137             if row[key] == 'LDST':  # we care about LDST units
 138                 res[key] = row[key]
 139             else:
 140                 res[key] = 'OTHER'
 141         # LDST len (LoadStore length)
 142         if key.startswith('ldst'):
 143             if row[key].startswith('NONE'):
 144                 res[key] = '0'
 145             else:
 146                 res[key] = '1'
 147         # rc, lk
 148         if key in ['rc', 'lk']:
 149             if row[key] == 'ONE':
 150                 res[key] = '1'
 151             elif row[key] == 'NONE':
 152                 res[key] = '0'
 153             else:
 154                 res[key] = 'R'
 155         if key == 'lk':
 156             res[key] = row[key]
 157
 158     # Convert the numerics 'in' & 'outcnt' to strings
 159     res['in'] = str(res['in'])
 160     res['outcnt'] = str(res['outcnt'])
 161
 162     # constants
 163     if row['in2'].startswith('CONST_'):
 164         res['imm'] = "1"  # row['in2'].split("_")[1]
 165     else:
 166         res['imm'] = ''
 167
 168     return res
 169
 170 #
 171
 172
 173 def dformat(d):
 174     res = []
 175     for k, v in d.items():
 176         res.append("%s: %s" % (k, v))
 177     return ' '.join(res)
 178
 179
 180 def tformat(d):
 181     return "| " + ' | '.join(d) + " |"
 182
 183
 184 def keyname(row):
 185     """converts a key into a readable string. anything null or zero
 186     is skipped, shortening the readable string
 187     """
 188     res = []
 189     if row['unit'] != 'OTHER':
 190         res.append(row['unit'])
 191     if row['in'] != '0':
 192         res.append('%sR' % row['in'])
 193     if row['outcnt'] != '0':
 194         res.append('%sW' % row['outcnt'])
 195     if row['CR in'] == '1' and row['CR out'] == '1':
 196         if 'crop' in row:
 197             res.append("CR=2R1W")
 198         else:
 199             res.append("CRio")
 200     elif row['CR in'] == '1':
 201         res.append("CRi")
 202     elif row['CR out'] == '1':
 203         res.append("CRo")
 204     elif 'imm' in row and row['imm']:
 205         res.append("imm")
 206     return '-'.join(res)
 207
 208
 209 class Format(enum.Enum):
 210     BINUTILS = enum.auto()
 211     VHDL = enum.auto()
 212
 213     @classmethod
 214     def _missing_(cls, value):
 215         return {
 216             "binutils": Format.BINUTILS,
 217             "vhdl": Format.VHDL,
 218         }[value.lower()]
 219
 220     def __str__(self):
 221         return self.name.lower()
 222
 223     def declarations(self, values, lens):
 224         def declaration_binutils(value, width):
 225             yield f"/* TODO: implement binutils declaration (value={value!r}, width={width!r}) */"
 226
 227         def declaration_vhdl(value, width):
 228             yield f"    type sv_{value}_rom_array_t is " \
 229                 f"array(0 to {width}) of sv_decode_rom_t;"
 230
 231         for value in values:
 232             if value not in lens:
 233                 todo = [f"TODO {value} (or no SVP64 augmentation)"]
 234                 todo = self.wrap_comment(todo)
 235                 yield from map(lambda line: f"    {line}", todo)
 236             else:
 237                 width = lens[value]
 238                 yield from {
 239                     Format.BINUTILS: declaration_binutils,
 240                     Format.VHDL: declaration_vhdl,
 241                 }[self](value, width)
 242
 243     def definitions(self, entries_svp64, fullcols):
 244         def definitions_vhdl():
 245             for (value, entries) in entries_svp64.items():
 246                 yield ""
 247                 yield f"    constant sv_{value}_decode_rom_array :"
 248                 yield f"             sv_{value}_rom_array_t := ("
 249                 yield f"        -- {'  '.join(fullcols)}"
 250
 251                 for (op, insn, row) in entries:
 252                     yield f"    {op:>13} => ({', '.join(row)}), -- {insn}"
 253
 254                 yield f"    {'others':>13} => sv_illegal_inst"
 255                 yield "    );"
 256                 yield ""
 257
 258         def definitions_binutils():
 259             yield f"/* TODO: implement binutils definitions */"
 260
 261         yield from {
 262             Format.BINUTILS: definitions_binutils,
 263             Format.VHDL: definitions_vhdl,
 264         }[self]()
 265
 266     def wrap_comment(self, lines):
 267         def wrap_comment_binutils(lines):
 268             lines = tuple(lines)
 269             if len(lines) == 1:
 270                 yield f"/* {lines[0]} */"
 271             else:
 272                 yield "/*"
 273                 yield from map(lambda line: f" * {line}", lines)
 274                 yield " */"
 275
 276         def wrap_comment_vhdl(lines):
 277             yield from map(lambda line: f"-- {line}", lines)
 278
 279         yield from {
 280             Format.BINUTILS: wrap_comment_binutils,
 281             Format.VHDL: wrap_comment_vhdl,
 282         }[self](lines)
 283
 284
 285 def read_csvs():
 286     csvs = {}
 287     csvs_svp64 = {}
 288     bykey = {}
 289     primarykeys = set()
 290     dictkeys = OrderedDict()
 291     immediates = {}
 292     insns = {}  # dictionary of CSV row, by instruction
 293     insn_to_csv = {}
 294
 295     # Expand that (all .csv files)
 296     pth = find_wiki_file("*.csv")
 297
 298     # Ignore those containing: valid test sprs
 299     for fname in glob_valid_csvs(pth):
 300         csvname = os.path.split(fname)[1]
 301         csvname_ = csvname.split(".")[0]
 302         # csvname is something like: minor_59.csv, fname the whole path
 303         csv = get_csv(fname)
 304         csvs[fname] = csv
 305         csvs_svp64[csvname_] = []
 306         for row in csv:
 307             if blank_key(row):
 308                 continue
 309             #print("row", row)
 310             insn_name = row['comment']
 311             condition = row['CONDITIONS']
 312             # skip instructions that are not suitable
 313             if insn_name.startswith("l") and insn_name.endswith("br"):
 314                 continue  # skip pseudo-alias lxxxbr
 315             if insn_name in ['mcrxr', 'mcrxrx', 'darn']:
 316                 continue
 317             if insn_name in ['bctar', 'bcctr']:  # for now. TODO
 318                 continue
 319             if 'rfid' in insn_name:
 320                 continue
 321             if 'addpcis' in insn_name:  # skip for now
 322                 continue
 323
 324             # sv.bc is being classified as 2P-2S-1D by mistake due to SPRs
 325             if insn_name.startswith('bc'):
 326                 # whoops: remove out reg (SPRs CTR etc)
 327                 row['in1'] = 'NONE'
 328                 row['in2'] = 'NONE'
 329                 row['in3'] = 'NONE'
 330                 row['out'] = 'NONE'
 331
 332             insns[(insn_name, condition)] = row  # accumulate csv data
 333             insn_to_csv[insn_name] = csvname_  # CSV file name by instruction
 334             dkey = create_key(row)
 335             key = tuple(dkey.values())
 336             #print("key=", key, dkey)
 337             dictkeys[key] = dkey
 338             primarykeys.add(key)
 339             if key not in bykey:
 340                 bykey[key] = []
 341             bykey[key].append((csvname, row['opcode'], insn_name, condition,
 342                                row['form'].upper() + '-Form'))
 343
 344             # detect immediates, collate them (useful info)
 345             if row['in2'].startswith('CONST_'):
 346                 imm = row['in2'].split("_")[1]
 347                 if key not in immediates:
 348                     immediates[key] = set()
 349                 immediates[key].add(imm)
 350
 351     primarykeys = list(primarykeys)
 352     primarykeys.sort()
 353
 354     return (csvs, csvs_svp64, primarykeys, bykey, insn_to_csv, insns,
 355             dictkeys, immediates)
 356
 357
 358 def regs_profile(insn, res):
 359     """get a more detailed register profile: 1st operand is RA,
 360     2nd is RB, etc. etc
 361     """
 362     regs = []
 363     for k in ['in1', 'in2', 'in3', 'out', 'CR in', 'CR out']:
 364         if insn[k].startswith('CONST'):
 365             res[k] = ''
 366             regs.append('')
 367         else:
 368             res[k] = insn[k]
 369             if insn[k] == 'RA_OR_ZERO':
 370                 regs.append('RA')
 371             elif insn[k] != 'NONE':
 372                 regs.append(insn[k])
 373             else:
 374                 regs.append('')
 375     return regs
 376
 377
 378 def extra_classifier(insn_name, value, name, res, regs):
 379     """extra_classifier: creates the SVP64.RM EXTRA2/3 classification.
 380     there is very little space (9 bits) to mark register operands
 381     (RT RA RB, BA BB, BFA, FRS etc.) with the "extra" information
 382     needed to tell if *EACH* operand (of which there can be up to five!)
 383     is Vectorised, and whether its numbering is extended into the
 384     0..127 range rather than the limited 3/5 bit of Scalar v3.0 Power ISA.
 385
 386     thus begins the rather tedious but by-rote examination of EVERY
 387     Scalar instruction, working out how best to tell a decoder how to
 388     extend the registers.  EXTRA2 can have up to 4 slots (of 2 bit each)
 389     where due to RM.EXTRA being 9 bits, EXTRA3 can have up to 3 slots
 390     (of 3 bit each).  the index REGNAME says which slot the register
 391     named REGNAME must read its decoding from.  d: means destination,
 392     s: means source.  some are *shared slots* especially LDST update.
 393     some Rc=1 ops have the CR0/CR1 as a co-result which is also
 394     obviously Vectorised if the result is Vectorised.
 395
 396     it is actually quite straightforward but the sheer quantity of
 397     Scalar Power ISA instructions made it prudent to do this in an
 398     intelligent way, almost by-rote, by analysing the register profiles.
 399     """
 400     # for LD/ST FP, use FRT/FRS not RT/RS, and use CR1 not CR0
 401     if insn_name.startswith("lf"):
 402         dRT = 'd:FRT'
 403         dCR = 'd:CR1'
 404     else:
 405         dRT = 'd:RT'
 406         dCR = 'd:CR0'
 407     if insn_name.startswith("stf"):
 408         sRS = 's:FRS'
 409         dCR = 'd:CR1'
 410     else:
 411         sRS = 's:RS'
 412         dCR = 'd:CR0'
 413
 414     # sigh now the fun begins.  this isn't the sanest way to do it
 415     # but the patterns are pretty regular.  we start with the "profile"
 416     # because that determines how much space is available (total num
 417     # regs to decode) then if necessary begin apecialising either
 418     # by the instruction name or through more detailed register
 419     # profiling. example:
 420     #     if regs == ['RA', '', '', 'RT', '', '']:
 421     # is in the order in1  in2  in3 out1 out2 Rc=1
 422
 423     # ********
 424     # start with LD/ST
 425
 426     if value == 'LDSTRM-2P-1S1D':
 427         res['Etype'] = 'EXTRA3'  # RM EXTRA3 type
 428         res['0'] = dRT    # RT: Rdest_EXTRA3
 429         res['1'] = 's:RA'  # RA: Rsrc1_EXTRA3
 430
 431     elif value == 'LDSTRM-2P-1S2D':
 432         res['Etype'] = 'EXTRA2'  # RM EXTRA2 type
 433         res['0'] = dRT    # RT: Rdest_EXTRA3
 434         res['1'] = 'd:RA'  # RA: Rdest2_EXTRA2
 435         res['2'] = 's:RA'  # RA: Rsrc1_EXTRA2
 436
 437     elif value == 'LDSTRM-2P-2S':
 438         # stw, std, sth, stb
 439         res['Etype'] = 'EXTRA3'  # RM EXTRA3 type
 440         res['0'] = sRS    # RS: Rdest1_EXTRA3
 441         res['1'] = 's:RA'  # RA: Rsrc1_EXTRA3
 442
 443     elif value == 'LDSTRM-2P-2S1D':
 444         if 'st' in insn_name and 'x' not in insn_name:  # stwu/stbu etc
 445             res['Etype'] = 'EXTRA2'  # RM EXTRA2 type
 446             res['0'] = 'd:RA'  # RA: Rdest1_EXTRA2
 447             res['1'] = sRS    # RS: Rdsrc1_EXTRA2
 448             res['2'] = 's:RA'  # RA: Rsrc2_EXTRA2
 449         elif 'st' in insn_name and 'x' in insn_name:  # stwux
 450             res['Etype'] = 'EXTRA2'  # RM EXTRA2 type
 451             res['0'] = 'd:RA'  # RA: Rdest1_EXTRA2
 452             # RS: Rdest2_EXTRA2, RA: Rsrc1_EXTRA2
 453             res['1'] = "%s;%s" % (sRS, 's:RA')
 454             res['2'] = 's:RB'  # RB: Rsrc2_EXTRA2
 455         elif 'u' in insn_name:  # ldux etc.
 456             res['Etype'] = 'EXTRA2'  # RM EXTRA2 type
 457             res['0'] = dRT    # RT: Rdest1_EXTRA2
 458             res['1'] = 'd:RA'  # RA: Rdest2_EXTRA2
 459             res['2'] = 's:RB'  # RB: Rsrc1_EXTRA2
 460         else:
 461             res['Etype'] = 'EXTRA2'  # RM EXTRA2 type
 462             res['0'] = dRT     # RT: Rdest1_EXTRA2
 463             res['1'] = 's:RA'  # RA: Rsrc1_EXTRA2
 464             res['2'] = 's:RB'  # RB: Rsrc2_EXTRA2
 465
 466     elif value == 'LDSTRM-2P-3S':
 467         res['Etype'] = 'EXTRA2'  # RM EXTRA2 type
 468         if 'cx' in insn_name:
 469             res['0'] = "%s;%s" % (sRS, dCR)  # RS: Rsrc1_EXTRA2 CR0: dest
 470         else:
 471             res['0'] = sRS  # RS: Rsrc1_EXTRA2
 472         res['1'] = 's:RA'  # RA: Rsrc2_EXTRA2
 473         res['2'] = 's:RB'  # RA: Rsrc3_EXTRA2
 474
 475     # **********
 476     # now begins,arithmetic
 477
 478     elif value == 'RM-2P-1S1D':
 479         res['Etype'] = 'EXTRA3'  # RM EXTRA3 type
 480         if insn_name == 'mtspr':
 481             res['0'] = 'd:SPR'  # SPR: Rdest1_EXTRA3
 482             res['1'] = 's:RS'  # RS: Rsrc1_EXTRA3
 483         elif insn_name == 'mfspr':
 484             res['0'] = 'd:RS'  # RS: Rdest1_EXTRA3
 485             res['1'] = 's:SPR'  # SPR: Rsrc1_EXTRA3
 486         elif name == 'CRio' and insn_name == 'mcrf':
 487             res['0'] = 'd:BF'  # BFA: Rdest1_EXTRA3
 488             res['1'] = 's:BFA'  # BFA: Rsrc1_EXTRA3
 489         elif 'mfcr' in insn_name or 'mfocrf' in insn_name:
 490             res['0'] = 'd:RT'  # RT: Rdest1_EXTRA3
 491             res['1'] = 's:CR'  # CR: Rsrc1_EXTRA3
 492         elif insn_name == 'setb':
 493             res['0'] = 'd:RT'  # RT: Rdest1_EXTRA3
 494             res['1'] = 's:BFA'  # BFA: Rsrc1_EXTRA3
 495         elif insn_name.startswith('cmp'):  # cmpi
 496             res['0'] = 'd:BF'  # BF: Rdest1_EXTRA3
 497             res['1'] = 's:RA'  # RA: Rsrc1_EXTRA3
 498         elif regs == ['RA', '', '', 'RT', '', '']:
 499             res['0'] = 'd:RT'  # RT: Rdest1_EXTRA3
 500             res['1'] = 's:RA'  # RA: Rsrc1_EXTRA3
 501         elif regs == ['RA', '', '', 'RT', '', 'CR0']:
 502             res['0'] = 'd:RT;d:CR0'  # RT,CR0: Rdest1_EXTRA3
 503             res['1'] = 's:RA'  # RA: Rsrc1_EXTRA3
 504         elif (regs == ['RS', '', '', 'RA', '', 'CR0'] or
 505               regs == ['', '', 'RS', 'RA', '', 'CR0']):
 506             res['0'] = 'd:RA;d:CR0'  # RA,CR0: Rdest1_EXTRA3
 507             res['1'] = 's:RS'  # RS: Rsrc1_EXTRA3
 508         elif regs == ['RS', '', '', 'RA', '', '']:
 509             res['0'] = 'd:RA'  # RA: Rdest1_EXTRA3
 510             res['1'] = 's:RS'  # RS: Rsrc1_EXTRA3
 511         elif regs == ['', 'FRB', '', 'FRT', '0', 'CR1']:
 512             res['0'] = 'd:FRT;d:CR1'  # FRT,CR1: Rdest1_EXTRA3
 513             res['1'] = 's:FRA'  # FRA: Rsrc1_EXTRA3
 514         elif regs == ['', 'FRB', '', '', '', 'CR1']:
 515             res['0'] = 'd:CR1'  # CR1: Rdest1_EXTRA3
 516             res['1'] = 's:FRB'  # FRA: Rsrc1_EXTRA3
 517         elif regs == ['', 'FRB', '', '', '', 'BF']:
 518             res['0'] = 'd:BF'  # BF: Rdest1_EXTRA3
 519             res['1'] = 's:FRB'  # FRA: Rsrc1_EXTRA3
 520         elif regs == ['', 'FRB', '', 'FRT', '', 'CR1']:
 521             res['0'] = 'd:FRT;d:CR1'  # FRT,CR1: Rdest1_EXTRA3
 522             res['1'] = 's:FRB'  # FRB: Rsrc1_EXTRA3
 523         elif insn_name == 'fishmv':
 524             # an overwrite instruction
 525             res['0'] = 'd:FRS'  # FRS: Rdest1_EXTRA3
 526             res['1'] = 's:FRS'  # FRS: Rsrc1_EXTRA3
 527         elif insn_name == 'setvl':
 528             res['0'] = 'd:RT'  # RT: Rdest1_EXTRA3
 529             res['1'] = 's:RA'  # RS: Rsrc1_EXTRA3
 530         else:
 531             res['0'] = 'TODO'
 532             print("regs TODO", insn_name, regs)
 533
 534     elif value == 'RM-1P-2S1D':
 535         res['Etype'] = 'EXTRA3'  # RM EXTRA3 type
 536         if insn_name.startswith('cr'):
 537             res['0'] = 'd:BT'  # BT: Rdest1_EXTRA3
 538             res['1'] = 's:BA'  # BA: Rsrc1_EXTRA3
 539             res['2'] = 's:BB'  # BB: Rsrc2_EXTRA3
 540         elif regs == ['FRA', '', 'FRC', 'FRT', '', 'CR1']:
 541             res['0'] = 'd:FRT;d:CR1'  # FRT,CR1: Rdest1_EXTRA3
 542             res['1'] = 's:FRA'  # FRA: Rsrc1_EXTRA3
 543             res['2'] = 's:FRC'  # FRC: Rsrc1_EXTRA3
 544         # should be for fcmp
 545         elif regs == ['FRA', 'FRB', '', '', '', 'BF']:
 546             res['0'] = 'd:BF'  # BF: Rdest1_EXTRA3
 547             res['1'] = 's:FRA'  # FRA: Rsrc1_EXTRA3
 548             res['2'] = 's:FRB'  # FRB: Rsrc1_EXTRA3
 549         elif regs == ['FRA', 'FRB', '', 'FRT', '', '']:
 550             res['0'] = 'd:FRT'  # FRT: Rdest1_EXTRA3
 551             res['1'] = 's:FRA'  # FRA: Rsrc1_EXTRA3
 552             res['2'] = 's:FRB'  # FRB: Rsrc1_EXTRA3
 553         elif regs == ['FRA', 'FRB', '', 'FRT', '', 'CR1']:
 554             res['0'] = 'd:FRT;d:CR1'  # FRT,CR1: Rdest1_EXTRA3
 555             res['1'] = 's:FRA'  # FRA: Rsrc1_EXTRA3
 556             res['2'] = 's:FRB'  # FRB: Rsrc1_EXTRA3
 557         elif regs == ['FRA', 'RB', '', 'FRT', '', 'CR1']:
 558             res['0'] = 'd:FRT;d:CR1'  # FRT,CR1: Rdest1_EXTRA3
 559             res['1'] = 's:FRA'  # FRA: Rsrc1_EXTRA3
 560             res['2'] = 's:RB'  # RB: Rsrc1_EXTRA3
 561         elif name == '2R-1W' or insn_name == 'cmpb':  # cmpb
 562             if insn_name in ['bpermd', 'cmpb']:
 563                 res['0'] = 'd:RA'  # RA: Rdest1_EXTRA3
 564                 res['1'] = 's:RS'  # RS: Rsrc1_EXTRA3
 565             else:
 566                 res['0'] = 'd:RT'  # RT: Rdest1_EXTRA3
 567                 res['1'] = 's:RA'  # RA: Rsrc1_EXTRA3
 568             res['2'] = 's:RB'  # RB: Rsrc1_EXTRA3
 569         elif insn_name.startswith('cmp'):  # cmp
 570             res['0'] = 'd:BF'  # BF: Rdest1_EXTRA3
 571             res['1'] = 's:RA'  # RA: Rsrc1_EXTRA3
 572             res['2'] = 's:RB'  # RB: Rsrc1_EXTRA3
 573         elif (regs == ['', 'RB', 'RS', 'RA', '', 'CR0'] or
 574               regs == ['RS', 'RB', '', 'RA', '', 'CR0']):
 575             res['0'] = 'd:RA;d:CR0'  # RA,CR0: Rdest1_EXTRA3
 576             res['1'] = 's:RB'  # RB: Rsrc1_EXTRA3
 577             res['2'] = 's:RS'  # RS: Rsrc1_EXTRA3
 578         elif regs == ['RA', 'RB', '', 'RT', '', 'CR0']:
 579             res['0'] = 'd:RT;d:CR0'  # RT,CR0: Rdest1_EXTRA3
 580             res['1'] = 's:RA'  # RA: Rsrc1_EXTRA3
 581             res['2'] = 's:RB'  # RB: Rsrc1_EXTRA3
 582         elif regs == ['RA', '', 'RS', 'RA', '', 'CR0']:
 583             res['0'] = 'd:RA;d:CR0'  # RA,CR0: Rdest1_EXTRA3
 584             res['1'] = 's:RA'  # RA: Rsrc1_EXTRA3
 585             res['2'] = 's:RS'  # RS: Rsrc1_EXTRA3
 586         else:
 587             res['0'] = 'TODO'
 588
 589     elif value == 'RM-2P-2S1D':
 590         res['Etype'] = 'EXTRA2'  # RM EXTRA2 type
 591         if insn_name.startswith('mt'):  # mtcrf
 592             res['0'] = 'd:CR'  # CR: Rdest1_EXTRA2
 593             res['1'] = 's:RS'  # RS: Rsrc1_EXTRA2
 594             res['2'] = 's:CR'  # CR: Rsrc2_EXTRA2
 595         else:
 596             res['0'] = 'TODO'
 597
 598     elif value == 'RM-1P-3S1D':
 599         res['Etype'] = 'EXTRA2'  # RM EXTRA2 type
 600         if regs == ['RA', 'RB', 'RC', 'RT', '', '']:  # madd*
 601             res['0'] = 'd:RT'  # RT,CR0: Rdest1_EXTRA2
 602             res['1'] = 's:RA'  # RA: Rsrc1_EXTRA2
 603             res['2'] = 's:RB'  # RT: Rsrc2_EXTRA2
 604             res['3'] = 's:RC'  # RT: Rsrc3_EXTRA2
 605         elif regs == ['RA', 'RB', 'RC', 'RT', '', 'CR0']:  # pcdec
 606             res['0'] = 'd:RT;d:CR0'  # RT,CR0: Rdest1_EXTRA2
 607             res['1'] = 's:RA'  # RA: Rsrc1_EXTRA2
 608             res['2'] = 's:RB'  # RT: Rsrc2_EXTRA2
 609             res['3'] = 's:RC'  # RT: Rsrc3_EXTRA2
 610         elif regs == ['RA', 'RB', 'RT', 'RT', '', 'CR0']:  # overwrite 3-in
 611             res['0'] = 'd:RT;d:CR0'  # RT,CR0: Rdest1_EXTRA2
 612             res['1'] = 's:RA'  # RA: Rsrc1_EXTRA2
 613             res['2'] = 's:RB'  # RT: Rsrc2_EXTRA2
 614             res['3'] = 's:RT'  # RT: Rsrc3_EXTRA2
 615         elif insn_name == 'isel':
 616             res['0'] = 'd:RT'  # RT: Rdest1_EXTRA2
 617             res['1'] = 's:RA'  # RA: Rsrc1_EXTRA2
 618             res['2'] = 's:RB'  # RT: Rsrc2_EXTRA2
 619             res['3'] = 's:BC'  # BC: Rsrc3_EXTRA2
 620         else:  # fmadd*
 621             res['0'] = 'd:FRT;d:CR1'  # FRT, CR1: Rdest1_EXTRA2
 622             res['1'] = 's:FRA'  # FRA: Rsrc1_EXTRA2
 623             res['2'] = 's:FRB'  # FRB: Rsrc2_EXTRA2
 624             res['3'] = 's:FRC'  # FRC: Rsrc3_EXTRA2
 625
 626     elif value == 'RM-1P-1D':
 627         res['Etype'] = 'EXTRA3'  # RM EXTRA3 type
 628         if insn_name == 'svstep':
 629             res['0'] = 'd:RT;d:CR0'  # RT,CR0: Rdest1_EXTRA3
 630         if insn_name == 'fmvis':
 631             res['0'] = 'd:FRS'  # FRS: Rdest1_EXTRA3
 632
 633     # HACK! thos should be RM-1P-1S butvthere is a bug with sv.bc
 634     elif value == 'RM-2P-1S':
 635         res['Etype'] = 'EXTRA3'  # RM EXTRA3 type
 636         if insn_name.startswith('bc'):
 637             res['0'] = 's:BI'  # BI: Rsrc1_EXTRA3
 638
 639
 640 def process_csvs(format):
 641
 642     print("# Draft SVP64 Power ISA register 'profile's")
 643     print('')
 644     print("this page is auto-generated, do not edit")
 645     print("created by http://libre-soc.org/openpower/sv_analysis.py")
 646     print('')
 647
 648     (csvs, csvs_svp64, primarykeys, bykey, insn_to_csv, insns,
 649      dictkeys, immediates) = read_csvs()
 650
 651     # mapping to old SVPrefix "Forms"
 652     mapsto = {'3R-1W-CRo': 'RM-1P-3S1D',
 653               '3R-1W': 'RM-1P-3S1D',
 654               '2R-1W-CRio': 'RM-1P-2S1D',
 655               '2R-1W-CRi': 'RM-1P-3S1D',
 656               '2R-1W-CRo': 'RM-1P-2S1D',
 657               '2R': 'non-SV',
 658               '2R-1W': 'RM-1P-2S1D',
 659               '1R-CRio': 'RM-2P-2S1D',
 660               '2R-CRio': 'RM-1P-2S1D',
 661               '2R-CRo': 'RM-1P-2S1D',
 662               '1R': 'non-SV',
 663               '1R-1W-CRio': 'RM-2P-1S1D',
 664               '1R-1W-CRo': 'RM-2P-1S1D',
 665               '1R-1W': 'RM-2P-1S1D',
 666               '1R-1W-imm': 'RM-2P-1S1D',
 667               '1R-CRo': 'RM-2P-1S1D',
 668               '1R-imm': 'RM-1P-1S',
 669               '1W-CRo': 'RM-1P-1D',
 670               '1W': 'non-SV',
 671               '1W-imm': 'RM-1P-1D',
 672               '1W-CRi': 'RM-2P-1S1D',
 673               'CRio': 'RM-2P-1S1D',
 674               'CR=2R1W': 'RM-1P-2S1D',
 675               'CRi': 'RM-2P-1S',  # HACK, bc here, it should be 1P
 676               'imm': 'non-SV',
 677               '': 'non-SV',
 678               'LDST-2R-imm': 'LDSTRM-2P-2S',
 679               'LDST-2R-1W-imm': 'LDSTRM-2P-2S1D',
 680               'LDST-2R-1W': 'LDSTRM-2P-2S1D',
 681               'LDST-2R-2W': 'LDSTRM-2P-2S1D',
 682               'LDST-1R-1W-imm': 'LDSTRM-2P-1S1D',
 683               'LDST-1R-2W-imm': 'LDSTRM-2P-1S2D',
 684               'LDST-3R': 'LDSTRM-2P-3S',
 685               'LDST-3R-CRo': 'LDSTRM-2P-3S',  # st*x
 686               'LDST-3R-1W': 'LDSTRM-2P-2S1D',  # st*x
 687               }
 688     print("# map to old SV Prefix")
 689     print('')
 690     print('|internal key | public name |')
 691     print('|-----        | ----------  |')
 692     for key in primarykeys:
 693         name = keyname(dictkeys[key])
 694         value = mapsto.get(name, "-")
 695         print(tformat([name, value + " "]))
 696     print('')
 697     print('')
 698
 699     print("# keys")
 700     print('')
 701     print(tformat(tablecols) + " imms | name |")
 702     print(tformat([" - "] * (len(tablecols)+2)))
 703
 704     # print out the keys and the table from which they're derived
 705     for key in primarykeys:
 706         name = keyname(dictkeys[key])
 707         row = tformat(dictkeys[key].values())
 708         imms = list(immediates.get(key, ""))
 709         imms.sort()
 710         row += " %s | " % ("/".join(imms))
 711         row += " %s |" % name
 712         print(row)
 713     print('')
 714     print('')
 715
 716     # print out, by remap name, all the instructions under that category
 717     for key in primarykeys:
 718         name = keyname(dictkeys[key])
 719         value = mapsto.get(name, "-")
 720         print("## %s (%s)" % (name, value))
 721         print('')
 722         print(tformat(['CSV', 'opcode', 'asm', 'flags', 'form']))
 723         print(tformat(['---', '------', '---', '-----', '----']))
 724         rows = bykey[key]
 725         rows.sort()
 726         for row in rows:
 727             print(tformat(row))
 728         print('')
 729         print('')
 730
 731     # for fname, csv in csvs.items():
 732     #    print (fname)
 733
 734     # for insn, row in insns.items():
 735     #    print (insn, row)
 736
 737     print("# svp64 remaps")
 738     svp64 = OrderedDict()
 739     # create a CSV file, per category, with SV "augmentation" info
 740     # XXX note: 'out2' not added here, needs to be added to CSV files
 741     # KEEP TRACK OF THESE https://bugs.libre-soc.org/show_bug.cgi?id=619
 742     csvcols = ['insn', 'mode', 'CONDITIONS', 'Ptype', 'Etype', 'SM']
 743     csvcols += ['0', '1', '2', '3']
 744     csvcols += ['in1', 'in2', 'in3', 'out', 'CR in', 'CR out']  # temporary
 745     for key in primarykeys:
 746         # get the decoded key containing row-analysis, and name/value
 747         dkey = dictkeys[key]
 748         name = keyname(dkey)
 749         value = mapsto.get(name, "-")
 750         if value == 'non-SV':
 751             continue
 752
 753         # print out svp64 tables by category
 754         print("* **%s**: %s" % (name, value))
 755
 756         # store csv entries by svp64 RM category
 757         if value not in svp64:
 758             svp64[value] = []
 759
 760         rows = bykey[key]
 761         rows.sort()
 762
 763         for row in rows:
 764             # for idx in range(len(row)):
 765             #    if row[idx] == 'NONE':
 766             #        row[idx] = ''
 767             # get the instruction
 768             #print(key, row)
 769             insn_name = row[2]
 770             condition = row[3]
 771             insn = insns[(insn_name, condition)]
 772
 773             # start constructing svp64 CSV row
 774             res = OrderedDict()
 775             res['insn'] = insn_name
 776             res['CONDITIONS'] = condition
 777             res['Ptype'] = value.split('-')[1]  # predication type (RM-xN-xxx)
 778             # get whether R_xxx_EXTRAn fields are 2-bit or 3-bit
 779             res['Etype'] = 'EXTRA2'
 780             # go through each register matching to Rxxxx_EXTRAx
 781             for k in ['0', '1', '2', '3']:
 782                 res[k] = ''
 783             # create "fake" out2 (TODO, needs to be added to CSV files)
 784             # KEEP TRACK HERE https://bugs.libre-soc.org/show_bug.cgi?id=619
 785             res['out2'] = 'NONE'
 786             if insn['upd'] == '1':  # LD/ST with update has RA as out2
 787                 res['out2'] = 'RA'
 788
 789             # set the SVP64 mode to NORMAL, LDST, BRANCH or CR
 790             crops = ['mfcr', 'mfocrf', 'mtcrf', 'mtocrf',
 791                      ]
 792             mode = 'NORMAL'
 793             if value.startswith('LDST'):
 794                 if 'x' in insn_name:  # Indexed detection
 795                     mode = 'LDST_IDX'
 796                 else:
 797                     mode = 'LDST_IMM'
 798             elif insn_name.startswith('bc'):
 799                 mode = 'BRANCH'
 800             elif insn_name.startswith('cmp') or insn_name.startswith('cr') or insn_name in crops:
 801                 mode = 'CROP'
 802             res['mode'] = mode
 803
 804             # create a register profile list (update res row as well)
 805             regs = regs_profile(insn, res)
 806
 807             #print("regs", insn_name, regs)
 808             extra_classifier(insn_name, value, name, res, regs)
 809
 810             # source-mask is hard to detect, it's part of RM-nn-nn.
 811             # to make disassembler easier, create a yes/no decision here
 812             # see https://libre-soc.org/openpower/sv/svp64/#extra_remap
 813             # MASK_SRC
 814             vstripped = value.replace("LDST", "")
 815             if vstripped in ['RM-2P-1S1D', 'RM-2P-2S',
 816                              'RM-2P-2S1D', 'RM-2P-1S2D', 'RM-2P-3S',
 817                              ]:
 818                 res['SM'] = 'EN'
 819             else:
 820                 res['SM'] = 'NO'
 821             # add to svp64 csvs
 822             # for k in ['in1', 'in2', 'in3', 'out', 'CR in', 'CR out']:
 823             #    del res[k]
 824             # if res['0'] != 'TODO':
 825             for k in res:
 826                 if k == 'CONDITIONS':
 827                     continue
 828                 if res[k] == 'NONE' or res[k] == '':
 829                     res[k] = '0'
 830             svp64[value].append(res)
 831             # also add to by-CSV version
 832             csv_fname = insn_to_csv[insn_name]
 833             csvs_svp64[csv_fname].append(res)
 834
 835     print('')
 836
 837     # now write out the csv files
 838     for value, csv in svp64.items():
 839         if value == '-':
 840             continue
 841             from time import sleep
 842             print("WARNING, filename '-' should NOT exist. instrs missing")
 843             print("TODO: fix this (and put in the bugreport number here)")
 844             sleep(2)
 845         # print out svp64 tables by category
 846         print("## %s" % value)
 847         print('')
 848         cols = csvcols + ['out2']
 849         print(tformat(cols))
 850         print(tformat([" - "] * (len(cols))))
 851         for d in csv:
 852             row = []
 853             for k in cols:
 854                 row.append(d[k])
 855             print(tformat(row))
 856         print('')
 857
 858         #csvcols = ['insn', 'Ptype', 'Etype', '0', '1', '2', '3']
 859         write_csv("%s.csv" % value, csv, csvcols + ['out2'])
 860
 861     # okaaay, now we re-read them back in for producing microwatt SV
 862
 863     # get SVP64 augmented CSV files
 864     svt = SVP64RM(microwatt_format=True)
 865     # Expand that (all .csv files)
 866     pth = find_wiki_file("*.csv")
 867
 868     # Ignore those containing: valid test sprs
 869     for fname in glob_valid_csvs(pth):
 870         svp64_csv = svt.get_svp64_csv(fname)
 871
 872     csvcols = ['insn', 'mode', 'Ptype', 'Etype', 'SM']
 873     csvcols += ['in1', 'in2', 'in3', 'out', 'out2', 'CR in', 'CR out']
 874
 875     if format is Format.VHDL:
 876         # and a nice microwatt VHDL file
 877         file_path = find_wiki_file("sv_decode.vhdl")
 878     elif format is Format.BINUTILS:
 879         file_path = find_wiki_file("binutils.c")
 880
 881     with open(file_path, 'w') as stream:
 882         output(format, svt, csvcols, insns, csvs_svp64, stream)
 883
 884
 885 def output_autogen_disclaimer(format, stream):
 886     lines = (
 887         "this file is auto-generated, do not edit",
 888         "http://libre-soc.org/openpower/sv_analysis.py",
 889         "part of Libre-SOC, sponsored by NLnet",
 890     )
 891     for line in format.wrap_comment(lines):
 892         stream.write(line)
 893         stream.write("\n")
 894     stream.write("\n")
 895
 896
 897 def output(format, svt, csvcols, insns, csvs_svp64, stream):
 898     lens = {
 899         'major': 63,
 900         'minor_4': 63,
 901         'minor_19': 7,
 902         'minor_30': 15,
 903         'minor_31': 1023,
 904         'minor_58': 63,
 905         'minor_59': 31,
 906         'minor_62': 63,
 907         'minor_63l': 511,
 908         'minor_63h': 16,
 909     }
 910
 911     def svp64_canonicalize(item):
 912         (value, csv) = item
 913         value = value.lower().replace("-", "_")
 914         return (value, csv)
 915
 916     csvs_svp64_canon = dict(map(svp64_canonicalize, csvs_svp64.items()))
 917
 918     # disclaimer
 919     output_autogen_disclaimer(format, stream)
 920
 921     # declarations
 922     for line in format.declarations(csvs_svp64_canon.keys(), lens):
 923         stream.write(f"{line}\n")
 924
 925     # definitions
 926     sv_cols = ['sv_in1', 'sv_in2', 'sv_in3', 'sv_out', 'sv_out2',
 927                'sv_cr_in', 'sv_cr_out']
 928     fullcols = csvcols + sv_cols
 929
 930     entries_svp64 = defaultdict(list)
 931     for (value, csv) in filter(lambda kv: kv[0] in lens, csvs_svp64_canon.items()):
 932         for entry in csv:
 933             insn = str(entry['insn'])
 934             condition = str(entry['CONDITIONS'])
 935             mode = str(entry['mode'])
 936             sventry = svt.svp64_instrs.get(insn, None)
 937             if sventry is not None:
 938                 sventry['mode'] = mode
 939             op = insns[(insn, condition)]['opcode']
 940             # binary-to-vhdl-binary
 941             if op.startswith("0b"):
 942                 op = "2#%s#" % op[2:]
 943             row = []
 944             for colname in csvcols[1:]:
 945                 re = entry[colname]
 946                 # zero replace with NONE
 947                 if re == '0':
 948                     re = 'NONE'
 949                 # 1/2 predication
 950                 re = re.replace("1P", "P1")
 951                 re = re.replace("2P", "P2")
 952                 row.append(re)
 953             #print("sventry", sventry)
 954             for colname in sv_cols:
 955                 if sventry is None:
 956                     re = 'NONE'
 957                 else:
 958                     re = sventry[colname]
 959                 row.append(re)
 960             entries_svp64[value].append((op, insn, row))
 961
 962     for line in format.definitions(entries_svp64, fullcols):
 963         stream.write(f"{line}\n")
 964
 965
 966 def main():
 967     import os
 968     os.environ['SILENCELOG'] = '1'
 969     parser = argparse.ArgumentParser()
 970     parser.add_argument("-f", "--format",
 971                         type=Format, choices=Format, default=Format.VHDL,
 972                         help="format to be used (binutils or VHDL)")
 973     args = parser.parse_args()
 974     process_csvs(args.format)
 975
 976
 977 if __name__ == '__main__':
 978     # don't do anything other than call main() here, cuz this code is bypassed
 979     # by the sv_analysis command created by setup.py
 980     main()