src/openpower/sv/sv_analysis.py

   1 #!/usr/bin/env python2
   2 #
   3 # NOTE that this program is python2 compatible, please do not stop it
   4 # from working by adding syntax that prevents that.
   5 #
   6 # Initial version written by lkcl Oct 2020
   7 # This program analyses the Power 9 op codes and looks at in/out register uses
   8 # The results are displayed:
   9 #       https://libre-soc.org/openpower/opcode_regs_deduped/
  10 #
  11 # It finds .csv files in the directory isatables/
  12 # then goes through the categories and creates svp64 CSV augmentation
  13 # tables on a per-opcode basis
  14 #
  15 # NOTE: this program is effectively part of the Simple-V Specification.
  16 # it encapsulates the relationships of what can be SVP64-encoded and
  17 # holds all of the information on how to encode and decode SVP64.
  18 # By auto-generating tables that go into the Simple-V Specification
  19 # this program *is* the specification. do not be confused just because
  20 # it is in python: if you do not understand please ask questions and
  21 # help create patches with explanatory comments.
  22
  23 import argparse
  24 import csv
  25 import enum
  26 import os
  27 from os.path import dirname, join
  28 from glob import glob
  29 from collections import defaultdict
  30 from collections import OrderedDict
  31 from openpower.decoder.power_svp64 import SVP64RM
  32 from openpower.decoder.power_enums import find_wiki_file, get_csv
  33 from openpower.util import log
  34
  35
  36 # Ignore those containing: valid test sprs
  37 def glob_valid_csvs(root):
  38     def check_csv(fname):
  39         _, name = os.path.split(fname)
  40         if '-' in name:
  41             return False
  42         if 'valid' in fname:
  43             return False
  44         if 'test' in fname:
  45             return False
  46         if fname.endswith('insndb.csv'):
  47             return False
  48         if fname.endswith('sprs.csv'):
  49             return False
  50         if fname.endswith('minor_19_valid.csv'):
  51             return False
  52         if 'RM' in fname:
  53             return False
  54         return True
  55
  56     yield from filter(check_csv, glob(root))
  57
  58
  59 # Write an array of dictionaries to the CSV file name:
  60 def write_csv(name, items, headers):
  61     file_path = find_wiki_file(name)
  62     with open(file_path, 'w') as csvfile:
  63         writer = csv.DictWriter(csvfile, headers, lineterminator="\n")
  64         writer.writeheader()
  65         writer.writerows(items)
  66
  67 # This will return True if all values are true.
  68 # Not sure what this is about
  69
  70
  71 def blank_key(row):
  72     # for v in row.values():
  73     #    if 'SPR' in v: # skip all SPRs
  74     #        return True
  75     for v in row.values():
  76         if v:
  77             return False
  78     return True
  79
  80 # General purpose registers have names like: RA, RT, R1, ...
  81 # Floating point registers names like: FRT, FRA, FR1, ..., FRTp, ...
  82 # Return True if field is a register
  83
  84
  85 def isreg(field):
  86     return (field.startswith('R') or field.startswith('FR') or
  87             field == 'SPR')
  88
  89
  90 # These are the attributes of the instructions,
  91 # register names
  92 keycolumns = ['unit', 'in1', 'in2', 'in3', 'out', 'CR in', 'CR out',
  93               ]  # don't think we need these: 'ldst len', 'rc', 'lk']
  94
  95 tablecols = ['unit', 'in', 'outcnt', 'CR in', 'CR out', 'imm'
  96              ]  # don't think we need these: 'ldst len', 'rc', 'lk']
  97
  98
  99 def create_key(row):
 100     """ create an equivalent of a database key by which it is possible
 101     to easily categorise an instruction.  later this category is used
 102     to decide what kind of EXTRA encoding is to be done because the
 103     key contains the total number of input and output registers
 104     """
 105     res = OrderedDict()
 106     #print ("row", row)
 107     for key in keycolumns:
 108         # registers IN - special-case: count number of regs RA/RB/RC/RS
 109         if key in ['in1', 'in2', 'in3']:
 110             if 'in' not in res:
 111                 res['in'] = 0
 112             if row['unit'] == 'BRANCH':  # branches must not include Vector SPRs
 113                 continue
 114             if isreg(row[key]):
 115                 res['in'] += 1
 116
 117         # registers OUT
 118         if key == 'out':
 119             # If upd is 1 then increment the count of outputs
 120             if 'outcnt' not in res:
 121                 res['outcnt'] = 0
 122             if isreg(row[key]):
 123                 res['outcnt'] += 1
 124             if row['upd'] == '1':
 125                 res['outcnt'] += 1
 126
 127         # CRs (Condition Register) (CR0 .. CR7)
 128         if key.startswith('CR'):
 129             if row[key].startswith('NONE'):
 130                 res[key] = '0'
 131             else:
 132                 res[key] = '1'
 133             if row['comment'].startswith('cr'):
 134                 res['crop'] = '1'
 135         # unit
 136         if key == 'unit':
 137             if row[key] == 'LDST':  # we care about LDST units
 138                 res[key] = row[key]
 139             else:
 140                 res[key] = 'OTHER'
 141         # LDST len (LoadStore length)
 142         if key.startswith('ldst'):
 143             if row[key].startswith('NONE'):
 144                 res[key] = '0'
 145             else:
 146                 res[key] = '1'
 147         # rc, lk
 148         if key in ['rc', 'lk']:
 149             if row[key] == 'ONE':
 150                 res[key] = '1'
 151             elif row[key] == 'NONE':
 152                 res[key] = '0'
 153             else:
 154                 res[key] = 'R'
 155         if key == 'lk':
 156             res[key] = row[key]
 157
 158     # Convert the numerics 'in' & 'outcnt' to strings
 159     res['in'] = str(res['in'])
 160     res['outcnt'] = str(res['outcnt'])
 161
 162     # constants
 163     if row['in2'].startswith('CONST_'):
 164         res['imm'] = "1"  # row['in2'].split("_")[1]
 165     else:
 166         res['imm'] = ''
 167
 168     return res
 169
 170 #
 171
 172
 173 def dformat(d):
 174     res = []
 175     for k, v in d.items():
 176         res.append("%s: %s" % (k, v))
 177     return ' '.join(res)
 178
 179
 180 def tformat(d):
 181     return "| " + ' | '.join(d) + " |"
 182
 183
 184 def keyname(row):
 185     """converts a key into a readable string. anything null or zero
 186     is skipped, shortening the readable string
 187     """
 188     res = []
 189     if row['unit'] != 'OTHER':
 190         res.append(row['unit'])
 191     if row['in'] != '0':
 192         res.append('%sR' % row['in'])
 193     if row['outcnt'] != '0':
 194         res.append('%sW' % row['outcnt'])
 195     if row['CR in'] == '1' and row['CR out'] == '1':
 196         if 'crop' in row:
 197             res.append("CR=2R1W")
 198         else:
 199             res.append("CRio")
 200     elif row['CR in'] == '1':
 201         res.append("CRi")
 202     elif row['CR out'] == '1':
 203         res.append("CRo")
 204     elif 'imm' in row and row['imm']:
 205         res.append("imm")
 206     return '-'.join(res)
 207
 208
 209 class Format(enum.Enum):
 210     BINUTILS = enum.auto()
 211     VHDL = enum.auto()
 212
 213     @classmethod
 214     def _missing_(cls, value):
 215         return {
 216             "binutils": Format.BINUTILS,
 217             "vhdl": Format.VHDL,
 218         }[value.lower()]
 219
 220     def __str__(self):
 221         return self.name.lower()
 222
 223     def declarations(self, values, lens):
 224         def declaration_binutils(value, width):
 225             yield f"/* TODO: implement binutils declaration (value={value!r}, width={width!r}) */"
 226
 227         def declaration_vhdl(value, width):
 228             yield f"    type sv_{value}_rom_array_t is " \
 229                 f"array(0 to {width}) of sv_decode_rom_t;"
 230
 231         for value in values:
 232             if value not in lens:
 233                 todo = [f"TODO {value} (or no SVP64 augmentation)"]
 234                 todo = self.wrap_comment(todo)
 235                 yield from map(lambda line: f"    {line}", todo)
 236             else:
 237                 width = lens[value]
 238                 yield from {
 239                     Format.BINUTILS: declaration_binutils,
 240                     Format.VHDL: declaration_vhdl,
 241                 }[self](value, width)
 242
 243     def definitions(self, entries_svp64, fullcols):
 244         def definitions_vhdl():
 245             for (value, entries) in entries_svp64.items():
 246                 yield ""
 247                 yield f"    constant sv_{value}_decode_rom_array :"
 248                 yield f"             sv_{value}_rom_array_t := ("
 249                 yield f"        -- {'  '.join(fullcols)}"
 250
 251                 for (op, insn, row) in entries:
 252                     yield f"    {op:>13} => ({', '.join(row)}), -- {insn}"
 253
 254                 yield f"    {'others':>13} => sv_illegal_inst"
 255                 yield "    );"
 256                 yield ""
 257
 258         def definitions_binutils():
 259             yield f"/* TODO: implement binutils definitions */"
 260
 261         yield from {
 262             Format.BINUTILS: definitions_binutils,
 263             Format.VHDL: definitions_vhdl,
 264         }[self]()
 265
 266     def wrap_comment(self, lines):
 267         def wrap_comment_binutils(lines):
 268             lines = tuple(lines)
 269             if len(lines) == 1:
 270                 yield f"/* {lines[0]} */"
 271             else:
 272                 yield "/*"
 273                 yield from map(lambda line: f" * {line}", lines)
 274                 yield " */"
 275
 276         def wrap_comment_vhdl(lines):
 277             yield from map(lambda line: f"-- {line}", lines)
 278
 279         yield from {
 280             Format.BINUTILS: wrap_comment_binutils,
 281             Format.VHDL: wrap_comment_vhdl,
 282         }[self](lines)
 283
 284
 285 def read_csvs():
 286     csvs = {}
 287     csvs_svp64 = {}
 288     bykey = {}
 289     primarykeys = set()
 290     dictkeys = OrderedDict()
 291     immediates = {}
 292     insns = {}  # dictionary of CSV row, by instruction
 293     insn_to_csv = {}
 294
 295     # Expand that (all .csv files)
 296     pth = find_wiki_file("*.csv")
 297
 298     # Ignore those containing: valid test sprs
 299     for fname in glob_valid_csvs(pth):
 300         csvname = os.path.split(fname)[1]
 301         csvname_ = csvname.split(".")[0]
 302         # csvname is something like: minor_59.csv, fname the whole path
 303         csv = get_csv(fname)
 304         csvs[fname] = csv
 305         csvs_svp64[csvname_] = []
 306         for row in csv:
 307             if blank_key(row):
 308                 continue
 309             #print("row", row)
 310             insn_name = row['comment']
 311             condition = row['CONDITIONS']
 312             # skip instructions that are not suitable
 313             if insn_name.startswith("l") and insn_name.endswith("br"):
 314                 continue  # skip pseudo-alias lxxxbr
 315             if insn_name in ['mcrxr', 'mcrxrx', 'darn']:
 316                 continue
 317             if insn_name in ['bctar', 'bcctr']:
 318                 continue
 319             if 'rfid' in insn_name:
 320                 continue
 321             if insn_name in ['setvl', ]:  # SVP64 opcodes
 322                 continue
 323
 324             insns[(insn_name, condition)] = row  # accumulate csv data
 325             insn_to_csv[insn_name] = csvname_  # CSV file name by instruction
 326             dkey = create_key(row)
 327             key = tuple(dkey.values())
 328             #print("key=", key, dkey)
 329             dictkeys[key] = dkey
 330             primarykeys.add(key)
 331             if key not in bykey:
 332                 bykey[key] = []
 333             bykey[key].append((csvname, row['opcode'], insn_name, condition,
 334                                row['form'].upper() + '-Form'))
 335
 336             # detect immediates, collate them (useful info)
 337             if row['in2'].startswith('CONST_'):
 338                 imm = row['in2'].split("_")[1]
 339                 if key not in immediates:
 340                     immediates[key] = set()
 341                 immediates[key].add(imm)
 342
 343     primarykeys = list(primarykeys)
 344     primarykeys.sort()
 345
 346     return (csvs, csvs_svp64, primarykeys, bykey, insn_to_csv, insns,
 347            dictkeys, immediates)
 348
 349
 350 def regs_profile(insn, res):
 351     """get a more detailed register profile: 1st operand is RA,
 352     2nd is RB, etc. etc
 353     """
 354     regs = []
 355     for k in ['in1', 'in2', 'in3', 'out', 'CR in', 'CR out']:
 356         if insn[k].startswith('CONST'):
 357             res[k] = ''
 358             regs.append('')
 359         else:
 360             res[k] = insn[k]
 361             if insn[k] == 'RA_OR_ZERO':
 362                 regs.append('RA')
 363             elif insn[k] != 'NONE':
 364                 regs.append(insn[k])
 365             else:
 366                 regs.append('')
 367     return regs
 368
 369
 370 def extra_classifier(insn_name, value, name, res, regs):
 371     """extra_classifier: creates the SVP64.RM EXTRA2/3 classification.
 372     there is very little space (9 bits) to mark register operands
 373     (RT RA RB, BA BB, BFA, FRS etc.) with the "extra" information
 374     needed to tell if *EACH* operand (of which there can be up to five!)
 375     is Vectorised, and whether its numbering is extended into the
 376     0..127 range rather than the limited 3/5 bit of Scalar v3.0 Power ISA.
 377
 378     thus begins the rather tedious but by-rote examination of EVERY
 379     Scalar instruction, working out how best to tell a decoder how to
 380     extend the registers.  EXTRA2 can have up to 4 slots (of 2 bit each)
 381     where due to RM.EXTRA being 9 bits, EXTRA3 can have up to 3 slots
 382     (of 3 bit each).  the index REGNAME says which slot the register
 383     named REGNAME must read its decoding from.  d: means destination,
 384     s: means source.  some are *shared slots* especially LDST update.
 385     some Rc=1 ops have the CR0/CR1 as a co-result which is also
 386     obviously Vectorised if the result is Vectorised.
 387
 388     it is actually quite straightforward but the sheer quantity of
 389     Scalar Power ISA instructions made it prudent to do this in an
 390     intelligent way, almost by-rote, by analysing the register profiles.
 391     """
 392     # for LD/ST FP, use FRT/FRS not RT/RS, and use CR1 not CR0
 393     if insn_name.startswith("lf"):
 394         dRT = 'd:FRT'
 395         dCR = 'd:CR1'
 396     else:
 397         dRT = 'd:RT'
 398         dCR = 'd:CR0'
 399     if insn_name.startswith("stf"):
 400         sRS = 's:FRS'
 401         dCR = 'd:CR1'
 402     else:
 403         sRS = 's:RS'
 404         dCR = 'd:CR0'
 405
 406     # sigh now the fun begins.  this isn't the sanest way to do it
 407     # but the patterns are pretty regular.  we start with the "profile"
 408     # because that determines how much space is available (total num
 409     # regs to decode) then if necessary begin apecialising either
 410     # by the instruction name or through more detailed register
 411     # profiling. example:
 412     #     if regs == ['RA', '', '', 'RT', '', '']:
 413     # is in the order in1  in2  in3 out1 out2 Rc=1
 414
 415     #********
 416     # start with LD/ST
 417
 418     if value == 'LDSTRM-2P-1S1D':
 419         res['Etype'] = 'EXTRA3'  # RM EXTRA3 type
 420         res['0'] = dRT    # RT: Rdest_EXTRA3
 421         res['1'] = 's:RA'  # RA: Rsrc1_EXTRA3
 422
 423     elif value == 'LDSTRM-2P-1S2D':
 424         res['Etype'] = 'EXTRA2'  # RM EXTRA2 type
 425         res['0'] = dRT    # RT: Rdest_EXTRA3
 426         res['1'] = 'd:RA'  # RA: Rdest2_EXTRA2
 427         res['2'] = 's:RA'  # RA: Rsrc1_EXTRA2
 428
 429     elif value == 'LDSTRM-2P-2S':
 430         # stw, std, sth, stb
 431         res['Etype'] = 'EXTRA3'  # RM EXTRA3 type
 432         res['0'] = sRS    # RS: Rdest1_EXTRA3
 433         res['1'] = 's:RA'  # RA: Rsrc1_EXTRA3
 434
 435     elif value == 'LDSTRM-2P-2S1D':
 436         if 'st' in insn_name and 'x' not in insn_name:  # stwu/stbu etc
 437             res['Etype'] = 'EXTRA2'  # RM EXTRA2 type
 438             res['0'] = 'd:RA'  # RA: Rdest1_EXTRA2
 439             res['1'] = sRS    # RS: Rdsrc1_EXTRA2
 440             res['2'] = 's:RA'  # RA: Rsrc2_EXTRA2
 441         elif 'st' in insn_name and 'x' in insn_name:  # stwux
 442             res['Etype'] = 'EXTRA2'  # RM EXTRA2 type
 443             res['0'] = 'd:RA'  # RA: Rdest1_EXTRA2
 444             # RS: Rdest2_EXTRA2, RA: Rsrc1_EXTRA2
 445             res['1'] = "%s;%s" % (sRS, 's:RA')
 446             res['2'] = 's:RB'  # RB: Rsrc2_EXTRA2
 447         elif 'u' in insn_name:  # ldux etc.
 448             res['Etype'] = 'EXTRA2'  # RM EXTRA2 type
 449             res['0'] = dRT    # RT: Rdest1_EXTRA2
 450             res['1'] = 'd:RA'  # RA: Rdest2_EXTRA2
 451             res['2'] = 's:RB'  # RB: Rsrc1_EXTRA2
 452         else:
 453             res['Etype'] = 'EXTRA2'  # RM EXTRA2 type
 454             res['0'] = dRT     # RT: Rdest1_EXTRA2
 455             res['1'] = 's:RA'  # RA: Rsrc1_EXTRA2
 456             res['2'] = 's:RB'  # RB: Rsrc2_EXTRA2
 457
 458     elif value == 'LDSTRM-2P-3S':
 459         res['Etype'] = 'EXTRA2'  # RM EXTRA2 type
 460         if 'cx' in insn_name:
 461             res['0'] = "%s;%s" % (sRS, dCR) # RS: Rsrc1_EXTRA2 CR0: dest
 462         else:
 463             res['0'] = sRS  # RS: Rsrc1_EXTRA2
 464         res['1'] = 's:RA'  # RA: Rsrc2_EXTRA2
 465         res['2'] = 's:RB'  # RA: Rsrc3_EXTRA2
 466
 467     #**********
 468     # now begins,arithmetic
 469
 470     elif value == 'RM-2P-1S1D':
 471         res['Etype'] = 'EXTRA3'  # RM EXTRA3 type
 472         if insn_name == 'mtspr':
 473             res['0'] = 'd:SPR'  # SPR: Rdest1_EXTRA3
 474             res['1'] = 's:RS'  # RS: Rsrc1_EXTRA3
 475         elif insn_name == 'mfspr':
 476             res['0'] = 'd:RS'  # RS: Rdest1_EXTRA3
 477             res['1'] = 's:SPR'  # SPR: Rsrc1_EXTRA3
 478         elif name == 'CRio' and insn_name == 'mcrf':
 479             res['0'] = 'd:BF'  # BFA: Rdest1_EXTRA3
 480             res['1'] = 's:BFA'  # BFA: Rsrc1_EXTRA3
 481         elif 'mfcr' in insn_name or 'mfocrf' in insn_name:
 482             res['0'] = 'd:RT'  # RT: Rdest1_EXTRA3
 483             res['1'] = 's:CR'  # CR: Rsrc1_EXTRA3
 484         elif insn_name == 'setb':
 485             res['0'] = 'd:RT'  # RT: Rdest1_EXTRA3
 486             res['1'] = 's:BFA'  # BFA: Rsrc1_EXTRA3
 487         elif insn_name.startswith('cmp'):  # cmpi
 488             res['0'] = 'd:BF'  # BF: Rdest1_EXTRA3
 489             res['1'] = 's:RA'  # RA: Rsrc1_EXTRA3
 490         elif regs == ['RA', '', '', 'RT', '', '']:
 491             res['0'] = 'd:RT'  # RT: Rdest1_EXTRA3
 492             res['1'] = 's:RA'  # RA: Rsrc1_EXTRA3
 493         elif regs == ['RA', '', '', 'RT', '', 'CR0']:
 494             res['0'] = 'd:RT;d:CR0'  # RT,CR0: Rdest1_EXTRA3
 495             res['1'] = 's:RA'  # RA: Rsrc1_EXTRA3
 496         elif (regs == ['RS', '', '', 'RA', '', 'CR0'] or
 497               regs == ['', '', 'RS', 'RA', '', 'CR0']):
 498             res['0'] = 'd:RA;d:CR0'  # RA,CR0: Rdest1_EXTRA3
 499             res['1'] = 's:RS'  # RS: Rsrc1_EXTRA3
 500         elif regs == ['RS', '', '', 'RA', '', '']:
 501             res['0'] = 'd:RA'  # RA: Rdest1_EXTRA3
 502             res['1'] = 's:RS'  # RS: Rsrc1_EXTRA3
 503         elif regs == ['', 'FRB', '', 'FRT', '0', 'CR1']:
 504             res['0'] = 'd:FRT;d:CR1'  # FRT,CR1: Rdest1_EXTRA3
 505             res['1'] = 's:FRA'  # FRA: Rsrc1_EXTRA3
 506         elif regs == ['', 'FRB', '', '', '', 'CR1']:
 507             res['0'] = 'd:CR1'  # CR1: Rdest1_EXTRA3
 508             res['1'] = 's:FRB'  # FRA: Rsrc1_EXTRA3
 509         elif regs == ['', 'FRB', '', '', '', 'BF']:
 510             res['0'] = 'd:BF'  # BF: Rdest1_EXTRA3
 511             res['1'] = 's:FRB'  # FRA: Rsrc1_EXTRA3
 512         elif regs == ['', 'FRB', '', 'FRT', '', 'CR1']:
 513             res['0'] = 'd:FRT;d:CR1'  # FRT,CR1: Rdest1_EXTRA3
 514             res['1'] = 's:FRB'  # FRB: Rsrc1_EXTRA3
 515         elif insn_name.startswith('bc'):
 516             res['0'] = 'd:BI'  # BI: Rdest1_EXTRA3
 517             res['1'] = 's:BI'  # BI: Rsrc1_EXTRA3
 518         elif insn_name == 'fishmv':
 519             # an overwrite ibstruction
 520             res['0'] = 'd:FRS'  # FRS: Rdest1_EXTRA3
 521             res['1'] = 's:FRS'  # FRS: Rsrc1_EXTRA3
 522         else:
 523             res['0'] = 'TODO'
 524             print("regs TODO", insn_name, regs)
 525
 526     elif value == 'RM-1P-2S1D':
 527         res['Etype'] = 'EXTRA3'  # RM EXTRA3 type
 528         if insn_name.startswith('cr'):
 529             res['0'] = 'd:BT'  # BT: Rdest1_EXTRA3
 530             res['1'] = 's:BA'  # BA: Rsrc1_EXTRA3
 531             res['2'] = 's:BB'  # BB: Rsrc2_EXTRA3
 532         elif regs == ['FRA', '', 'FRC', 'FRT', '', 'CR1']:
 533             res['0'] = 'd:FRT;d:CR1'  # FRT,CR1: Rdest1_EXTRA3
 534             res['1'] = 's:FRA'  # FRA: Rsrc1_EXTRA3
 535             res['2'] = 's:FRC'  # FRC: Rsrc1_EXTRA3
 536         # should be for fcmp
 537         elif regs == ['FRA', 'FRB', '', '', '', 'BF']:
 538             res['0'] = 'd:BF'  # BF: Rdest1_EXTRA3
 539             res['1'] = 's:FRA'  # FRA: Rsrc1_EXTRA3
 540             res['2'] = 's:FRB'  # FRB: Rsrc1_EXTRA3
 541         elif regs == ['FRA', 'FRB', '', 'FRT', '', '']:
 542             res['0'] = 'd:FRT'  # FRT: Rdest1_EXTRA3
 543             res['1'] = 's:FRA'  # FRA: Rsrc1_EXTRA3
 544             res['2'] = 's:FRB'  # FRB: Rsrc1_EXTRA3
 545         elif regs == ['FRA', 'FRB', '', 'FRT', '', 'CR1']:
 546             res['0'] = 'd:FRT;d:CR1'  # FRT,CR1: Rdest1_EXTRA3
 547             res['1'] = 's:FRA'  # FRA: Rsrc1_EXTRA3
 548             res['2'] = 's:FRB'  # FRB: Rsrc1_EXTRA3
 549         elif name == '2R-1W' or insn_name == 'cmpb':  # cmpb
 550             if insn_name in ['bpermd', 'cmpb']:
 551                 res['0'] = 'd:RA'  # RA: Rdest1_EXTRA3
 552                 res['1'] = 's:RS'  # RS: Rsrc1_EXTRA3
 553             else:
 554                 res['0'] = 'd:RT'  # RT: Rdest1_EXTRA3
 555                 res['1'] = 's:RA'  # RA: Rsrc1_EXTRA3
 556             res['2'] = 's:RB'  # RB: Rsrc1_EXTRA3
 557         elif insn_name.startswith('cmp'):  # cmp
 558             res['0'] = 'd:BF'  # BF: Rdest1_EXTRA3
 559             res['1'] = 's:RA'  # RA: Rsrc1_EXTRA3
 560             res['2'] = 's:RB'  # RB: Rsrc1_EXTRA3
 561         elif (regs == ['', 'RB', 'RS', 'RA', '', 'CR0'] or
 562               regs == ['RS', 'RB', '', 'RA', '', 'CR0']):
 563             res['0'] = 'd:RA;d:CR0'  # RA,CR0: Rdest1_EXTRA3
 564             res['1'] = 's:RB'  # RB: Rsrc1_EXTRA3
 565             res['2'] = 's:RS'  # RS: Rsrc1_EXTRA3
 566         elif regs == ['RA', 'RB', '', 'RT', '', 'CR0']:
 567             res['0'] = 'd:RT;d:CR0'  # RT,CR0: Rdest1_EXTRA3
 568             res['1'] = 's:RA'  # RA: Rsrc1_EXTRA3
 569             res['2'] = 's:RB'  # RB: Rsrc1_EXTRA3
 570         elif regs == ['RA', '', 'RS', 'RA', '', 'CR0']:
 571             res['0'] = 'd:RA;d:CR0'  # RA,CR0: Rdest1_EXTRA3
 572             res['1'] = 's:RA'  # RA: Rsrc1_EXTRA3
 573             res['2'] = 's:RS'  # RS: Rsrc1_EXTRA3
 574         else:
 575             res['0'] = 'TODO'
 576
 577     elif value == 'RM-2P-2S1D':
 578         res['Etype'] = 'EXTRA2'  # RM EXTRA2 type
 579         if insn_name.startswith('mt'):  # mtcrf
 580             res['0'] = 'd:CR'  # CR: Rdest1_EXTRA2
 581             res['1'] = 's:RS'  # RS: Rsrc1_EXTRA2
 582             res['2'] = 's:CR'  # CR: Rsrc2_EXTRA2
 583         else:
 584             res['0'] = 'TODO'
 585
 586     elif value == 'RM-1P-3S1D':
 587         res['Etype'] = 'EXTRA2'  # RM EXTRA2 type
 588         if regs == ['RA', 'RB', 'RT', 'RT', '', 'CR0']:
 589             res['0'] = 'd:RT;d:CR0'  # RT,CR0: Rdest1_EXTRA2
 590             res['1'] = 's:RA'  # RA: Rsrc1_EXTRA2
 591             res['2'] = 's:RB'  # RT: Rsrc2_EXTRA2
 592             res['3'] = 's:RT'  # RT: Rsrc3_EXTRA2
 593         elif insn_name == 'isel':
 594             res['0'] = 'd:RT'  # RT: Rdest1_EXTRA2
 595             res['1'] = 's:RA'  # RA: Rsrc1_EXTRA2
 596             res['2'] = 's:RB'  # RT: Rsrc2_EXTRA2
 597             res['3'] = 's:BC'  # BC: Rsrc3_EXTRA2
 598         else:
 599             res['0'] = 'd:FRT;d:CR1'  # FRT, CR1: Rdest1_EXTRA2
 600             res['1'] = 's:FRA'  # FRA: Rsrc1_EXTRA2
 601             res['2'] = 's:FRB'  # FRB: Rsrc2_EXTRA2
 602             res['3'] = 's:FRC'  # FRC: Rsrc3_EXTRA2
 603
 604     elif value == 'RM-1P-1D':
 605         res['Etype'] = 'EXTRA3'  # RM EXTRA3 type
 606         if insn_name == 'svstep':
 607             res['0'] = 'd:RT;d:CR0'  # RT,CR0: Rdest1_EXTRA3
 608         if insn_name == 'fmvis':
 609             res['0'] = 'd:FRS'  # FRS: Rdest1_EXTRA3
 610
 611
 612 def process_csvs(format):
 613
 614     print("# Draft SVP64 Power ISA register 'profile's")
 615     print('')
 616     print("this page is auto-generated, do not edit")
 617     print("created by http://libre-soc.org/openpower/sv_analysis.py")
 618     print('')
 619
 620     (csvs, csvs_svp64, primarykeys, bykey, insn_to_csv, insns,
 621            dictkeys, immediates) = read_csvs()
 622
 623     # mapping to old SVPrefix "Forms"
 624     mapsto = {'3R-1W-CRo': 'RM-1P-3S1D',
 625               '2R-1W-CRio': 'RM-1P-2S1D',
 626               '2R-1W-CRi': 'RM-1P-3S1D',
 627               '2R-1W-CRo': 'RM-1P-2S1D',
 628               '2R': 'non-SV',
 629               '2R-1W': 'RM-1P-2S1D',
 630               '1R-CRio': 'RM-2P-2S1D',
 631               '2R-CRio': 'RM-1P-2S1D',
 632               '2R-CRo': 'RM-1P-2S1D',
 633               '1R': 'non-SV',
 634               '1R-1W-CRio': 'RM-2P-1S1D',
 635               '1R-1W-CRo': 'RM-2P-1S1D',
 636               '1R-1W': 'RM-2P-1S1D',
 637               '1R-1W-imm': 'RM-2P-1S1D',
 638               '1R-CRo': 'RM-2P-1S1D',
 639               '1R-imm': 'RM-1P-1S',
 640               '1W-CRo': 'RM-1P-1D',
 641               '1W': 'non-SV',
 642               '1W-imm': 'RM-1P-1D',
 643               '1W-CRi': 'RM-2P-1S1D',
 644               'CRio': 'RM-2P-1S1D',
 645               'CR=2R1W': 'RM-1P-2S1D',
 646               'CRi': 'non-SV',
 647               'imm': 'non-SV',
 648               '': 'non-SV',
 649               'LDST-2R-imm': 'LDSTRM-2P-2S',
 650               'LDST-2R-1W-imm': 'LDSTRM-2P-2S1D',
 651               'LDST-2R-1W': 'LDSTRM-2P-2S1D',
 652               'LDST-2R-2W': 'LDSTRM-2P-2S1D',
 653               'LDST-1R-1W-imm': 'LDSTRM-2P-1S1D',
 654               'LDST-1R-2W-imm': 'LDSTRM-2P-1S2D',
 655               'LDST-3R': 'LDSTRM-2P-3S',
 656               'LDST-3R-CRo': 'LDSTRM-2P-3S',  # st*x
 657               'LDST-3R-1W': 'LDSTRM-2P-2S1D',  # st*x
 658               }
 659     print("# map to old SV Prefix")
 660     print('')
 661     print('|internal key | public name |')
 662     print('|-----        | ----------  |')
 663     for key in primarykeys:
 664         name = keyname(dictkeys[key])
 665         value = mapsto.get(name, "-")
 666         print(tformat([name, value + " "]))
 667     print('')
 668     print('')
 669
 670     print("# keys")
 671     print('')
 672     print(tformat(tablecols) + " imms | name |")
 673     print(tformat([" - "] * (len(tablecols)+2)))
 674
 675     # print out the keys and the table from which they're derived
 676     for key in primarykeys:
 677         name = keyname(dictkeys[key])
 678         row = tformat(dictkeys[key].values())
 679         imms = list(immediates.get(key, ""))
 680         imms.sort()
 681         row += " %s | " % ("/".join(imms))
 682         row += " %s |" % name
 683         print(row)
 684     print('')
 685     print('')
 686
 687     # print out, by remap name, all the instructions under that category
 688     for key in primarykeys:
 689         name = keyname(dictkeys[key])
 690         value = mapsto.get(name, "-")
 691         print("## %s (%s)" % (name, value))
 692         print('')
 693         print(tformat(['CSV', 'opcode', 'asm', 'flags', 'form']))
 694         print(tformat(['---', '------', '---', '-----', '----']))
 695         rows = bykey[key]
 696         rows.sort()
 697         for row in rows:
 698             print(tformat(row))
 699         print('')
 700         print('')
 701
 702     # for fname, csv in csvs.items():
 703     #    print (fname)
 704
 705     # for insn, row in insns.items():
 706     #    print (insn, row)
 707
 708     print("# svp64 remaps")
 709     svp64 = OrderedDict()
 710     # create a CSV file, per category, with SV "augmentation" info
 711     # XXX note: 'out2' not added here, needs to be added to CSV files
 712     # KEEP TRACK OF THESE https://bugs.libre-soc.org/show_bug.cgi?id=619
 713     csvcols = ['insn', 'mode', 'CONDITIONS', 'Ptype', 'Etype',]
 714     csvcols += ['0', '1', '2', '3']
 715     csvcols += ['in1', 'in2', 'in3', 'out', 'CR in', 'CR out']  # temporary
 716     for key in primarykeys:
 717         # get the decoded key containing row-analysis, and name/value
 718         dkey = dictkeys[key]
 719         name = keyname(dkey)
 720         value = mapsto.get(name, "-")
 721         if value == 'non-SV':
 722             continue
 723
 724         # print out svp64 tables by category
 725         print("* **%s**: %s" % (name, value))
 726
 727         # store csv entries by svp64 RM category
 728         if value not in svp64:
 729             svp64[value] = []
 730
 731         rows = bykey[key]
 732         rows.sort()
 733
 734         for row in rows:
 735             # for idx in range(len(row)):
 736             #    if row[idx] == 'NONE':
 737             #        row[idx] = ''
 738             # get the instruction
 739             #print(key, row)
 740             insn_name = row[2]
 741             condition = row[3]
 742             insn = insns[(insn_name, condition)]
 743
 744             # start constructing svp64 CSV row
 745             res = OrderedDict()
 746             res['insn'] = insn_name
 747             res['CONDITIONS'] = condition
 748             res['Ptype'] = value.split('-')[1]  # predication type (RM-xN-xxx)
 749             # get whether R_xxx_EXTRAn fields are 2-bit or 3-bit
 750             res['Etype'] = 'EXTRA2'
 751             # go through each register matching to Rxxxx_EXTRAx
 752             for k in ['0', '1', '2', '3']:
 753                 res[k] = ''
 754             # create "fake" out2 (TODO, needs to be added to CSV files)
 755             # KEEP TRACK HERE https://bugs.libre-soc.org/show_bug.cgi?id=619
 756             res['out2'] = 'NONE'
 757             if insn['upd'] == '1':  # LD/ST with update has RA as out2
 758                 res['out2'] = 'RA'
 759
 760             # set the SVP64 mode to NORMAL, LDST, BRANCH or CR
 761             crops = ['mfcr', 'mfocrf', 'mtcrf', 'mtocrf',
 762                     ]
 763             mode = 'NORMAL'
 764             if value.startswith('LDST'):
 765                 mode = 'LDST'
 766             elif insn_name.startswith('bc'):
 767                 mode = 'BRANCH'
 768             elif insn_name.startswith('cr') or insn_name in crops:
 769                 mode = 'CROP'
 770             res['mode'] = mode
 771
 772             # create a register profile list (update res row as well)
 773             regs = regs_profile(insn, res)
 774
 775             #print("regs", insn_name, regs)
 776             extra_classifier(insn_name, value, name, res, regs)
 777
 778             # add to svp64 csvs
 779             # for k in ['in1', 'in2', 'in3', 'out', 'CR in', 'CR out']:
 780             #    del res[k]
 781             # if res['0'] != 'TODO':
 782             for k in res:
 783                 if k == 'CONDITIONS':
 784                     continue
 785                 if res[k] == 'NONE' or res[k] == '':
 786                     res[k] = '0'
 787             svp64[value].append(res)
 788             # also add to by-CSV version
 789             csv_fname = insn_to_csv[insn_name]
 790             csvs_svp64[csv_fname].append(res)
 791
 792     print('')
 793
 794     # now write out the csv files
 795     for value, csv in svp64.items():
 796         if value == '-':
 797             continue
 798             from time import sleep
 799             print ("WARNING, filename '-' should NOT exist. instrs missing")
 800             print ("TODO: fix this (and put in the bugreport number here)")
 801             sleep(2)
 802         # print out svp64 tables by category
 803         print("## %s" % value)
 804         print('')
 805         cols = csvcols + ['out2']
 806         print(tformat(cols))
 807         print(tformat([" - "] * (len(cols))))
 808         for d in csv:
 809             row = []
 810             for k in cols:
 811                 row.append(d[k])
 812             print(tformat(row))
 813         print('')
 814
 815         #csvcols = ['insn', 'Ptype', 'Etype', '0', '1', '2', '3']
 816         write_csv("%s.csv" % value, csv, csvcols + ['out2'])
 817
 818     # okaaay, now we re-read them back in for producing microwatt SV
 819
 820     # get SVP64 augmented CSV files
 821     svt = SVP64RM(microwatt_format=True)
 822     # Expand that (all .csv files)
 823     pth = find_wiki_file("*.csv")
 824
 825     # Ignore those containing: valid test sprs
 826     for fname in glob_valid_csvs(pth):
 827         svp64_csv = svt.get_svp64_csv(fname)
 828
 829     csvcols = ['insn', 'mode', 'Ptype', 'Etype']
 830     csvcols += ['in1', 'in2', 'in3', 'out', 'out2', 'CR in', 'CR out']
 831
 832     if format is Format.VHDL:
 833         # and a nice microwatt VHDL file
 834         file_path = find_wiki_file("sv_decode.vhdl")
 835     elif format is Format.BINUTILS:
 836         file_path = find_wiki_file("binutils.c")
 837
 838     with open(file_path, 'w') as stream:
 839         output(format, svt, csvcols, insns, csvs_svp64, stream)
 840
 841
 842 def output_autogen_disclaimer(format, stream):
 843     lines = (
 844         "this file is auto-generated, do not edit",
 845         "http://libre-soc.org/openpower/sv_analysis.py",
 846         "part of Libre-SOC, sponsored by NLnet",
 847     )
 848     for line in format.wrap_comment(lines):
 849         stream.write(line)
 850         stream.write("\n")
 851     stream.write("\n")
 852
 853
 854 def output(format, svt, csvcols, insns, csvs_svp64, stream):
 855     lens = {
 856         'major': 63,
 857         'minor_4': 63,
 858         'minor_19': 7,
 859         'minor_30': 15,
 860         'minor_31': 1023,
 861         'minor_58': 63,
 862         'minor_59': 31,
 863         'minor_62': 63,
 864         'minor_63l': 511,
 865         'minor_63h': 16,
 866     }
 867
 868     def svp64_canonicalize(item):
 869         (value, csv) = item
 870         value = value.lower().replace("-", "_")
 871         return (value, csv)
 872
 873     csvs_svp64_canon = dict(map(svp64_canonicalize, csvs_svp64.items()))
 874
 875     # disclaimer
 876     output_autogen_disclaimer(format, stream)
 877
 878     # declarations
 879     for line in format.declarations(csvs_svp64_canon.keys(), lens):
 880         stream.write(f"{line}\n")
 881
 882     # definitions
 883     sv_cols = ['sv_in1', 'sv_in2', 'sv_in3', 'sv_out', 'sv_out2',
 884                'sv_cr_in', 'sv_cr_out']
 885     fullcols = csvcols + sv_cols
 886
 887     entries_svp64 = defaultdict(list)
 888     for (value, csv) in filter(lambda kv: kv[0] in lens, csvs_svp64_canon.items()):
 889         for entry in csv:
 890             insn = str(entry['insn'])
 891             condition = str(entry['CONDITIONS'])
 892             mode = str(entry['mode'])
 893             sventry = svt.svp64_instrs.get(insn, None)
 894             if sventry is not None:
 895                 sventry['mode'] = mode
 896             op = insns[(insn, condition)]['opcode']
 897             # binary-to-vhdl-binary
 898             if op.startswith("0b"):
 899                 op = "2#%s#" % op[2:]
 900             row = []
 901             for colname in csvcols[1:]:
 902                 re = entry[colname]
 903                 # zero replace with NONE
 904                 if re == '0':
 905                     re = 'NONE'
 906                 # 1/2 predication
 907                 re = re.replace("1P", "P1")
 908                 re = re.replace("2P", "P2")
 909                 row.append(re)
 910             #print("sventry", sventry)
 911             for colname in sv_cols:
 912                 if sventry is None:
 913                     re = 'NONE'
 914                 else:
 915                     re = sventry[colname]
 916                 row.append(re)
 917             entries_svp64[value].append((op, insn, row))
 918
 919     for line in format.definitions(entries_svp64, fullcols):
 920         stream.write(f"{line}\n")
 921
 922
 923 def main():
 924     import os
 925     os.environ['SILENCELOG'] = '1'
 926     parser = argparse.ArgumentParser()
 927     parser.add_argument("-f", "--format",
 928                         type=Format, choices=Format, default=Format.VHDL,
 929                         help="format to be used (binutils or VHDL)")
 930     args = parser.parse_args()
 931     process_csvs(args.format)
 932
 933
 934 if __name__ == '__main__':
 935     # don't do anything other than call main() here, cuz this code is bypassed
 936     # by the sv_analysis command created by setup.py
 937     main()