src/openpower/sv/svp64.py

   1 # SPDX-License-Identifier: LGPLv3+
   2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3 # Funded by NLnet http://nlnet.nl
   4 """SVP64 Data Structures
   5
   6 For full spec see https://libre-soc.org/openpower/sv/
   7 """
   8
   9 from nmigen import Record
  10
  11
  12 # in nMigen, Record begins at the LSB and fills upwards
  13 # however in OpenPOWER, numbering is MSB0.  sigh.
  14 class SVP64Rec(Record):
  15     """SVP64 RM (Remap) Record.
  16
  17     https://libre-soc.org/openpower/sv/svp64/
  18
  19     | Field Name  | Field bits | Description                            |
  20     |-------------|------------|----------------------------------------|
  21     | MASKMODE    | `0`        | Execution (predication) Mask Kind      |
  22     | MASK        | `1:3`      | Execution Mask                         |
  23     | ELWIDTH     | `4:5`      | Element Width                          |
  24     | ELWIDTH_SRC | `6:7`      | Element Width for Source               |
  25     | SUBVL       | `8:9`      | Sub-vector length                      |
  26     | EXTRA       | `10:18`    | context-dependent extra                |
  27     | MODE        | `19:23`    | changes Vector behaviour               |
  28     """
  29     def __init__(self, name=None):
  30         Record.__init__(self, layout=[("mode"    , 5),
  31                                       ("extra"   , 9),
  32                                       ("subvl"   , 2),
  33                                       ("ewsrc"   , 2),
  34                                       ("elwidth" , 2),
  35                                       ("mask"    , 3),
  36                                       ("mmode"   , 1)], name=name)
  37
  38     def ports(self):
  39         return [self.mmode, self.mask, self.elwidth, self.ewsrc,
  40                 self.subvl, self.extra, self.mode]
  41
  42
  43 options = {0b000: (0,1,2),
  44            0b001: (0,2,1),
  45            0b010: (1,0,2),
  46            0b011: (1,2,0),
  47            0b100: (2,0,1),
  48            0b101: (2,1,0)}
  49 roptions = {}
  50 for k, v in options.items():
  51     roptions[v] = k
  52
  53 # in nMigen, Record begins at the LSB and fills upwards
  54 # however in OpenPOWER, numbering is MSB0.  sigh.
  55 class SVP64REMAP(Record):
  56     layout=[("mode"    , 2),
  57             ("skip"    , 2),
  58             ("offset"  , 4),
  59             ("invxyz"  , 3),
  60             ("permute" , 3),
  61             ("zdimsz"  , 6),
  62             ("ydimsz"  , 6),
  63             ("xdimsz"  , 6)]
  64
  65     """SVP64 SHAPE (REMAP) Record.
  66
  67     https://libre-soc.org/openpower/sv/remap/
  68
  69     | Field Name | Field bits | Description                            |
  70     |------------|------------|----------------------------------------|
  71     | XDIMSZ     | `0:5`      | X Dimension size                       |
  72     | YDIMSZ     | `6:11`     | Y Dimension size                       |
  73     | ZDIMSZ     | `12:17`    | Z Dimension size                       |
  74     | PERMUTE    | `18:20`    | Permutation order (XYZ, XZY, YXZ...)   |
  75     | INVXYZ     | `21:23`    | Invert order of X or Y or Z            |
  76     | OFFSET     | `24:27`    | Adds to index after REMAP (offsets)    |
  77     | SKIP       | `28:29`    | Skips dimension numbered SKIP          |
  78     | MODE       | `30:31`    | Selects Mode: Matrix, FFT, DCT         |
  79     """
  80     def __init__(self, name=None):
  81         Record.__init__(self, layout=self.layout, name=name)
  82
  83     @staticmethod
  84     def order(permute):
  85         return options[permute]
  86
  87     @staticmethod
  88     def rorder(order):
  89         return roptions[tuple(order)]
  90
  91     def ports(self):
  92         return [self.mode, self.skip, self.offset, self.invxyz, self.permute,
  93                 self.zdimsz, self.ydimsz, self.xdimsz]
  94