src/openpower/sv/svp64.py

   1 # SPDX-License-Identifier: LGPLv3+
   2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3 # Funded by NLnet http://nlnet.nl
   4 """SVP64 Data Structures
   5
   6 For full spec see https://libre-soc.org/openpower/sv/
   7 """
   8
   9 from nmigen import Record
  10
  11 # in nMigen, Record begins at the LSB and fills upwards
  12 class SVP64Rec(Record):
  13     """SVP64 RM (Remap) Record.
  14
  15     https://libre-soc.org/openpower/sv/svp64/
  16
  17     | Field Name  | Field bits | Description                            |
  18     |-------------|------------|----------------------------------------|
  19     | MASKMODE    | `0`        | Execution (predication) Mask Kind      |
  20     | MASK        | `1:3`      | Execution Mask                         |
  21     | ELWIDTH     | `4:5`      | Element Width                          |
  22     | ELWIDTH_SRC | `6:7`      | Element Width for Source               |
  23     | SUBVL       | `8:9`      | Sub-vector length                      |
  24     | EXTRA       | `10:18`    | context-dependent extra                |
  25     | MODE        | `19:23`    | changes Vector behaviour               |
  26     """
  27     def __init__(self, name=None):
  28         Record.__init__(self, layout=[("mode"    , 5),
  29                                       ("extra"   , 9),
  30                                       ("subvl"   , 2),
  31                                       ("ewsrc"   , 2),
  32                                       ("elwidth" , 2),
  33                                       ("mask"    , 3),
  34                                       ("mmode"   , 1)], name=name)
  35
  36     def ports(self):
  37         return [self.mmode, self.mask, self.elwidth, self.ewsrc,
  38                 self.extra, self.mode]
  39