src/openpower/sv/svstate.py

   1 # SPDX-License-Identifier: LGPLv3+
   2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3 # Funded by NLnet http://nlnet.nl
   4 """SVSATE SPR Record.  actually a peer of PC (CIA/NIA) and MSR
   5
   6 https://libre-soc.org/openpower/sv/sprs/
   7
   8 | Field | Name     | Description           |
   9 | ----- | -------- | --------------------- |
  10 | 0:6   | maxvl    | Max Vector Length     |
  11 | 7:13  |    vl    | Vector Length         |
  12 | 14:20 | srcstep  | for srcstep = 0..VL-1 |
  13 | 21:27 | dststep  | for dststep = 0..VL-1 |
  14 | 28:29 | dsubstep | for dsubstep = 0..SUBVL-1  |
  15 | 30:31 | ssubstep | for ssubstep = 0..SUBVL-1  |
  16 | 32:33 | mi0      | REMAP RA SVSHAPE0-3    |
  17 | 34:35 | mi1      | REMAP RB SVSHAPE0-3    |
  18 | 36:37 | mi2      | REMAP RC SVSHAPE0-3    |
  19 | 38:39 | mo0      | REMAP RT SVSHAPE0-3    |
  20 | 40:41 | mo1      | REMAP EA SVSHAPE0-3    |
  21 | 42:46 | SVme     | REMAP enable (RA-RT)  |
  22 | 47:61 | rsvd     | reserved              |
  23 | 62    | RMpst    | REMAP persistence     |
  24 | 63    | vfirst   | Vertical First mode   |
  25 """
  26
  27 from nmigen import Signal, Record
  28
  29
  30 # In nMigen, Record order is from LSB to MSB
  31 # but Power ISA specs are all MSB to LSB (MSB0).
  32 class SVSTATERec(Record):
  33     layout = [("vfirst", 1),
  34             ("RMpst", 1),
  35             ("rsvd", 15),
  36             ("SVme", 5),
  37             ("mo1", 2),
  38             ("mo0", 2),
  39             ("mi2", 2),
  40             ("mi1", 2),
  41             ("mi0", 2),
  42             ("ssubstep", 2),
  43             ("dsubstep", 2),
  44             ("dststep", 7),
  45             ("srcstep", 7),
  46             ("vl", 7),
  47             ("maxvl", 7),
  48         ]
  49
  50     def __init__(self, name=None):
  51         super().__init__(name=name, layout=SVSTATERec.layout)