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sv_binutils: consider opcode whenever names match
[openpower-isa.git] / src / openpower / sv / trans / svp64.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Funded by NLnet http://nlnet.nl
4
5 """SVP64 OpenPOWER v3.0B assembly translator
6
7 This class takes raw svp64 assembly mnemonics (aliases excluded) and creates
8 an EXT001-encoded "svp64 prefix" (as a .long) followed by a v3.0B opcode.
9
10 It is very simple and straightforward, the only weirdness being the
11 extraction of the register information and conversion to v3.0B numbering.
12
13 Encoding format of svp64: https://libre-soc.org/openpower/sv/svp64/
14 Encoding format of LDST: https://libre-soc.org/openpower/sv/ldst/
15 Bugtracker: https://bugs.libre-soc.org/show_bug.cgi?id=578
16 """
17
18 import os
19 import sys
20 from collections import OrderedDict
21
22 from openpower.decoder.isa.caller import (SVP64PrefixFields, SV64P_MAJOR_SIZE,
23 SV64P_PID_SIZE, SVP64RMFields,
24 SVP64RM_EXTRA2_SPEC_SIZE,
25 SVP64RM_EXTRA3_SPEC_SIZE,
26 SVP64RM_MODE_SIZE, SVP64RM_SMASK_SIZE,
27 SVP64RM_MMODE_SIZE, SVP64RM_MASK_SIZE,
28 SVP64RM_SUBVL_SIZE, SVP64RM_EWSRC_SIZE,
29 SVP64RM_ELWIDTH_SIZE)
30 from openpower.decoder.pseudo.pagereader import ISA
31 from openpower.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra
32 from openpower.decoder.selectable_int import SelectableInt
33 from openpower.consts import SVP64MODE
34
35 # for debug logging
36 from openpower.util import log
37
38
39 # decode GPR into sv extra
40 def get_extra_gpr(etype, regmode, field):
41 if regmode == 'scalar':
42 # cut into 2-bits 5-bits SS FFFFF
43 sv_extra = field >> 5
44 field = field & 0b11111
45 else:
46 # cut into 5-bits 2-bits FFFFF SS
47 sv_extra = field & 0b11
48 field = field >> 2
49 return sv_extra, field
50
51
52 # decode 3-bit CR into sv extra
53 def get_extra_cr_3bit(etype, regmode, field):
54 if regmode == 'scalar':
55 # cut into 2-bits 3-bits SS FFF
56 sv_extra = field >> 3
57 field = field & 0b111
58 else:
59 # cut into 3-bits 4-bits FFF SSSS but will cut 2 zeros off later
60 sv_extra = field & 0b1111
61 field = field >> 4
62 return sv_extra, field
63
64
65 # decodes SUBVL
66 def decode_subvl(encoding):
67 pmap = {'2': 0b01, '3': 0b10, '4': 0b11}
68 assert encoding in pmap, \
69 "encoding %s for SUBVL not recognised" % encoding
70 return pmap[encoding]
71
72
73 # decodes elwidth
74 def decode_elwidth(encoding):
75 pmap = {'8': 0b11, '16': 0b10, '32': 0b01}
76 assert encoding in pmap, \
77 "encoding %s for elwidth not recognised" % encoding
78 return pmap[encoding]
79
80
81 # decodes predicate register encoding
82 def decode_predicate(encoding):
83 pmap = { # integer
84 '1<<r3': (0, 0b001),
85 'r3': (0, 0b010),
86 '~r3': (0, 0b011),
87 'r10': (0, 0b100),
88 '~r10': (0, 0b101),
89 'r30': (0, 0b110),
90 '~r30': (0, 0b111),
91 # CR
92 'lt': (1, 0b000),
93 'nl': (1, 0b001), 'ge': (1, 0b001), # same value
94 'gt': (1, 0b010),
95 'ng': (1, 0b011), 'le': (1, 0b011), # same value
96 'eq': (1, 0b100),
97 'ne': (1, 0b101),
98 'so': (1, 0b110), 'un': (1, 0b110), # same value
99 'ns': (1, 0b111), 'nu': (1, 0b111), # same value
100 }
101 assert encoding in pmap, \
102 "encoding %s for predicate not recognised" % encoding
103 return pmap[encoding]
104
105
106 # decodes "Mode" in similar way to BO field (supposed to, anyway)
107 def decode_bo(encoding):
108 pmap = { # TODO: double-check that these are the same as Branch BO
109 'lt': 0b000,
110 'nl': 0b001, 'ge': 0b001, # same value
111 'gt': 0b010,
112 'ng': 0b011, 'le': 0b011, # same value
113 'eq': 0b100,
114 'ne': 0b101,
115 'so': 0b110, 'un': 0b110, # same value
116 'ns': 0b111, 'nu': 0b111, # same value
117 }
118 assert encoding in pmap, \
119 "encoding %s for BO Mode not recognised" % encoding
120 return pmap[encoding]
121
122 # partial-decode fail-first mode
123
124
125 def decode_ffirst(encoding):
126 if encoding in ['RC1', '~RC1']:
127 return encoding
128 return decode_bo(encoding)
129
130
131 def decode_reg(field):
132 # decode the field number. "5.v" or "3.s" or "9"
133 field = field.split(".")
134 regmode = 'scalar' # default
135 if len(field) == 2:
136 if field[1] == 's':
137 regmode = 'scalar'
138 elif field[1] == 'v':
139 regmode = 'vector'
140 field = int(field[0]) # actual register number
141 return field, regmode
142
143
144 def decode_imm(field):
145 ldst_imm = "(" in field and field[-1] == ')'
146 if ldst_imm:
147 return field[:-1].split("(")
148 else:
149 return None, field
150
151
152 # decodes svp64 assembly listings and creates EXT001 svp64 prefixes
153 class SVP64Asm:
154 def __init__(self, lst, bigendian=False, macros=None):
155 if macros is None:
156 macros = {}
157 self.macros = macros
158 self.lst = lst
159 self.trans = self.translate(lst)
160 self.isa = ISA() # reads the v3.0B pseudo-code markdown files
161 self.svp64 = SVP64RM() # reads the svp64 Remap entries for registers
162 assert bigendian == False, "error, bigendian not supported yet"
163
164 def __iter__(self):
165 yield from self.trans
166
167 def translate_one(self, insn, macros=None):
168 if macros is None:
169 macros = {}
170 macros.update(self.macros)
171 isa = self.isa
172 svp64 = self.svp64
173 # find first space, to get opcode
174 ls = insn.split(' ')
175 opcode = ls[0]
176 # now find opcode fields
177 fields = ''.join(ls[1:]).split(',')
178 mfields = list(map(str.strip, fields))
179 log("opcode, fields", ls, opcode, mfields)
180 fields = []
181 # macro substitution
182 for field in mfields:
183 fields.append(macro_subst(macros, field))
184 log("opcode, fields substed", ls, opcode, fields)
185
186 # sigh have to do setvl here manually for now...
187 # note the subtract one from SVi.
188 if opcode in ["setvl", "setvl."]:
189 insn = 22 << (31-5) # opcode 22, bits 0-5
190 fields = list(map(int, fields))
191 insn |= fields[0] << (31-10) # RT , bits 6-10
192 insn |= fields[1] << (31-15) # RA , bits 11-15
193 insn |= (fields[2]-1) << (31-22) # SVi , bits 16-22
194 insn |= fields[3] << (31-25) # ms , bit 25
195 insn |= fields[4] << (31-24) # vs , bit 24
196 insn |= fields[5] << (31-23) # vf , bit 23
197 insn |= 0b00000 << (31-30) # XO , bits 26..30
198 if opcode == 'setvl.':
199 insn |= 1 << (31-31) # Rc=1 , bit 31
200 log("setvl", bin(insn))
201 yield ".long 0x%x" % insn
202 return
203
204 # sigh have to do setvl here manually for now...
205 # note the subtract one from SVi.
206 if opcode in ["svstep", "svstep."]:
207 insn = 22 << (31-5) # opcode 22, bits 0-5
208 fields = list(map(int, fields))
209 insn |= fields[0] << (31-10) # RT , bits 6-10
210 insn |= (fields[1]-1) << (31-22) # SVi , bits 16-22
211 insn |= fields[2] << (31-25) # vf , bit 25
212 insn |= 0b00011 << (31-30) # XO , bits 26..30
213 if opcode == 'svstep.':
214 insn |= 1 << (31-31) # Rc=1 , bit 31
215 log("svstep", bin(insn))
216 yield ".long 0x%x" % insn
217 return
218
219 # and svshape. note that the dimension fields one subtracted from each
220 if opcode == 'svshape':
221 insn = 22 << (31-5) # opcode 22, bits 0-5
222 fields = list(map(int, fields))
223 insn |= (fields[0]-1) << (31-10) # SVxd , bits 6-10
224 insn |= (fields[1]-1) << (31-15) # SVyd , bits 11-15
225 insn |= (fields[2]-1) << (31-20) # SVzd , bits 16-20
226 insn |= (fields[3]) << (31-24) # SVRM , bits 21-24
227 insn |= (fields[4]) << (31-25) # vf , bits 25
228 insn |= 0b00001 << (31-30) # XO , bits 26..30
229 #insn &= ((1<<32)-1)
230 log("svshape", bin(insn))
231 yield ".long 0x%x" % insn
232 return
233
234 # and svremap
235 if opcode == 'svremap':
236 insn = 22 << (31-5) # opcode 22, bits 0-5
237 fields = list(map(int, fields))
238 insn |= fields[0] << (31-10) # SVme , bits 6-10
239 insn |= fields[1] << (31-12) # mi0 , bits 11-12
240 insn |= fields[2] << (31-14) # mi1 , bits 13-14
241 insn |= fields[3] << (31-16) # mi2 , bits 15-16
242 insn |= fields[4] << (31-18) # m00 , bits 17-18
243 insn |= fields[5] << (31-20) # m01 , bits 19-20
244 insn |= fields[6] << (31-21) # m01 , bit 21
245 insn |= 0b00010 << (31-30) # XO , bits 26..30
246 #insn &= ((1<<32)-1)
247 log("svremap", bin(insn))
248 yield ".long 0x%x" % insn
249 return
250
251 # and fsins
252 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
253 # however we are out of space with opcode 22
254 if opcode.startswith('fsins'):
255 fields = list(map(int, fields))
256 insn = 59 << (31-5) # opcode 59, bits 0-5
257 insn |= fields[0] << (31-10) # RT , bits 6-10
258 insn |= fields[1] << (31-20) # RB , bits 16-20
259 insn |= 0b1000001110 << (31-30) # XO , bits 21..30
260 if opcode == 'fsins.':
261 insn |= 1 << (31-31) # Rc=1 , bit 31
262 log("fsins", bin(insn))
263 yield ".long 0x%x" % insn
264 return
265
266 # and fcoss
267 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
268 # however we are out of space with opcode 22
269 if opcode.startswith('fcoss'):
270 fields = list(map(int, fields))
271 insn = 59 << (31-5) # opcode 59, bits 0-5
272 insn |= fields[0] << (31-10) # RT , bits 6-10
273 insn |= fields[1] << (31-20) # RB , bits 16-20
274 insn |= 0b1000101110 << (31-30) # XO , bits 21..30
275 if opcode == 'fcoss.':
276 insn |= 1 << (31-31) # Rc=1 , bit 31
277 log("fcoss", bin(insn))
278 yield ".long 0x%x" % insn
279 return
280
281 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
282 # however we are out of space with opcode 22
283 if opcode == 'ternlogi':
284 po = 5
285 xo = 0
286 rt = int(fields[0])
287 ra = int(fields[1])
288 rb = int(fields[2])
289 imm = int(fields[3])
290 instr = po
291 instr = (instr << 5) | rt
292 instr = (instr << 5) | ra
293 instr = (instr << 5) | rb
294 instr = (instr << 8) | imm
295 instr = (instr << 3) | xo
296 asm = f"ternlogi {rt}, {ra}, {rb}, {imm}"
297 yield f".4byte {hex(instr)} # {asm}"
298 return
299
300 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
301 # however we are out of space with opcode 22
302 if opcode in ('grev', 'grevi', 'grevw', 'grevwi',
303 'grev.', 'grevi.', 'grevw.', 'grevwi.'):
304 po = 5
305 # _ matches fields in table at:
306 # https://libre-soc.org/openpower/sv/bitmanip/
307 xo = 0b1_0010_110
308 if 'w' in opcode:
309 xo |= 0b100_000
310 if 'i' in opcode:
311 xo |= 0b1000_000
312 Rc = 1 if '.' in opcode else 0
313 rt = int(fields[0])
314 ra = int(fields[1])
315 rb_imm = int(fields[2])
316 instr = po
317 instr = (instr << 5) | rt
318 instr = (instr << 5) | ra
319 if opcode == 'grevi' or opcode == 'grevi.':
320 assert 0 <= rb_imm < 64
321 instr = (instr << 6) | rb_imm
322 instr = (instr << 9) | xo
323 else:
324 assert 0 <= rb_imm < 32
325 instr = (instr << 5) | rb_imm
326 instr = (instr << 10) | xo
327 instr = (instr << 1) | Rc
328 asm = f"{opcode} {rt}, {ra}, {rb_imm}"
329 yield f".4byte {hex(instr)} # {asm}"
330 return
331
332 # identify if is a svp64 mnemonic
333 if not opcode.startswith('sv.'):
334 yield insn # unaltered
335 return
336 opcode = opcode[3:] # strip leading "sv"
337
338 # start working on decoding the svp64 op: sv.basev30Bop/vec2/mode
339 opmodes = opcode.split("/") # split at "/"
340 v30b_op = opmodes.pop(0) # first is the v3.0B
341 # check instruction ends with dot
342 rc_mode = v30b_op.endswith('.')
343 if rc_mode:
344 v30b_op = v30b_op[:-1]
345
346 # sigh again, have to recognised LD/ST bit-reverse instructions
347 # this has to be "processed" to fit into a v3.0B without the "sh"
348 # e.g. ldsh is actually ld
349 ldst_shift = v30b_op.startswith("l") and v30b_op.endswith("sh")
350
351 if v30b_op not in isa.instr:
352 raise Exception("opcode %s of '%s' not supported" %
353 (v30b_op, insn))
354
355 if ldst_shift:
356 # okaay we need to process the fields and make this:
357 # ldsh RT, SVD(RA), RC - 11 bits for SVD, 5 for RC
358 # into this:
359 # ld RT, D(RA) - 16 bits
360 # likewise same for SVDS (9 bits for SVDS, 5 for RC, 14 bits for DS)
361 form = isa.instr[v30b_op].form # get form (SVD-Form, SVDS-Form)
362
363 newfields = []
364 for field in fields:
365 # identify if this is a ld/st immediate(reg) thing
366 ldst_imm = "(" in field and field[-1] == ')'
367 if ldst_imm:
368 newfields.append(field[:-1].split("("))
369 else:
370 newfields.append(field)
371
372 immed, RA = newfields[1]
373 immed = int(immed)
374 RC = int(newfields.pop(2)) # better be an integer number!
375 if form == 'SVD': # 16 bit: immed 11 bits, RC shift up 11
376 immed = (immed & 0b11111111111) | (RC << 11)
377 if immed & (1 << 15): # should be negative
378 immed -= 1 << 16
379 if form == 'SVDS': # 14 bit: immed 9 bits, RC shift up 9
380 immed = (immed & 0b111111111) | (RC << 9)
381 if immed & (1 << 13): # should be negative
382 immed -= 1 << 14
383 newfields[1] = "%d(%s)" % (immed, RA)
384 fields = newfields
385
386 # and strip off "sh" from end, and add "sh" to opmodes, instead
387 v30b_op = v30b_op[:-2]
388 opmodes.append("sh")
389 log("rewritten", v30b_op, opmodes, fields)
390
391 if v30b_op not in svp64.instrs:
392 raise Exception("opcode %s of '%s' not an svp64 instruction" %
393 (v30b_op, insn))
394 v30b_regs = isa.instr[v30b_op].regs[0] # get regs info "RT, RA, RB"
395 rm = svp64.instrs[v30b_op] # one row of the svp64 RM CSV
396 log("v3.0B op", v30b_op, "Rc=1" if rc_mode else '')
397 log("v3.0B regs", opcode, v30b_regs)
398 log("RM", rm)
399
400 # right. the first thing to do is identify the ordering of
401 # the registers, by name. the EXTRA2/3 ordering is in
402 # rm['0']..rm['3'] but those fields contain the names RA, BB
403 # etc. we have to read the pseudocode to understand which
404 # reg is which in our instruction. sigh.
405
406 # first turn the svp64 rm into a "by name" dict, recording
407 # which position in the RM EXTRA it goes into
408 # also: record if the src or dest was a CR, for sanity-checking
409 # (elwidth overrides on CRs are banned)
410 decode = decode_extra(rm)
411 dest_reg_cr, src_reg_cr, svp64_src, svp64_dest = decode
412
413 log("EXTRA field index, src", svp64_src)
414 log("EXTRA field index, dest", svp64_dest)
415
416 # okaaay now we identify the field value (opcode N,N,N) with
417 # the pseudo-code info (opcode RT, RA, RB)
418 assert len(fields) == len(v30b_regs), \
419 "length of fields %s must match insn `%s` fields %s" % \
420 (str(v30b_regs), insn, str(fields))
421 opregfields = zip(fields, v30b_regs) # err that was easy
422
423 # now for each of those find its place in the EXTRA encoding
424 # note there is the possibility (for LD/ST-with-update) of
425 # RA occurring **TWICE**. to avoid it getting added to the
426 # v3.0B suffix twice, we spot it as a duplicate, here
427 extras = OrderedDict()
428 for idx, (field, regname) in enumerate(opregfields):
429 imm, regname = decode_imm(regname)
430 rtype = get_regtype(regname)
431 log(" idx find", rtype, idx, field, regname, imm)
432 if rtype is None:
433 # probably an immediate field, append it straight
434 extras[('imm', idx, False)] = (idx, field, None, None, None)
435 continue
436 extra = svp64_src.get(regname, None)
437 if extra is not None:
438 extra = ('s', extra, False) # not a duplicate
439 extras[extra] = (idx, field, regname, rtype, imm)
440 log(" idx src", idx, extra, extras[extra])
441 dextra = svp64_dest.get(regname, None)
442 log("regname in", regname, dextra)
443 if dextra is not None:
444 is_a_duplicate = extra is not None # duplicate spotted
445 dextra = ('d', dextra, is_a_duplicate)
446 extras[dextra] = (idx, field, regname, rtype, imm)
447 log(" idx dst", idx, extra, extras[dextra])
448
449 # great! got the extra fields in their associated positions:
450 # also we know the register type. now to create the EXTRA encodings
451 etype = rm['Etype'] # Extra type: EXTRA3/EXTRA2
452 ptype = rm['Ptype'] # Predication type: Twin / Single
453 extra_bits = 0
454 v30b_newfields = []
455 for extra_idx, (idx, field, rname, rtype, iname) in extras.items():
456 # is it a field we don't alter/examine? if so just put it
457 # into newfields
458 if rtype is None:
459 v30b_newfields.append(field)
460 continue
461
462 # identify if this is a ld/st immediate(reg) thing
463 ldst_imm = "(" in field and field[-1] == ')'
464 if ldst_imm:
465 immed, field = field[:-1].split("(")
466
467 field, regmode = decode_reg(field)
468 log(" ", extra_idx, rname, rtype,
469 regmode, iname, field, end=" ")
470
471 # see Mode field https://libre-soc.org/openpower/sv/svp64/
472 # XXX TODO: the following is a bit of a laborious repeated
473 # mess, which could (and should) easily be parameterised.
474 # XXX also TODO: the LD/ST modes which are different
475 # https://libre-soc.org/openpower/sv/ldst/
476
477 # encode SV-GPR and SV-FPR field into extra, v3.0field
478 if rtype in ['GPR', 'FPR']:
479 sv_extra, field = get_extra_gpr(etype, regmode, field)
480 # now sanity-check. EXTRA3 is ok, EXTRA2 has limits
481 # (and shrink to a single bit if ok)
482 if etype == 'EXTRA2':
483 if regmode == 'scalar':
484 # range is r0-r63 in increments of 1
485 assert (sv_extra >> 1) == 0, \
486 "scalar GPR %s cannot fit into EXTRA2 %s" % \
487 (rname, str(extras[extra_idx]))
488 # all good: encode as scalar
489 sv_extra = sv_extra & 0b01
490 else:
491 # range is r0-r127 in increments of 4
492 assert sv_extra & 0b01 == 0, \
493 "%s: vector field %s cannot fit " \
494 "into EXTRA2 %s" % \
495 (insn, rname, str(extras[extra_idx]))
496 # all good: encode as vector (bit 2 set)
497 sv_extra = 0b10 | (sv_extra >> 1)
498 elif regmode == 'vector':
499 # EXTRA3 vector bit needs marking
500 sv_extra |= 0b100
501
502 # encode SV-CR 3-bit field into extra, v3.0field
503 elif rtype == 'CR_3bit':
504 sv_extra, field = get_extra_cr_3bit(etype, regmode, field)
505 # now sanity-check (and shrink afterwards)
506 if etype == 'EXTRA2':
507 if regmode == 'scalar':
508 # range is CR0-CR15 in increments of 1
509 assert (sv_extra >> 1) == 0, \
510 "scalar CR %s cannot fit into EXTRA2 %s" % \
511 (rname, str(extras[extra_idx]))
512 # all good: encode as scalar
513 sv_extra = sv_extra & 0b01
514 else:
515 # range is CR0-CR127 in increments of 16
516 assert sv_extra & 0b111 == 0, \
517 "vector CR %s cannot fit into EXTRA2 %s" % \
518 (rname, str(extras[extra_idx]))
519 # all good: encode as vector (bit 2 set)
520 sv_extra = 0b10 | (sv_extra >> 3)
521 else:
522 if regmode == 'scalar':
523 # range is CR0-CR31 in increments of 1
524 assert (sv_extra >> 2) == 0, \
525 "scalar CR %s cannot fit into EXTRA2 %s" % \
526 (rname, str(extras[extra_idx]))
527 # all good: encode as scalar
528 sv_extra = sv_extra & 0b11
529 else:
530 # range is CR0-CR127 in increments of 8
531 assert sv_extra & 0b11 == 0, \
532 "vector CR %s cannot fit into EXTRA2 %s" % \
533 (rname, str(extras[extra_idx]))
534 # all good: encode as vector (bit 3 set)
535 sv_extra = 0b100 | (sv_extra >> 2)
536
537 # encode SV-CR 5-bit field into extra, v3.0field
538 # *sigh* this is the same as 3-bit except the 2 LSBs are
539 # passed through
540 elif rtype == 'CR_5bit':
541 cr_subfield = field & 0b11
542 field = field >> 2 # strip bottom 2 bits
543 sv_extra, field = get_extra_cr_3bit(etype, regmode, field)
544 # now sanity-check (and shrink afterwards)
545 if etype == 'EXTRA2':
546 if regmode == 'scalar':
547 # range is CR0-CR15 in increments of 1
548 assert (sv_extra >> 1) == 0, \
549 "scalar CR %s cannot fit into EXTRA2 %s" % \
550 (rname, str(extras[extra_idx]))
551 # all good: encode as scalar
552 sv_extra = sv_extra & 0b01
553 else:
554 # range is CR0-CR127 in increments of 16
555 assert sv_extra & 0b111 == 0, \
556 "vector CR %s cannot fit into EXTRA2 %s" % \
557 (rname, str(extras[extra_idx]))
558 # all good: encode as vector (bit 2 set)
559 sv_extra = 0b10 | (sv_extra >> 3)
560 else:
561 if regmode == 'scalar':
562 # range is CR0-CR31 in increments of 1
563 assert (sv_extra >> 2) == 0, \
564 "scalar CR %s cannot fit into EXTRA2 %s" % \
565 (rname, str(extras[extra_idx]))
566 # all good: encode as scalar
567 sv_extra = sv_extra & 0b11
568 else:
569 # range is CR0-CR127 in increments of 8
570 assert sv_extra & 0b11 == 0, \
571 "vector CR %s cannot fit into EXTRA3 %s" % \
572 (rname, str(extras[extra_idx]))
573 # all good: encode as vector (bit 3 set)
574 sv_extra = 0b100 | (sv_extra >> 2)
575 # reconstruct the actual 5-bit CR field
576 field = (field << 2) | cr_subfield
577
578 else:
579 print("no type match", rtype)
580
581 # capture the extra field info
582 log("=>", "%5s" % bin(sv_extra), field)
583 extras[extra_idx] = sv_extra
584
585 # append altered field value to v3.0b, differs for LDST
586 # note that duplicates are skipped e.g. EXTRA2 contains
587 # *BOTH* s:RA *AND* d:RA which happens on LD/ST-with-update
588 srcdest, idx, duplicate = extra_idx
589 if duplicate: # skip adding to v3.0b fields, already added
590 continue
591 if ldst_imm:
592 v30b_newfields.append(("%s(%s)" % (immed, str(field))))
593 else:
594 v30b_newfields.append(str(field))
595
596 log("new v3.0B fields", v30b_op, v30b_newfields)
597 log("extras", extras)
598
599 # rright. now we have all the info. start creating SVP64 RM
600 svp64_rm = SVP64RMFields()
601
602 # begin with EXTRA fields
603 for idx, sv_extra in extras.items():
604 log(idx)
605 if idx is None:
606 continue
607 if idx[0] == 'imm':
608 continue
609 srcdest, idx, duplicate = idx
610 if etype == 'EXTRA2':
611 svp64_rm.extra2[idx].eq(
612 SelectableInt(sv_extra, SVP64RM_EXTRA2_SPEC_SIZE))
613 else:
614 svp64_rm.extra3[idx].eq(
615 SelectableInt(sv_extra, SVP64RM_EXTRA3_SPEC_SIZE))
616
617 # identify if the op is a LD/ST. the "blegh" way. copied
618 # from power_enums. TODO, split the list _insns down.
619 is_ld = v30b_op in [
620 "lbarx", "lbz", "lbzu", "lbzux", "lbzx", # load byte
621 "ld", "ldarx", "ldbrx", "ldu", "ldux", "ldx", # load double
622 "lfs", "lfsx", "lfsu", "lfsux", # FP load single
623 "lfd", "lfdx", "lfdu", "lfdux", "lfiwzx", "lfiwax", # FP load double
624 "lha", "lharx", "lhau", "lhaux", "lhax", # load half
625 "lhbrx", "lhz", "lhzu", "lhzux", "lhzx", # more load half
626 "lwa", "lwarx", "lwaux", "lwax", "lwbrx", # load word
627 "lwz", "lwzcix", "lwzu", "lwzux", "lwzx", # more load word
628 ]
629 is_st = v30b_op in [
630 "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
631 "std", "stdbrx", "stdcx", "stdu", "stdux", "stdx",
632 "stfs", "stfsx", "stfsu", "stfux", # FP store single
633 "stfd", "stfdx", "stfdu", "stfdux", "stfiwx", # FP store double
634 "sth", "sthbrx", "sthcx", "sthu", "sthux", "sthx",
635 "stw", "stwbrx", "stwcx", "stwu", "stwux", "stwx",
636 ]
637 # use this to determine if the SVP64 RM format is different.
638 # see https://libre-soc.org/openpower/sv/ldst/
639 is_ldst = is_ld or is_st
640
641 # branch-conditional detection
642 is_bc = v30b_op in [
643 "bc", "bclr",
644 ]
645
646 # parts of svp64_rm
647 mmode = 0 # bit 0
648 pmask = 0 # bits 1-3
649 destwid = 0 # bits 4-5
650 srcwid = 0 # bits 6-7
651 subvl = 0 # bits 8-9
652 smask = 0 # bits 16-18 but only for twin-predication
653 mode = 0 # bits 19-23
654
655 mask_m_specified = False
656 has_pmask = False
657 has_smask = False
658
659 saturation = None
660 src_zero = 0
661 dst_zero = 0
662 sv_mode = None
663
664 mapreduce = False
665 reverse_gear = False
666 mapreduce_crm = False
667 mapreduce_svm = False
668
669 predresult = False
670 failfirst = False
671 ldst_elstride = 0
672
673 # branch-conditional bits
674 bc_all = 0
675 bc_lru = 0
676 bc_brc = 0
677 bc_svstep = 0
678 bc_vsb = 0
679 bc_vlset = 0
680 bc_vli = 0
681 bc_snz = 0
682
683 # ok let's start identifying opcode augmentation fields
684 for encmode in opmodes:
685 # predicate mask (src and dest)
686 if encmode.startswith("m="):
687 pme = encmode
688 pmmode, pmask = decode_predicate(encmode[2:])
689 smmode, smask = pmmode, pmask
690 mmode = pmmode
691 mask_m_specified = True
692 # predicate mask (dest)
693 elif encmode.startswith("dm="):
694 pme = encmode
695 pmmode, pmask = decode_predicate(encmode[3:])
696 mmode = pmmode
697 has_pmask = True
698 # predicate mask (src, twin-pred)
699 elif encmode.startswith("sm="):
700 sme = encmode
701 smmode, smask = decode_predicate(encmode[3:])
702 mmode = smmode
703 has_smask = True
704 # shifted LD/ST
705 elif encmode.startswith("sh"):
706 ldst_shift = True
707 # vec2/3/4
708 elif encmode.startswith("vec"):
709 subvl = decode_subvl(encmode[3:])
710 # elwidth
711 elif encmode.startswith("ew="):
712 destwid = decode_elwidth(encmode[3:])
713 elif encmode.startswith("sw="):
714 srcwid = decode_elwidth(encmode[3:])
715 # element-strided LD/ST
716 elif encmode == 'els':
717 ldst_elstride = 1
718 # saturation
719 elif encmode == 'sats':
720 assert sv_mode is None
721 saturation = 1
722 sv_mode = 0b10
723 elif encmode == 'satu':
724 assert sv_mode is None
725 sv_mode = 0b10
726 saturation = 0
727 # predicate zeroing
728 elif encmode == 'sz':
729 src_zero = 1
730 elif encmode == 'dz':
731 dst_zero = 1
732 # failfirst
733 elif encmode.startswith("ff="):
734 assert sv_mode is None
735 sv_mode = 0b01
736 failfirst = decode_ffirst(encmode[3:])
737 # predicate-result, interestingly same as fail-first
738 elif encmode.startswith("pr="):
739 assert sv_mode is None
740 sv_mode = 0b11
741 predresult = decode_ffirst(encmode[3:])
742 # map-reduce mode, reverse-gear
743 elif encmode == 'mrr':
744 assert sv_mode is None
745 sv_mode = 0b00
746 mapreduce = True
747 reverse_gear = True
748 # map-reduce mode
749 elif encmode == 'mr':
750 assert sv_mode is None
751 sv_mode = 0b00
752 mapreduce = True
753 elif encmode == 'crm': # CR on map-reduce
754 assert sv_mode is None
755 sv_mode = 0b00
756 mapreduce_crm = True
757 elif encmode == 'svm': # sub-vector mode
758 mapreduce_svm = True
759 elif is_bc:
760 if encmode == 'all':
761 bc_all = 1
762 elif encmode == 'st': # svstep mode
763 bc_step = 1
764 elif encmode == 'sr': # svstep BRc mode
765 bc_step = 1
766 bc_brc = 1
767 elif encmode == 'vs': # VLSET mode
768 bc_vlset = 1
769 elif encmode == 'vsi': # VLSET mode with VLI (VL inclusives)
770 bc_vlset = 1
771 bc_vli = 1
772 elif encmode == 'vsb': # VLSET mode with VSb
773 bc_vlset = 1
774 bc_vsb = 1
775 elif encmode == 'vsbi': # VLSET mode with VLI and VSb
776 bc_vlset = 1
777 bc_vli = 1
778 bc_vsb = 1
779 elif encmode == 'snz': # sz (only) already set above
780 src_zero = 1
781 bc_snz = 1
782 elif encmode == 'lu': # LR update mode
783 bc_lru = 1
784 else:
785 raise AssertionError("unknown encmode %s" % encmode)
786 else:
787 raise AssertionError("unknown encmode %s" % encmode)
788
789 if ptype == '2P':
790 # since m=xx takes precedence (overrides) sm=xx and dm=xx,
791 # treat them as mutually exclusive
792 if mask_m_specified:
793 assert not has_smask,\
794 "cannot have both source-mask and predicate mask"
795 assert not has_pmask,\
796 "cannot have both dest-mask and predicate mask"
797 # since the default is INT predication (ALWAYS), if you
798 # specify one CR mask, you must specify both, to avoid
799 # mixing INT and CR reg types
800 if has_pmask and pmmode == 1:
801 assert has_smask, \
802 "need explicit source-mask in CR twin predication"
803 if has_smask and smmode == 1:
804 assert has_pmask, \
805 "need explicit dest-mask in CR twin predication"
806 # sanity-check that 2Pred mask is same mode
807 if has_pmask and has_smask:
808 assert smmode == pmmode, \
809 "predicate masks %s and %s must be same reg type" % \
810 (pme, sme)
811
812 # sanity-check that twin-predication mask only specified in 2P mode
813 if ptype == '1P':
814 assert not has_smask, \
815 "source-mask can only be specified on Twin-predicate ops"
816 assert not has_pmask, \
817 "dest-mask can only be specified on Twin-predicate ops"
818
819 # construct the mode field, doing sanity-checking along the way
820 if mapreduce_svm:
821 assert sv_mode == 0b00, "sub-vector mode in mapreduce only"
822 assert subvl != 0, "sub-vector mode not possible on SUBVL=1"
823
824 if src_zero:
825 assert has_smask or mask_m_specified, \
826 "src zeroing requires a source predicate"
827 if dst_zero:
828 assert has_pmask or mask_m_specified, \
829 "dest zeroing requires a dest predicate"
830
831 # check LDST shifted, only available in "normal" mode
832 if is_ldst and ldst_shift:
833 assert sv_mode is None, \
834 "LD shift cannot have modes (%s) applied" % sv_mode
835
836 # now create mode and (overridden) src/dst widths
837 # XXX TODO: sanity-check bc modes
838 if is_bc:
839 sv_mode = ((bc_svstep << SVP64MODE.MOD2_MSB) |
840 (bc_vlset << SVP64MODE.MOD2_LSB) |
841 (bc_snz << SVP64MODE.BC_SNZ))
842 srcwid = (bc_vsb << 1) | bc_lru
843 destwid = (bc_lru << 1) | bc_all
844
845 else:
846
847 ######################################
848 # "normal" mode
849 if sv_mode is None:
850 mode |= src_zero << SVP64MODE.SZ # predicate zeroing
851 mode |= dst_zero << SVP64MODE.DZ # predicate zeroing
852 if is_ldst:
853 # TODO: for now, LD/ST-indexed is ignored.
854 mode |= ldst_elstride << SVP64MODE.ELS_NORMAL # el-strided
855 # shifted mode
856 if ldst_shift:
857 mode |= 1 << SVP64MODE.LDST_SHIFT
858 else:
859 # TODO, reduce and subvector mode
860 # 00 1 dz CRM reduce mode (mapreduce), SUBVL=1
861 # 00 1 SVM CRM subvector reduce mode, SUBVL>1
862 pass
863 sv_mode = 0b00
864
865 ######################################
866 # "mapreduce" modes
867 elif sv_mode == 0b00:
868 mode |= (0b1 << SVP64MODE.REDUCE) # sets mapreduce
869 assert dst_zero == 0, "dest-zero not allowed in mapreduce mode"
870 if reverse_gear:
871 mode |= (0b1 << SVP64MODE.RG) # sets Reverse-gear mode
872 if mapreduce_crm:
873 mode |= (0b1 << SVP64MODE.CRM) # sets CRM mode
874 assert rc_mode, "CRM only allowed when Rc=1"
875 # bit of weird encoding to jam zero-pred or SVM mode in.
876 # SVM mode can be enabled only when SUBVL=2/3/4 (vec2/3/4)
877 if subvl == 0:
878 mode |= dst_zero << SVP64MODE.DZ # predicate zeroing
879 elif mapreduce_svm:
880 mode |= (0b1 << SVP64MODE.SVM) # sets SVM mode
881
882 ######################################
883 # "failfirst" modes
884 elif sv_mode == 0b01:
885 assert src_zero == 0, "dest-zero not allowed in failfirst mode"
886 if failfirst == 'RC1':
887 mode |= (0b1 << SVP64MODE.RC1) # sets RC1 mode
888 mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
889 assert rc_mode == False, "ffirst RC1 only possible when Rc=0"
890 elif failfirst == '~RC1':
891 mode |= (0b1 << SVP64MODE.RC1) # sets RC1 mode
892 mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
893 mode |= (0b1 << SVP64MODE.INV) # ... with inversion
894 assert rc_mode == False, "ffirst RC1 only possible when Rc=0"
895 else:
896 assert dst_zero == 0, "dst-zero not allowed in ffirst BO"
897 assert rc_mode, "ffirst BO only possible when Rc=1"
898 mode |= (failfirst << SVP64MODE.BO_LSB) # set BO
899
900 ######################################
901 # "saturation" modes
902 elif sv_mode == 0b10:
903 mode |= src_zero << SVP64MODE.SZ # predicate zeroing
904 mode |= dst_zero << SVP64MODE.DZ # predicate zeroing
905 mode |= (saturation << SVP64MODE.N) # signed/us saturation
906
907 ######################################
908 # "predicate-result" modes. err... code-duplication from ffirst
909 elif sv_mode == 0b11:
910 assert src_zero == 0, "dest-zero not allowed in predresult mode"
911 if predresult == 'RC1':
912 mode |= (0b1 << SVP64MODE.RC1) # sets RC1 mode
913 mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
914 assert rc_mode == False, "pr-mode RC1 only possible when Rc=0"
915 elif predresult == '~RC1':
916 mode |= (0b1 << SVP64MODE.RC1) # sets RC1 mode
917 mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
918 mode |= (0b1 << SVP64MODE.INV) # ... with inversion
919 assert rc_mode == False, "pr-mode RC1 only possible when Rc=0"
920 else:
921 assert dst_zero == 0, "dst-zero not allowed in pr-mode BO"
922 assert rc_mode, "pr-mode BO only possible when Rc=1"
923 mode |= (predresult << SVP64MODE.BO_LSB) # set BO
924
925 # whewww.... modes all done :)
926 # now put into svp64_rm
927 mode |= sv_mode
928 # mode: bits 19-23
929 svp64_rm.mode.eq(SelectableInt(mode, SVP64RM_MODE_SIZE))
930
931 # put in predicate masks into svp64_rm
932 if ptype == '2P':
933 # source pred: bits 16-18
934 svp64_rm.smask.eq(SelectableInt(smask, SVP64RM_SMASK_SIZE))
935 # mask mode: bit 0
936 svp64_rm.mmode.eq(SelectableInt(mmode, SVP64RM_MMODE_SIZE))
937 # 1-pred: bits 1-3
938 svp64_rm.mask.eq(SelectableInt(pmask, SVP64RM_MASK_SIZE))
939
940 # and subvl: bits 8-9
941 svp64_rm.subvl.eq(SelectableInt(subvl, SVP64RM_SUBVL_SIZE))
942
943 # put in elwidths
944 # srcwid: bits 6-7
945 svp64_rm.ewsrc.eq(SelectableInt(srcwid, SVP64RM_EWSRC_SIZE))
946 # destwid: bits 4-5
947 svp64_rm.elwidth.eq(SelectableInt(destwid, SVP64RM_ELWIDTH_SIZE))
948
949 # nice debug printout. (and now for something completely different)
950 # https://youtu.be/u0WOIwlXE9g?t=146
951 svp64_rm_value = svp64_rm.spr.value
952 log("svp64_rm", hex(svp64_rm_value), bin(svp64_rm_value))
953 log(" mmode 0 :", bin(mmode))
954 log(" pmask 1-3 :", bin(pmask))
955 log(" dstwid 4-5 :", bin(destwid))
956 log(" srcwid 6-7 :", bin(srcwid))
957 log(" subvl 8-9 :", bin(subvl))
958 log(" mode 19-23:", bin(mode))
959 offs = 2 if etype == 'EXTRA2' else 3 # 2 or 3 bits
960 for idx, sv_extra in extras.items():
961 if idx is None:
962 continue
963 if idx[0] == 'imm':
964 continue
965 srcdest, idx, duplicate = idx
966 start = (10+idx*offs)
967 end = start + offs-1
968 log(" extra%d %2d-%2d:" % (idx, start, end),
969 bin(sv_extra))
970 if ptype == '2P':
971 log(" smask 16-17:", bin(smask))
972 log()
973
974 # first, construct the prefix from its subfields
975 svp64_prefix = SVP64PrefixFields()
976 svp64_prefix.major.eq(SelectableInt(0x1, SV64P_MAJOR_SIZE))
977 svp64_prefix.pid.eq(SelectableInt(0b11, SV64P_PID_SIZE))
978 svp64_prefix.rm.eq(svp64_rm.spr)
979
980 # fiinally yield the svp64 prefix and the thingy. v3.0b opcode
981 rc = '.' if rc_mode else ''
982 yield ".long 0x%x" % svp64_prefix.insn.value
983 log(v30b_newfields)
984 # argh, sv.fmadds etc. need to be done manually
985 if v30b_op == 'ffmadds':
986 opcode = 59 << (32-6) # bits 0..6 (MSB0)
987 opcode |= int(v30b_newfields[0]) << (32-11) # FRT
988 opcode |= int(v30b_newfields[1]) << (32-16) # FRA
989 opcode |= int(v30b_newfields[2]) << (32-21) # FRB
990 opcode |= int(v30b_newfields[3]) << (32-26) # FRC
991 opcode |= 0b00101 << (32-31) # bits 26-30
992 if rc:
993 opcode |= 1 # Rc, bit 31.
994 yield ".long 0x%x" % opcode
995 # argh, sv.fdmadds need to be done manually
996 elif v30b_op == 'fdmadds':
997 opcode = 59 << (32-6) # bits 0..6 (MSB0)
998 opcode |= int(v30b_newfields[0]) << (32-11) # FRT
999 opcode |= int(v30b_newfields[1]) << (32-16) # FRA
1000 opcode |= int(v30b_newfields[2]) << (32-21) # FRB
1001 opcode |= int(v30b_newfields[3]) << (32-26) # FRC
1002 opcode |= 0b01111 << (32-31) # bits 26-30
1003 if rc:
1004 opcode |= 1 # Rc, bit 31.
1005 yield ".long 0x%x" % opcode
1006 # argh, sv.ffadds etc. need to be done manually
1007 elif v30b_op == 'ffadds':
1008 opcode = 59 << (32-6) # bits 0..6 (MSB0)
1009 opcode |= int(v30b_newfields[0]) << (32-11) # FRT
1010 opcode |= int(v30b_newfields[1]) << (32-16) # FRA
1011 opcode |= int(v30b_newfields[2]) << (32-21) # FRB
1012 opcode |= 0b01101 << (32-31) # bits 26-30
1013 if rc:
1014 opcode |= 1 # Rc, bit 31.
1015 yield ".long 0x%x" % opcode
1016 # sigh have to do svstep here manually for now...
1017 elif opcode in ["svstep", "svstep."]:
1018 insn = 22 << (31-5) # opcode 22, bits 0-5
1019 insn |= int(v30b_newfields[0]) << (31-10) # RT , bits 6-10
1020 insn |= int(v30b_newfields[1]) << (31-22) # SVi , bits 16-22
1021 insn |= int(v30b_newfields[2]) << (31-25) # vf , bit 25
1022 insn |= 0b00011 << (31-30) # XO , bits 26..30
1023 if opcode == 'svstep.':
1024 insn |= 1 << (31-31) # Rc=1 , bit 31
1025 log("svstep", bin(insn))
1026 yield ".long 0x%x" % insn
1027
1028 elif v30b_op in ["setvl", "setvl."]:
1029 insn = 22 << (31-5) # opcode 22, bits 0-5
1030 fields = list(map(int, fields))
1031 insn |= fields[0] << (31-10) # RT , bits 6-10
1032 insn |= fields[1] << (31-15) # RA , bits 11-15
1033 insn |= (fields[2]-1) << (31-22) # SVi , bits 16-22
1034 insn |= fields[3] << (31-25) # ms , bit 25
1035 insn |= fields[4] << (31-24) # vs , bit 24
1036 insn |= fields[5] << (31-23) # vf , bit 23
1037 insn |= 0b00000 << (31-30) # XO , bits 26..30
1038 if opcode == 'setvl.':
1039 insn |= 1 << (31-31) # Rc=1 , bit 31
1040 log("setvl", bin(insn))
1041 yield ".long 0x%x" % insn
1042
1043 elif v30b_op in ["fcoss", "fcoss."]:
1044 insn = 59 << (31-5) # opcode 59, bits 0-5
1045 insn |= int(v30b_newfields[0]) << (31-10) # RT , bits 6-10
1046 insn |= int(v30b_newfields[1]) << (31-20) # RB , bits 16-20
1047 insn |= 0b1000101110 << (31-30) # XO , bits 21..30
1048 if opcode == 'fcoss.':
1049 insn |= 1 << (31-31) # Rc=1 , bit 31
1050 log("fcoss", bin(insn))
1051 yield ".long 0x%x" % insn
1052
1053 else:
1054 yield "%s %s" % (v30b_op+rc, ", ".join(v30b_newfields))
1055 log("new v3.0B fields", v30b_op, v30b_newfields)
1056
1057 def translate(self, lst):
1058 for insn in lst:
1059 yield from self.translate_one(insn)
1060
1061
1062 def macro_subst(macros, txt):
1063 again = True
1064 print("subst", txt, macros)
1065 while again:
1066 again = False
1067 for macro, value in macros.items():
1068 if macro == txt:
1069 again = True
1070 replaced = txt.replace(macro, value)
1071 print("macro", txt, "replaced", replaced, macro, value)
1072 txt = replaced
1073 continue
1074 toreplace = '%s.s' % macro
1075 if toreplace == txt:
1076 again = True
1077 replaced = txt.replace(toreplace, "%s.s" % value)
1078 print("macro", txt, "replaced", replaced, toreplace, value)
1079 txt = replaced
1080 continue
1081 toreplace = '%s.v' % macro
1082 if toreplace == txt:
1083 again = True
1084 replaced = txt.replace(toreplace, "%s.v" % value)
1085 print("macro", txt, "replaced", replaced, toreplace, value)
1086 txt = replaced
1087 continue
1088 toreplace = '(%s)' % macro
1089 if toreplace in txt:
1090 again = True
1091 replaced = txt.replace(toreplace, '(%s)' % value)
1092 print("macro", txt, "replaced", replaced, toreplace, value)
1093 txt = replaced
1094 continue
1095 print(" processed", txt)
1096 return txt
1097
1098
1099 def get_ws(line):
1100 # find whitespace
1101 ws = ''
1102 while line:
1103 if not line[0].isspace():
1104 break
1105 ws += line[0]
1106 line = line[1:]
1107 return ws, line
1108
1109
1110 def asm_process():
1111
1112 # get an input file and an output file
1113 args = sys.argv[1:]
1114 if len(args) == 0:
1115 infile = sys.stdin
1116 outfile = sys.stdout
1117 # read the whole lot in advance in case of in-place
1118 lines = list(infile.readlines())
1119 elif len(args) != 2:
1120 print("pysvp64asm [infile | -] [outfile | -]")
1121 exit(0)
1122 else:
1123 if args[0] == '--':
1124 infile = sys.stdin
1125 else:
1126 infile = open(args[0], "r")
1127 # read the whole lot in advance in case of in-place overwrite
1128 lines = list(infile.readlines())
1129
1130 if args[1] == '--':
1131 outfile = sys.stdout
1132 else:
1133 outfile = open(args[1], "w")
1134
1135 # read the line, look for "sv", process it
1136 macros = {} # macros which start ".set"
1137 isa = SVP64Asm([])
1138 for line in lines:
1139 ls = line.split("#")
1140 # identify macros
1141 op = ls[0].strip()
1142 if op.startswith("setvl") or op.startswith("svshape"):
1143 ws, line = get_ws(ls[0])
1144 lst = list(isa.translate_one(ls[0].strip(), macros))
1145 lst = '; '.join(lst)
1146 outfile.write("%s%s # %s\n" % (ws, lst, ls[0]))
1147 continue
1148 if ls[0].startswith(".set"):
1149 macro = ls[0][4:].split(",")
1150 macro, value = list(map(str.strip, macro))
1151 macros[macro] = value
1152 if len(ls) != 2:
1153 outfile.write(line)
1154 continue
1155 potential = ls[1].strip()
1156 if not potential.startswith("sv."):
1157 outfile.write(line)
1158 continue
1159
1160 ws, line = get_ws(line)
1161 # SV line indentified
1162 lst = list(isa.translate_one(potential, macros))
1163 lst = '; '.join(lst)
1164 outfile.write("%s%s # %s\n" % (ws, lst, potential))
1165
1166
1167 if __name__ == '__main__':
1168 lst = ['slw 3, 1, 4',
1169 'extsw 5, 3',
1170 'sv.extsw 5, 3',
1171 'sv.cmpi 5, 1, 3, 2',
1172 'sv.setb 5, 31',
1173 'sv.isel 64.v, 3, 2, 65.v',
1174 'sv.setb/dm=r3/sm=1<<r3 5, 31',
1175 'sv.setb/m=r3 5, 31',
1176 'sv.setb/vec2 5, 31',
1177 'sv.setb/sw=8/ew=16 5, 31',
1178 'sv.extsw./ff=eq 5, 31',
1179 'sv.extsw./satu/sz/dz/sm=r3/dm=r3 5, 31',
1180 'sv.extsw./pr=eq 5.v, 31',
1181 'sv.add. 5.v, 2.v, 1.v',
1182 'sv.add./m=r3 5.v, 2.v, 1.v',
1183 ]
1184 lst += [
1185 'sv.stw 5.v, 4(1.v)',
1186 'sv.ld 5.v, 4(1.v)',
1187 'setvl. 2, 3, 4, 0, 1, 1',
1188 'sv.setvl. 2, 3, 4, 0, 1, 1',
1189 ]
1190 lst = [
1191 "sv.stfsu 0.v, 16(4.v)",
1192 ]
1193 lst = [
1194 "sv.stfsu/els 0.v, 16(4)",
1195 ]
1196 lst = [
1197 'sv.add./mr 5.v, 2.v, 1.v',
1198 ]
1199 macros = {'win2': '50', 'win': '60'}
1200 lst = [
1201 'sv.addi win2.v, win.v, -1',
1202 'sv.add./mrr 5.v, 2.v, 1.v',
1203 #'sv.lhzsh 5.v, 11(9.v), 15',
1204 #'sv.lwzsh 5.v, 11(9.v), 15',
1205 'sv.ffmadds 6.v, 2.v, 4.v, 6.v',
1206 ]
1207 lst = [
1208 #'sv.fmadds 0.v, 8.v, 16.v, 4.v',
1209 #'sv.ffadds 0.v, 8.v, 4.v',
1210 'svremap 11, 0, 1, 2, 3, 2, 1',
1211 'svshape 8, 1, 1, 1, 0',
1212 'svshape 8, 1, 1, 1, 1',
1213 ]
1214 lst = [
1215 #'sv.lfssh 4.v, 11(8.v), 15',
1216 #'sv.lwzsh 4.v, 11(8.v), 15',
1217 #'sv.svstep. 2.v, 4, 0',
1218 #'sv.fcfids. 48.v, 64.v',
1219 'sv.fcoss. 80.v, 0.v',
1220 'sv.fcoss. 20.v, 0.v',
1221 ]
1222 lst = [
1223 'sv.bc/all 3,12,192',
1224 'sv.bclr/vsbi 3,81.v,192',
1225 ]
1226 isa = SVP64Asm(lst, macros=macros)
1227 print("list", list(isa))
1228 csvs = SVP64RM()
1229 # asm_process()