src/openpower/sv/trans/svp64.py

   1 # SPDX-License-Identifier: LGPLv3+
   2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3 # Funded by NLnet http://nlnet.nl
   4
   5 """SVP64 OpenPOWER v3.0B assembly translator
   6
   7 This class takes raw svp64 assembly mnemonics (aliases excluded) and
   8 creates an EXT001-encoded "svp64 prefix" followed by a v3.0B opcode.
   9
  10 It is very simple and straightforward, the only weirdness being the
  11 extraction of the register information and conversion to v3.0B numbering.
  12
  13 Encoding format of svp64: https://libre-soc.org/openpower/sv/svp64/
  14 Bugtracker: https://bugs.libre-soc.org/show_bug.cgi?id=578
  15 """
  16
  17 import os, sys
  18 from collections import OrderedDict
  19
  20 from openpower.decoder.isa.caller import (SVP64PrefixFields, SV64P_MAJOR_SIZE,
  21                                     SV64P_PID_SIZE, SVP64RMFields,
  22                                     SVP64RM_EXTRA2_SPEC_SIZE,
  23                                     SVP64RM_EXTRA3_SPEC_SIZE,
  24                                     SVP64RM_MODE_SIZE, SVP64RM_SMASK_SIZE,
  25                                     SVP64RM_MMODE_SIZE, SVP64RM_MASK_SIZE,
  26                                     SVP64RM_SUBVL_SIZE, SVP64RM_EWSRC_SIZE,
  27                                     SVP64RM_ELWIDTH_SIZE)
  28 from openpower.decoder.pseudo.pagereader import ISA
  29 from openpower.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra
  30 from openpower.decoder.selectable_int import SelectableInt
  31 from openpower.consts import SVP64MODE
  32
  33
  34 # decode GPR into sv extra
  35 def  get_extra_gpr(etype, regmode, field):
  36     if regmode == 'scalar':
  37         # cut into 2-bits 5-bits SS FFFFF
  38         sv_extra = field >> 5
  39         field = field & 0b11111
  40     else:
  41         # cut into 5-bits 2-bits FFFFF SS
  42         sv_extra = field & 0b11
  43         field = field >> 2
  44     return sv_extra, field
  45
  46
  47 # decode 3-bit CR into sv extra
  48 def  get_extra_cr_3bit(etype, regmode, field):
  49     if regmode == 'scalar':
  50         # cut into 2-bits 3-bits SS FFF
  51         sv_extra = field >> 3
  52         field = field & 0b111
  53     else:
  54         # cut into 3-bits 4-bits FFF SSSS but will cut 2 zeros off later
  55         sv_extra = field & 0b1111
  56         field = field >> 4
  57     return sv_extra, field
  58
  59
  60 # decodes SUBVL
  61 def decode_subvl(encoding):
  62     pmap = {'2': 0b01, '3': 0b10, '4': 0b11}
  63     assert encoding in pmap, \
  64         "encoding %s for SUBVL not recognised" % encoding
  65     return pmap[encoding]
  66
  67
  68 # decodes elwidth
  69 def decode_elwidth(encoding):
  70     pmap = {'8': 0b11, '16': 0b10, '32': 0b01}
  71     assert encoding in pmap, \
  72         "encoding %s for elwidth not recognised" % encoding
  73     return pmap[encoding]
  74
  75
  76 # decodes predicate register encoding
  77 def decode_predicate(encoding):
  78     pmap = { # integer
  79             '1<<r3': (0, 0b001),
  80             'r3'   : (0, 0b010),
  81             '~r3'   : (0, 0b011),
  82             'r10'   : (0, 0b100),
  83             '~r10'  : (0, 0b101),
  84             'r30'   : (0, 0b110),
  85             '~r30'  : (0, 0b111),
  86             # CR
  87             'lt'    : (1, 0b000),
  88             'nl'    : (1, 0b001), 'ge'    : (1, 0b001), # same value
  89             'gt'    : (1, 0b010),
  90             'ng'    : (1, 0b011), 'le'    : (1, 0b011), # same value
  91             'eq'    : (1, 0b100),
  92             'ne'    : (1, 0b101),
  93             'so'    : (1, 0b110), 'un'    : (1, 0b110), # same value
  94             'ns'    : (1, 0b111), 'nu'    : (1, 0b111), # same value
  95            }
  96     assert encoding in pmap, \
  97         "encoding %s for predicate not recognised" % encoding
  98     return pmap[encoding]
  99
 100
 101 # decodes "Mode" in similar way to BO field (supposed to, anyway)
 102 def decode_bo(encoding):
 103     pmap = { # TODO: double-check that these are the same as Branch BO
 104             'lt'    : 0b000,
 105             'nl'    : 0b001, 'ge'    : 0b001, # same value
 106             'gt'    : 0b010,
 107             'ng'    : 0b011, 'le'    : 0b011, # same value
 108             'eq'    : 0b100,
 109             'ne'    : 0b101,
 110             'so'    : 0b110, 'un'    : 0b110, # same value
 111             'ns'    : 0b111, 'nu'    : 0b111, # same value
 112            }
 113     assert encoding in pmap, \
 114         "encoding %s for BO Mode not recognised" % encoding
 115     return pmap[encoding]
 116
 117 # partial-decode fail-first mode
 118 def decode_ffirst(encoding):
 119     if encoding in ['RC1', '~RC1']:
 120         return encoding
 121     return decode_bo(encoding)
 122
 123
 124 def decode_reg(field):
 125     # decode the field number. "5.v" or "3.s" or "9"
 126     field = field.split(".")
 127     regmode = 'scalar' # default
 128     if len(field) == 2:
 129         if field[1] == 's':
 130             regmode = 'scalar'
 131         elif field[1] == 'v':
 132             regmode = 'vector'
 133     field = int(field[0]) # actual register number
 134     return field, regmode
 135
 136
 137 def decode_imm(field):
 138     ldst_imm = "(" in field and field[-1] == ')'
 139     if ldst_imm:
 140         return field[:-1].split("(")
 141     else:
 142         return None, field
 143
 144 # decodes svp64 assembly listings and creates EXT001 svp64 prefixes
 145 class SVP64Asm:
 146     def __init__(self, lst, bigendian=False):
 147         self.lst = lst
 148         self.trans = self.translate(lst)
 149         assert bigendian == False, "error, bigendian not supported yet"
 150
 151     def __iter__(self):
 152         yield from self.trans
 153
 154     def translate(self, lst):
 155         isa = ISA() # reads the v3.0B pseudo-code markdown files
 156         svp64 = SVP64RM() # reads the svp64 Remap entries for registers
 157         for insn in lst:
 158             # find first space, to get opcode
 159             ls = insn.split(' ')
 160             opcode = ls[0]
 161             # now find opcode fields
 162             fields = ''.join(ls[1:]).split(',')
 163             fields = list(map(str.strip, fields))
 164             print ("opcode, fields", ls, opcode, fields)
 165
 166             # sigh have to do setvl here manually for now...
 167             if opcode in ["setvl", "setvl."]:
 168                 insn = 22 << (31-5)          # opcode 22, bits 0-5
 169                 fields = list(map(int, fields))
 170                 insn |= fields[0] << (31-10) # RT       , bits 6-10
 171                 insn |= fields[1] << (31-15) # RA       , bits 11-15
 172                 insn |= fields[2] << (31-23) # SVi      , bits 16-23
 173                 insn |= fields[3] << (31-24) # vs       , bit  24
 174                 insn |= fields[4] << (31-25) # ms       , bit  25
 175                 insn |= 0b00000   << (31-30) # XO       , bits 26..30
 176                 if opcode == 'setvl.':
 177                     insn |= 1 << (31-31)     # Rc=1     , bit 31
 178                 print ("setvl", bin(insn))
 179                 yield ".long 0x%x" % insn
 180                 continue
 181
 182             # identify if is a svp64 mnemonic
 183             if not opcode.startswith('sv.'):
 184                 yield insn  # unaltered
 185                 continue
 186             opcode = opcode[3:] # strip leading "sv"
 187
 188             # start working on decoding the svp64 op: sv.basev30Bop/vec2/mode
 189             opmodes = opcode.split("/") # split at "/"
 190             v30b_op = opmodes.pop(0)    # first is the v3.0B
 191             # check instruction ends with dot
 192             rc_mode = v30b_op.endswith('.')
 193             if rc_mode:
 194                 v30b_op = v30b_op[:-1]
 195
 196             if v30b_op not in isa.instr:
 197                 raise Exception("opcode %s of '%s' not supported" % \
 198                                 (v30b_op, insn))
 199             if v30b_op not in svp64.instrs:
 200                 raise Exception("opcode %s of '%s' not an svp64 instruction" % \
 201                                 (v30b_op, insn))
 202             v30b_regs = isa.instr[v30b_op].regs[0] # get regs info "RT, RA, RB"
 203             rm = svp64.instrs[v30b_op]             # one row of the svp64 RM CSV
 204             print ("v3.0B op", v30b_op, "Rc=1" if rc_mode else '')
 205             print ("v3.0B regs", opcode, v30b_regs)
 206             print ("RM", rm)
 207
 208             # right.  the first thing to do is identify the ordering of
 209             # the registers, by name.  the EXTRA2/3 ordering is in
 210             # rm['0']..rm['3'] but those fields contain the names RA, BB
 211             # etc.  we have to read the pseudocode to understand which
 212             # reg is which in our instruction. sigh.
 213
 214             # first turn the svp64 rm into a "by name" dict, recording
 215             # which position in the RM EXTRA it goes into
 216             # also: record if the src or dest was a CR, for sanity-checking
 217             # (elwidth overrides on CRs are banned)
 218             decode = decode_extra(rm)
 219             dest_reg_cr, src_reg_cr, svp64_src, svp64_dest = decode
 220
 221             print ("EXTRA field index, src", svp64_src)
 222             print ("EXTRA field index, dest", svp64_dest)
 223
 224             # okaaay now we identify the field value (opcode N,N,N) with
 225             # the pseudo-code info (opcode RT, RA, RB)
 226             assert len(fields) == len(v30b_regs), \
 227                 "length of fields %s must match insn `%s`" % \
 228                         (str(v30b_regs), insn)
 229             opregfields = zip(fields, v30b_regs) # err that was easy
 230
 231             # now for each of those find its place in the EXTRA encoding
 232             extras = OrderedDict()
 233             for idx, (field, regname) in enumerate(opregfields):
 234                 imm, regname = decode_imm(regname)
 235                 rtype = get_regtype(regname)
 236                 print ("    idx find", idx, field, regname, imm)
 237                 extra = svp64_src.get(regname, None)
 238                 if extra is not None:
 239                     extra = ('s', extra, False)
 240                     extras[extra] = (idx, field, regname, rtype, imm)
 241                     print ("    idx src", idx, extra, extras[extra])
 242                 dextra = svp64_dest.get(regname, None)
 243                 print ("regname in", regname, dextra)
 244                 if dextra is not None:
 245                     dextra = ('d', dextra, extra is not None)
 246                     extras[dextra] = (idx, field, regname, rtype, imm)
 247                     print ("    idx dst", idx, extra, extras[dextra])
 248
 249             # great! got the extra fields in their associated positions:
 250             # also we know the register type. now to create the EXTRA encodings
 251             etype = rm['Etype'] # Extra type: EXTRA3/EXTRA2
 252             ptype = rm['Ptype'] # Predication type: Twin / Single
 253             extra_bits = 0
 254             v30b_newfields = []
 255             for extra_idx, (idx, field, rname, rtype, iname) in extras.items():
 256                 # is it a field we don't alter/examine?  if so just put it
 257                 # into newfields
 258                 if rtype is None:
 259                     v30b_newfields.append(field)
 260
 261                 # identify if this is a ld/st immediate(reg) thing
 262                 ldst_imm = "(" in field and field[-1] == ')'
 263                 if ldst_imm:
 264                     immed, field = field[:-1].split("(")
 265
 266                 field, regmode = decode_reg(field)
 267                 print ("    ", extra_idx, rname, rtype,
 268                                regmode, iname, field, end=" ")
 269
 270                 # see Mode field https://libre-soc.org/openpower/sv/svp64/
 271                 # XXX TODO: the following is a bit of a laborious repeated
 272                 # mess, which could (and should) easily be parameterised.
 273                 # XXX also TODO: the LD/ST modes which are different
 274                 # https://libre-soc.org/openpower/sv/ldst/
 275
 276                 # encode SV-GPR and SV-FPR field into extra, v3.0field
 277                 if rtype in ['GPR', 'FPR']:
 278                     sv_extra, field = get_extra_gpr(etype, regmode, field)
 279                     # now sanity-check. EXTRA3 is ok, EXTRA2 has limits
 280                     # (and shrink to a single bit if ok)
 281                     if etype == 'EXTRA2':
 282                         if regmode == 'scalar':
 283                             # range is r0-r63 in increments of 1
 284                             assert (sv_extra >> 1) == 0, \
 285                                 "scalar GPR %s cannot fit into EXTRA2 %s" % \
 286                                     (rname, str(extras[extra_idx]))
 287                             # all good: encode as scalar
 288                             sv_extra = sv_extra & 0b01
 289                         else:
 290                             # range is r0-r127 in increments of 4
 291                             assert sv_extra & 0b01 == 0, \
 292                                 "%s: vector field %s cannot fit " \
 293                                 "into EXTRA2 %s" % \
 294                                     (insn, rname, str(extras[extra_idx]))
 295                             # all good: encode as vector (bit 2 set)
 296                             sv_extra = 0b10 | (sv_extra >> 1)
 297                     elif regmode == 'vector':
 298                         # EXTRA3 vector bit needs marking
 299                         sv_extra |= 0b100
 300
 301                 # encode SV-CR 3-bit field into extra, v3.0field
 302                 elif rtype == 'CR_3bit':
 303                     sv_extra, field = get_extra_cr_3bit(etype, regmode, field)
 304                     # now sanity-check (and shrink afterwards)
 305                     if etype == 'EXTRA2':
 306                         if regmode == 'scalar':
 307                             # range is CR0-CR15 in increments of 1
 308                             assert (sv_extra >> 1) == 0, \
 309                                 "scalar CR %s cannot fit into EXTRA2 %s" % \
 310                                     (rname, str(extras[extra_idx]))
 311                             # all good: encode as scalar
 312                             sv_extra = sv_extra & 0b01
 313                         else:
 314                             # range is CR0-CR127 in increments of 16
 315                             assert sv_extra & 0b111 == 0, \
 316                                 "vector CR %s cannot fit into EXTRA2 %s" % \
 317                                     (rname, str(extras[extra_idx]))
 318                             # all good: encode as vector (bit 2 set)
 319                             sv_extra = 0b10 | (sv_extra >> 3)
 320                     else:
 321                         if regmode == 'scalar':
 322                             # range is CR0-CR31 in increments of 1
 323                             assert (sv_extra >> 2) == 0, \
 324                                 "scalar CR %s cannot fit into EXTRA2 %s" % \
 325                                     (rname, str(extras[extra_idx]))
 326                             # all good: encode as scalar
 327                             sv_extra = sv_extra & 0b11
 328                         else:
 329                             # range is CR0-CR127 in increments of 8
 330                             assert sv_extra & 0b11 == 0, \
 331                                 "vector CR %s cannot fit into EXTRA2 %s" % \
 332                                     (rname, str(extras[extra_idx]))
 333                             # all good: encode as vector (bit 3 set)
 334                             sv_extra = 0b100 | (sv_extra >> 2)
 335
 336                 # encode SV-CR 5-bit field into extra, v3.0field
 337                 # *sigh* this is the same as 3-bit except the 2 LSBs are
 338                 # passed through
 339                 elif rtype == 'CR_5bit':
 340                     cr_subfield = field & 0b11
 341                     field = field >> 2 # strip bottom 2 bits
 342                     sv_extra, field = get_extra_cr_3bit(etype, regmode, field)
 343                     # now sanity-check (and shrink afterwards)
 344                     if etype == 'EXTRA2':
 345                         if regmode == 'scalar':
 346                             # range is CR0-CR15 in increments of 1
 347                             assert (sv_extra >> 1) == 0, \
 348                                 "scalar CR %s cannot fit into EXTRA2 %s" % \
 349                                     (rname, str(extras[extra_idx]))
 350                             # all good: encode as scalar
 351                             sv_extra = sv_extra & 0b01
 352                         else:
 353                             # range is CR0-CR127 in increments of 16
 354                             assert sv_extra & 0b111 == 0, \
 355                                 "vector CR %s cannot fit into EXTRA2 %s" % \
 356                                     (rname, str(extras[extra_idx]))
 357                             # all good: encode as vector (bit 2 set)
 358                             sv_extra = 0b10 | (sv_extra >> 3)
 359                     else:
 360                         if regmode == 'scalar':
 361                             # range is CR0-CR31 in increments of 1
 362                             assert (sv_extra >> 2) == 0, \
 363                                 "scalar CR %s cannot fit into EXTRA2 %s" % \
 364                                     (rname, str(extras[extra_idx]))
 365                             # all good: encode as scalar
 366                             sv_extra = sv_extra & 0b11
 367                         else:
 368                             # range is CR0-CR127 in increments of 8
 369                             assert sv_extra & 0b11 == 0, \
 370                                 "vector CR %s cannot fit into EXTRA2 %s" % \
 371                                     (rname, str(extras[extra_idx]))
 372                             # all good: encode as vector (bit 3 set)
 373                             sv_extra = 0b100 | (sv_extra >> 2)
 374
 375                     # reconstruct the actual 5-bit CR field
 376                     field = (field << 2) | cr_subfield
 377
 378                 # capture the extra field info
 379                 print ("=>", "%5s" % bin(sv_extra), field)
 380                 extras[extra_idx] = sv_extra
 381
 382                 # append altered field value to v3.0b, differs for LDST
 383                 srcdest, idx, duplicate = extra_idx
 384                 if duplicate: # skip adding to v3.0b fields, already added
 385                     continue
 386                 if ldst_imm:
 387                     v30b_newfields.append(("%s(%s)" % (immed, str(field))))
 388                 else:
 389                     v30b_newfields.append(str(field))
 390
 391             print ("new v3.0B fields", v30b_op, v30b_newfields)
 392             print ("extras", extras)
 393
 394             # rright.  now we have all the info. start creating SVP64 RM
 395             svp64_rm = SVP64RMFields()
 396
 397             # begin with EXTRA fields
 398             for idx, sv_extra in extras.items():
 399                 if idx is None: continue
 400                 print (idx)
 401                 srcdest, idx, duplicate = idx
 402                 if etype == 'EXTRA2':
 403                     svp64_rm.extra2[idx].eq(
 404                         SelectableInt(sv_extra, SVP64RM_EXTRA2_SPEC_SIZE))
 405                 else:
 406                     svp64_rm.extra3[idx].eq(
 407                         SelectableInt(sv_extra, SVP64RM_EXTRA3_SPEC_SIZE))
 408
 409             # parts of svp64_rm
 410             mmode = 0  # bit 0
 411             pmask = 0  # bits 1-3
 412             destwid = 0 # bits 4-5
 413             srcwid = 0 # bits 6-7
 414             subvl = 0   # bits 8-9
 415             smask = 0 # bits 16-18 but only for twin-predication
 416             mode = 0 # bits 19-23
 417
 418             mask_m_specified = False
 419             has_pmask = False
 420             has_smask = False
 421
 422             saturation = None
 423             src_zero = 0
 424             dst_zero = 0
 425             sv_mode = None
 426
 427             mapreduce = False
 428             mapreduce_crm = False
 429             mapreduce_svm = False
 430
 431             predresult = False
 432             failfirst = False
 433
 434             # ok let's start identifying opcode augmentation fields
 435             for encmode in opmodes:
 436                 # predicate mask (src and dest)
 437                 if encmode.startswith("m="):
 438                     pme = encmode
 439                     pmmode, pmask = decode_predicate(encmode[2:])
 440                     smmode, smask = pmmode, pmask
 441                     mmode = pmmode
 442                     mask_m_specified = True
 443                 # predicate mask (dest)
 444                 elif encmode.startswith("dm="):
 445                     pme = encmode
 446                     pmmode, pmask = decode_predicate(encmode[3:])
 447                     mmode = pmmode
 448                     has_pmask = True
 449                 # predicate mask (src, twin-pred)
 450                 elif encmode.startswith("sm="):
 451                     sme = encmode
 452                     smmode, smask = decode_predicate(encmode[3:])
 453                     mmode = smmode
 454                     has_smask = True
 455                 # vec2/3/4
 456                 elif encmode.startswith("vec"):
 457                     subvl = decode_subvl(encmode[3:])
 458                 # elwidth
 459                 elif encmode.startswith("ew="):
 460                     destwid = decode_elwidth(encmode[3:])
 461                 elif encmode.startswith("sw="):
 462                     srcwid = decode_elwidth(encmode[3:])
 463                 # saturation
 464                 elif encmode == 'sats':
 465                     assert sv_mode is None
 466                     saturation = 1
 467                     sv_mode = 0b10
 468                 elif encmode == 'satu':
 469                     assert sv_mode is None
 470                     sv_mode = 0b10
 471                     saturation = 0
 472                 # predicate zeroing
 473                 elif encmode == 'sz':
 474                     src_zero = 1
 475                 elif encmode == 'dz':
 476                     dst_zero = 1
 477                 # failfirst
 478                 elif encmode.startswith("ff="):
 479                     assert sv_mode is None
 480                     sv_mode = 0b01
 481                     failfirst = decode_ffirst(encmode[3:])
 482                 # predicate-result, interestingly same as fail-first
 483                 elif encmode.startswith("pr="):
 484                     assert sv_mode is None
 485                     sv_mode = 0b11
 486                     predresult = decode_ffirst(encmode[3:])
 487                 # map-reduce mode
 488                 elif encmode == 'mr':
 489                     assert sv_mode is None
 490                     sv_mode = 0b00
 491                     mapreduce = True
 492                 elif encmode == 'crm': # CR on map-reduce
 493                     assert sv_mode is None
 494                     sv_mode = 0b00
 495                     mapreduce_crm = True
 496                 elif encmode == 'svm': # sub-vector mode
 497                     mapreduce_svm = True
 498                 else:
 499                     raise AssertionError("unknown encmode %s" % encmode)
 500
 501             if ptype == '2P':
 502                 # since m=xx takes precedence (overrides) sm=xx and dm=xx,
 503                 # treat them as mutually exclusive
 504                 if mask_m_specified:
 505                     assert not has_smask,\
 506                         "cannot have both source-mask and predicate mask"
 507                     assert not has_pmask,\
 508                         "cannot have both dest-mask and predicate mask"
 509                 # since the default is INT predication (ALWAYS), if you
 510                 # specify one CR mask, you must specify both, to avoid
 511                 # mixing INT and CR reg types
 512                 if has_pmask and pmmode == 1:
 513                     assert has_smask, \
 514                         "need explicit source-mask in CR twin predication"
 515                 if has_smask and smmode == 1:
 516                     assert has_pmask, \
 517                         "need explicit dest-mask in CR twin predication"
 518                 # sanity-check that 2Pred mask is same mode
 519                 if has_pmask and has_smask:
 520                     assert smmode == pmmode, \
 521                         "predicate masks %s and %s must be same reg type" % \
 522                             (pme, sme)
 523
 524             # sanity-check that twin-predication mask only specified in 2P mode
 525             if ptype == '1P':
 526                 assert not has_smask, \
 527                     "source-mask can only be specified on Twin-predicate ops"
 528                 assert not has_pmask, \
 529                     "dest-mask can only be specified on Twin-predicate ops"
 530
 531             # construct the mode field, doing sanity-checking along the way
 532
 533             if mapreduce_svm:
 534                 assert sv_mode == 0b00, "sub-vector mode in mapreduce only"
 535                 assert subvl != 0, "sub-vector mode not possible on SUBVL=1"
 536
 537             if src_zero:
 538                 assert has_smask or mask_m_specified, \
 539                     "src zeroing requires a source predicate"
 540             if dst_zero:
 541                 assert has_pmask or mask_m_specified, \
 542                     "dest zeroing requires a dest predicate"
 543
 544             # "normal" mode
 545             if sv_mode is None:
 546                 mode |= src_zero << SVP64MODE.SZ # predicate zeroing
 547                 mode |= dst_zero << SVP64MODE.DZ # predicate zeroing
 548                 sv_mode = 0b00
 549
 550             # "mapreduce" modes
 551             elif sv_mode == 0b00:
 552                 mode |= (0b1<<SVP64MODE.REDUCE) # sets mapreduce
 553                 assert dst_zero == 0, "dest-zero not allowed in mapreduce mode"
 554                 if mapreduce_crm:
 555                     mode |= (0b1<<SVP64MODE.CRM) # sets CRM mode
 556                     assert rc_mode, "CRM only allowed when Rc=1"
 557                 # bit of weird encoding to jam zero-pred or SVM mode in.
 558                 # SVM mode can be enabled only when SUBVL=2/3/4 (vec2/3/4)
 559                 if subvl == 0:
 560                     mode |= dst_zero << SVP64MODE.DZ # predicate zeroing
 561                 elif mapreduce_svm:
 562                     mode |= (0b1<<SVP64MODE.SVM) # sets SVM mode
 563
 564             # "failfirst" modes
 565             elif sv_mode == 0b01:
 566                 assert src_zero == 0, "dest-zero not allowed in failfirst mode"
 567                 if failfirst == 'RC1':
 568                     mode |= (0b1<<SVP64MODE.RC1) # sets RC1 mode
 569                     mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
 570                     assert rc_mode==False, "ffirst RC1 only possible when Rc=0"
 571                 elif failfirst == '~RC1':
 572                     mode |= (0b1<<SVP64MODE.RC1) # sets RC1 mode
 573                     mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
 574                     mode |= (0b1<<SVP64MODE.INV) # ... with inversion
 575                     assert rc_mode==False, "ffirst RC1 only possible when Rc=0"
 576                 else:
 577                     assert dst_zero == 0, "dst-zero not allowed in ffirst BO"
 578                     assert rc_mode, "ffirst BO only possible when Rc=1"
 579                     mode |= (failfirst << SVP64MODE.BO_LSB) # set BO
 580
 581             # "saturation" modes
 582             elif sv_mode == 0b10:
 583                 mode |= src_zero << SVP64MODE.SZ # predicate zeroing
 584                 mode |= dst_zero << SVP64MODE.DZ # predicate zeroing
 585                 mode |= (saturation << SVP64MODE.N) # signed/unsigned saturation
 586
 587             # "predicate-result" modes.  err... code-duplication from ffirst
 588             elif sv_mode == 0b11:
 589                 assert src_zero == 0, "dest-zero not allowed in predresult mode"
 590                 if predresult == 'RC1':
 591                     mode |= (0b1<<SVP64MODE.RC1) # sets RC1 mode
 592                     mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
 593                     assert rc_mode==False, "pr-mode RC1 only possible when Rc=0"
 594                 elif predresult == '~RC1':
 595                     mode |= (0b1<<SVP64MODE.RC1) # sets RC1 mode
 596                     mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
 597                     mode |= (0b1<<SVP64MODE.INV) # ... with inversion
 598                     assert rc_mode==False, "pr-mode RC1 only possible when Rc=0"
 599                 else:
 600                     assert dst_zero == 0, "dst-zero not allowed in pr-mode BO"
 601                     assert rc_mode, "pr-mode BO only possible when Rc=1"
 602                     mode |= (predresult << SVP64MODE.BO_LSB) # set BO
 603
 604             # whewww.... modes all done :)
 605             # now put into svp64_rm
 606             mode |= sv_mode
 607             # mode: bits 19-23
 608             svp64_rm.mode.eq(SelectableInt(mode, SVP64RM_MODE_SIZE))
 609
 610             # put in predicate masks into svp64_rm
 611             if ptype == '2P':
 612                 # source pred: bits 16-18
 613                 svp64_rm.smask.eq(SelectableInt(smask, SVP64RM_SMASK_SIZE))
 614             # mask mode: bit 0
 615             svp64_rm.mmode.eq(SelectableInt(mmode, SVP64RM_MMODE_SIZE))
 616             # 1-pred: bits 1-3
 617             svp64_rm.mask.eq(SelectableInt(pmask, SVP64RM_MASK_SIZE))
 618
 619             # and subvl: bits 8-9
 620             svp64_rm.subvl.eq(SelectableInt(subvl, SVP64RM_SUBVL_SIZE))
 621
 622             # put in elwidths
 623             # srcwid: bits 6-7
 624             svp64_rm.ewsrc.eq(SelectableInt(srcwid, SVP64RM_EWSRC_SIZE))
 625             # destwid: bits 4-5
 626             svp64_rm.elwidth.eq(SelectableInt(destwid, SVP64RM_ELWIDTH_SIZE))
 627
 628             # nice debug printout. (and now for something completely different)
 629             # https://youtu.be/u0WOIwlXE9g?t=146
 630             svp64_rm_value = svp64_rm.spr.value
 631             print ("svp64_rm", hex(svp64_rm_value), bin(svp64_rm_value))
 632             print ("    mmode  0    :", bin(mmode))
 633             print ("    pmask  1-3  :", bin(pmask))
 634             print ("    dstwid 4-5  :", bin(destwid))
 635             print ("    srcwid 6-7  :", bin(srcwid))
 636             print ("    subvl  8-9  :", bin(subvl))
 637             print ("    mode   19-23:", bin(mode))
 638             offs = 2 if etype == 'EXTRA2' else 3 # 2 or 3 bits
 639             for idx, sv_extra in extras.items():
 640                 if idx is None: continue
 641                 srcdest, idx, duplicate = idx
 642                 start = (10+idx*offs)
 643                 end = start + offs-1
 644                 print ("    extra%d %2d-%2d:" % (idx, start, end),
 645                         bin(sv_extra))
 646             if ptype == '2P':
 647                 print ("    smask  16-17:", bin(smask))
 648             print ()
 649
 650             # first, construct the prefix from its subfields
 651             svp64_prefix = SVP64PrefixFields()
 652             svp64_prefix.major.eq(SelectableInt(0x1, SV64P_MAJOR_SIZE))
 653             svp64_prefix.pid.eq(SelectableInt(0b11, SV64P_PID_SIZE))
 654             svp64_prefix.rm.eq(svp64_rm.spr)
 655
 656             # fiinally yield the svp64 prefix and the thingy.  v3.0b opcode
 657             rc = '.' if rc_mode else ''
 658             yield ".long 0x%x" % svp64_prefix.insn.value
 659             yield "%s %s" % (v30b_op+rc, ", ".join(v30b_newfields))
 660             print ("new v3.0B fields", v30b_op, v30b_newfields)
 661
 662 if __name__ == '__main__':
 663     lst = ['slw 3, 1, 4',
 664                  'extsw 5, 3',
 665                  'sv.extsw 5, 3',
 666                  'sv.cmpi 5, 1, 3, 2',
 667                  'sv.setb 5, 31',
 668                  'sv.isel 64.v, 3, 2, 65.v',
 669                  'sv.setb/dm=r3/sm=1<<r3 5, 31',
 670                  'sv.setb/m=r3 5, 31',
 671                  'sv.setb/vec2 5, 31',
 672                  'sv.setb/sw=8/ew=16 5, 31',
 673                  'sv.extsw./ff=eq 5, 31',
 674                  'sv.extsw./satu/sz/dz/sm=r3/dm=r3 5, 31',
 675                  'sv.extsw./pr=eq 5.v, 31',
 676                  'sv.add. 5.v, 2.v, 1.v',
 677                  'sv.add./m=r3 5.v, 2.v, 1.v',
 678                 ]
 679     lst += [
 680                  'sv.stw 5.v, 4(1.v)',
 681                  'sv.ld 5.v, 4(1.v)',
 682                  'setvl. 2, 3, 4, 1, 1',
 683           ]
 684     lst = [
 685             "sv.stfsu 0.v, 16(4.v)",
 686     ]
 687     isa = SVP64Asm(lst)
 688     print ("list", list(isa))
 689     csvs = SVP64RM()