src/openpower/sv/trans/svp64.py

   1 # SPDX-License-Identifier: LGPLv3+
   2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3 # Funded by NLnet http://nlnet.nl
   4
   5 """SVP64 OpenPOWER v3.0B assembly translator
   6
   7 This class takes raw svp64 assembly mnemonics (aliases excluded) and creates
   8 an EXT001-encoded "svp64 prefix" (as a .long) followed by a v3.0B opcode.
   9
  10 It is very simple and straightforward, the only weirdness being the
  11 extraction of the register information and conversion to v3.0B numbering.
  12
  13 Encoding format of svp64: https://libre-soc.org/openpower/sv/svp64/
  14 Encoding format of arithmetic: https://libre-soc.org/openpower/sv/normal/
  15 Encoding format of LDST: https://libre-soc.org/openpower/sv/ldst/
  16 **TODO format of branches: https://libre-soc.org/openpower/sv/branches/**
  17 **TODO format of CRs: https://libre-soc.org/openpower/sv/cr_ops/**
  18 Bugtracker: https://bugs.libre-soc.org/show_bug.cgi?id=578
  19 """
  20
  21 import functools
  22 import os
  23 import sys
  24 from collections import OrderedDict
  25
  26 from openpower.decoder.isa.caller import (SVP64PrefixFields, SV64P_MAJOR_SIZE,
  27                                           SV64P_PID_SIZE, SVP64RMFields,
  28                                           SVP64RM_EXTRA2_SPEC_SIZE,
  29                                           SVP64RM_EXTRA3_SPEC_SIZE,
  30                                           SVP64RM_MODE_SIZE,
  31                                           SVP64RM_SMASK_SIZE,
  32                                           SVP64RM_MMODE_SIZE,
  33                                           SVP64RM_MASK_SIZE,
  34                                           SVP64RM_SUBVL_SIZE,
  35                                           SVP64RM_EWSRC_SIZE,
  36                                           SVP64RM_ELWIDTH_SIZE)
  37 from openpower.decoder.pseudo.pagereader import ISA
  38 from openpower.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra
  39 from openpower.decoder.selectable_int import SelectableInt
  40 from openpower.consts import SVP64MODE
  41
  42 # for debug logging
  43 from openpower.util import log
  44
  45
  46 def instruction(*fields):
  47     def instruction(insn, desc):
  48         (value, start, end) = desc
  49         bits = ((1,) * ((end + 1) - start))
  50         mask = 0
  51         for bit in bits:
  52             mask = ((mask << 1) | bit)
  53         return (insn | ((value & mask) << (31 - end)))
  54
  55     return functools.reduce(instruction, fields, 0)
  56
  57
  58 def setvl(fields, Rc):
  59     """
  60     setvl is a *32-bit-only* instruction. It controls SVSTATE.
  61     It is *not* a 64-bit-prefixed Vector instruction (no sv.setvl, yet),
  62     it is a Vector *control* instruction.
  63
  64     * setvl RT,RA,SVi,vf,vs,ms
  65
  66     1.6.28 SVL-FORM - from fields.txt
  67     |0     |6    |11    |16   |23 |24 |25 |26    |31 |
  68     | PO   |  RT |   RA | SVi |ms |vs |vf |   XO |Rc |
  69     """
  70     PO = 22
  71     XO = 0b11011
  72     # ARRRGH these are in a non-obvious order in openpower/isa/simplev.mdwn
  73     # compared to the SVL-Form above. sigh
  74     # setvl RT,RA,SVi,vf,vs,ms
  75     (RT, RA, SVi, vf, vs, ms) = fields
  76     SVi -= 1
  77     return instruction(
  78         (PO , 0 , 5),
  79         (RT , 6 , 10),
  80         (RA , 11, 15),
  81         (SVi, 16, 22),
  82         (ms , 23, 23),
  83         (vs , 24, 24),
  84         (vf , 25, 25),
  85         (XO , 26, 30),
  86         (Rc , 31, 31),
  87     )
  88
  89
  90 def svstep(fields, Rc):
  91     """
  92     svstep is a 32-bit instruction. It updates SVSTATE.
  93     It *can* be SVP64-prefixed, to indicate that its registers
  94     are Vectorised.
  95
  96     * svstep RT,SVi,vf
  97
  98     # 1.6.28 SVL-FORM - from fields.txt
  99     # |0     |6    |11    |16   |23 |24 |25 |26    |31 |
 100     # | PO   |  RT | /    | SVi |/  |/  |vf |   XO |Rc |
 101
 102     """
 103     PO = 22
 104     XO = 0b10011
 105     (RT, SVi, vf) = fields
 106     SVi -= 1
 107     return instruction(
 108         (PO , 0 , 5),
 109         (RT , 6 , 10),
 110         (0 , 11, 15),
 111         (SVi, 16, 22),
 112         (0 , 23, 23),
 113         (0 , 24, 24),
 114         (vf , 25, 25),
 115         (XO , 26, 30),
 116         (Rc , 31, 31),
 117     )
 118
 119
 120 def svshape(fields):
 121     """
 122     svshape is a *32-bit-only* instruction. It updates SVSHAPE and SVSTATE.
 123     It is *not* a 64-bit-prefixed Vector instruction (no sv.svshape, yet),
 124     it is a Vector *control* instruction.
 125
 126     * svshape SVxd,SVyd,SVzd,SVrm,vf
 127
 128     # 1.6.33 SVM-FORM from fields.txt
 129     # |0     |6        |11      |16    |21    |25 |26    |31  |
 130     # | PO   |  SVxd   |   SVyd | SVzd | SVrm |vf |   XO      |
 131
 132     """
 133     PO = 22
 134     XO = 0b011001
 135     (SVxd, SVyd, SVzd, SVrm, vf) = fields
 136     SVxd -= 1
 137     SVyd -= 1
 138     SVzd -= 1
 139     return instruction(
 140         (PO  , 0 , 5),
 141         (SVxd, 6 , 10),
 142         (SVyd, 11, 15),
 143         (SVzd, 16, 20),
 144         (SVrm, 21, 24),
 145         (vf  , 25, 25),
 146         (XO  , 26, 31),
 147     )
 148
 149
 150 def svindex(fields):
 151     """
 152     svindex is a *32-bit-only* instruction. It is a convenience
 153     instruction that reduces instruction count for Indexed REMAP
 154     Mode.
 155     It is *not* a 64-bit-prefixed Vector instruction (no sv.svindex, yet),
 156     it is a Vector *control* instruction.
 157
 158     1.6.28 SVI-FORM
 159       |0     |6    |11    |16   |21 |23|24|25|26    31|
 160       | PO   |  RS |rmm   | SVd |ew |yx|mm|sk|   XO   |
 161     """
 162     # note that the dimension field one subtracted
 163     PO = 22
 164     XO = 0b101001
 165     (RS, rmm, SVd, ew, yx, mm, sk) = fields
 166     SVd -= 1
 167     return instruction(
 168         (PO , 0 , 5),
 169         (RS , 6 , 10),
 170         (rmm, 11 , 15),
 171         (SVd, 16 , 20),
 172         (ew , 21 , 22),
 173         (yx , 23 , 23),
 174         (mm , 24 , 24),
 175         (sk , 25 , 25),
 176         (XO , 26 , 31),
 177     )
 178
 179
 180 def svremap(fields):
 181     """
 182     this is a *32-bit-only* instruction. It updates the SVSHAPE SPR
 183     it is *not* a 64-bit-prefixed Vector instruction (no sv.svremap),
 184     it is a Vector *control* instruction.
 185
 186     * svremap SVme,mi0,mi1,mi2,mo0,mo1,pst
 187
 188     # 1.6.34 SVRM-FORM
 189        |0     |6     |11  |13   |15   |17   |19   |21  |22   |26     |31 |
 190        | PO   | SVme |mi0 | mi1 | mi2 | mo0 | mo1 |pst |///  | XO        |
 191
 192     """
 193     PO = 22
 194     XO = 0b111001
 195     (SVme, mi0, mi1, mi2, mo0, mo1, pst) = fields
 196     return instruction(
 197         (PO  , 0 , 5),
 198         (SVme, 6 , 10),
 199         (mi0 , 11, 12),
 200         (mi1 , 13, 14),
 201         (mi2 , 15, 16),
 202         (mo0 , 17, 18),
 203         (mo1 , 19, 20),
 204         (pst , 21, 21),
 205         (0   , 22, 25),
 206         (XO  , 26, 31),
 207     )
 208
 209
 210 # ok from here-on down these are added as 32-bit instructions
 211 # and are here only because binutils (at present) doesn't have
 212 # them (that's being fixed!)
 213 # they can - if implementations then choose - be Vectorised
 214 # because they are general-purpose scalar instructions
 215 def bmask(fields):
 216     """
 217     1.6.2.2 BM2-FORM
 218     |0     |6    |11    |16    |21   |26 |27    31|
 219     | PO   |  RT |   RA |   RB |bm   |L  |   XO   |
 220     """
 221     PO = 22
 222     XO = 0b010001
 223     (RT, RA, RB, bm, L) = fields
 224     return instruction(
 225         (PO, 0 , 5),
 226         (RT, 6 , 10),
 227         (RA, 11, 15),
 228         (RB, 16, 20),
 229         (bm, 21, 25),
 230         (L , 26, 26),
 231         (XO, 27, 31),
 232     )
 233
 234
 235 def fsins(fields, Rc):
 236     # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
 237     # however we are out of space with opcode 22
 238     # 1.6.7 X-FORM
 239     # |0     |6 |7|8|9  |10  |11|12|13  |15|16|17     |20|21    |31  |
 240     # | PO   |   FRT         |     ///     |   FRB       |   XO |Rc  |
 241     PO = 59
 242     XO = 0b1000001110
 243     (FRT, FRB) = fields
 244     return instruction(
 245         (PO , 0 , 5),
 246         (FRT, 6 , 10),
 247         (0  , 11, 15),
 248         (FRB, 16, 20),
 249         (XO , 21, 30),
 250         (Rc , 31, 31),
 251     )
 252
 253
 254 def fcoss(fields, Rc):
 255     # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
 256     # however we are out of space with opcode 22
 257     # 1.6.7 X-FORM
 258     # |0     |6 |7|8|9  |10  |11|12|13  |15|16|17     |20|21    |31  |
 259     # | PO   |   FRT         |     ///     |   FRB       |   XO |Rc  |
 260     PO = 59
 261     XO = 0b1000101110
 262     (FRT, FRB) = fields
 263     return instruction(
 264         (PO , 0 , 5),
 265         (FRT, 6 , 10),
 266         (0  , 11, 15),
 267         (FRB, 16, 20),
 268         (XO , 21, 30),
 269         (Rc , 31, 31),
 270     )
 271
 272
 273 def ternlogi(fields, Rc):
 274     # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
 275     # however we are out of space with opcode 22
 276     # 1.6.34 TLI-FORM
 277     #   |0   |6   |11   |16   |21   |29  |31 |
 278     #   | PO | RT |  RA |  RB | TLI | XO |Rc |
 279     PO = 5
 280     XO = 0
 281     (RT, RA, RB, TLI) = fields
 282     return instruction(
 283         (PO , 0 , 5),
 284         (RT , 6 , 10),
 285         (RA , 11, 15),
 286         (RB , 16, 20),
 287         (TLI, 21, 28),
 288         (XO , 29, 30),
 289         (Rc , 31, 31),
 290     )
 291
 292
 293 def grev(fields, Rc, imm, wide):
 294     # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
 295     # however we are out of space with opcode 22
 296     PO = 5
 297     # _ matches fields in table at:
 298     # https://libre-soc.org/openPOwer/sv/bitmanip/
 299     XO = 0b1_0010_110
 300     if wide:
 301         XO |= 0b100_000
 302     if imm:
 303         XO |= 0b1000_000
 304     (RT, RA, XBI) = fields
 305     insn = (insn << 5) | RT
 306     insn = (insn << 5) | RA
 307     if imm and not wide:
 308         assert 0 <= XBI < 64
 309         insn = (insn << 6) | XBI
 310         insn = (insn << 9) | XO
 311     else:
 312         assert 0 <= XBI < 32
 313         insn = (insn << 5) | XBI
 314         insn = (insn << 10) | XO
 315     insn = (insn << 1) | Rc
 316     return insn
 317
 318
 319 def av(fields, XO, Rc):
 320     # 1.6.7 X-FORM
 321     #   |0     |6 |7|8|9  |10  |11|12|13  |15|16|17     |20|21    |31  |
 322     #   | PO   |       RT      |    RA       |    RB       |   XO |Rc  |
 323     PO = 22
 324     (RT, RA, RB) = fields
 325     return instruction(
 326         (PO, 0 , 5),
 327         (RT, 6 , 10),
 328         (RA, 11, 15),
 329         (RB, 16, 20),
 330         (XO, 21, 30),
 331         (Rc, 31, 31),
 332     )
 333
 334
 335 CUSTOM_INSNS = {}
 336 for (name, hook) in (
 337             ("setvl", setvl),
 338             ("svstep", svstep),
 339             ("fsins", fsins),
 340             ("fcoss", fcoss),
 341             ("ternlogi", ternlogi),
 342         ):
 343     CUSTOM_INSNS[name] = functools.partial(hook, Rc=False)
 344     CUSTOM_INSNS[f"{name}."] = functools.partial(hook, Rc=True)
 345 CUSTOM_INSNS["bmask"] = bmask
 346 CUSTOM_INSNS["svshape"] = svshape
 347 CUSTOM_INSNS["svindex"] = svindex
 348 CUSTOM_INSNS["svremap"] = svremap
 349
 350 for (name, imm, wide) in (
 351             ("grev", False, False),
 352             ("grevi", True, False),
 353             ("grevw", False, True),
 354             ("grevwi", True, True),
 355         ):
 356     CUSTOM_INSNS[name] = functools.partial(grev,
 357         imm=("i" in name), wide=("w" in name), Rc=False)
 358     CUSTOM_INSNS[f"{name}."] = functools.partial(grev,
 359         imm=("i" in name), wide=("w" in name), Rc=True)
 360
 361 for (name, XO) in (
 362             ("maxs"   , 0b0111001110),
 363             ("maxu"   , 0b0011001110),
 364             ("minu"   , 0b0001001110),
 365             ("mins"   , 0b0101001110),
 366             ("absdu"  , 0b1011110110),
 367             ("absds"  , 0b1001110110),
 368             ("avgadd" , 0b1101001110),
 369             ("absdacu", 0b1111110110),
 370             ("absdacs", 0b0111110110),
 371             ("cprop"  , 0b0110001110),
 372         ):
 373     CUSTOM_INSNS[name] = functools.partial(av, XO=XO, Rc=False)
 374     CUSTOM_INSNS[f"{name}."] = functools.partial(av, XO=XO, Rc=True)
 375
 376
 377 # decode GPR into sv extra
 378 def get_extra_gpr(etype, regmode, field):
 379     if regmode == 'scalar':
 380         # cut into 2-bits 5-bits SS FFFFF
 381         sv_extra = field >> 5
 382         field = field & 0b11111
 383     else:
 384         # cut into 5-bits 2-bits FFFFF SS
 385         sv_extra = field & 0b11
 386         field = field >> 2
 387     return sv_extra, field
 388
 389
 390 # decode 3-bit CR into sv extra
 391 def get_extra_cr_3bit(etype, regmode, field):
 392     if regmode == 'scalar':
 393         # cut into 2-bits 3-bits SS FFF
 394         sv_extra = field >> 3
 395         field = field & 0b111
 396     else:
 397         # cut into 3-bits 4-bits FFF SSSS but will cut 2 zeros off later
 398         sv_extra = field & 0b1111
 399         field = field >> 4
 400     return sv_extra, field
 401
 402
 403 # decodes SUBVL
 404 def decode_subvl(encoding):
 405     pmap = {'2': 0b01, '3': 0b10, '4': 0b11}
 406     assert encoding in pmap, \
 407         "encoding %s for SUBVL not recognised" % encoding
 408     return pmap[encoding]
 409
 410
 411 # decodes elwidth
 412 def decode_elwidth(encoding):
 413     pmap = {'8': 0b11, '16': 0b10, '32': 0b01}
 414     assert encoding in pmap, \
 415         "encoding %s for elwidth not recognised" % encoding
 416     return pmap[encoding]
 417
 418
 419 # decodes predicate register encoding
 420 def decode_predicate(encoding):
 421     pmap = {  # integer
 422         '1<<r3': (0, 0b001),
 423         'r3': (0, 0b010),
 424         '~r3': (0, 0b011),
 425         'r10': (0, 0b100),
 426         '~r10': (0, 0b101),
 427         'r30': (0, 0b110),
 428         '~r30': (0, 0b111),
 429         # CR
 430         'lt': (1, 0b000),
 431         'nl': (1, 0b001), 'ge': (1, 0b001),  # same value
 432         'gt': (1, 0b010),
 433         'ng': (1, 0b011), 'le': (1, 0b011),  # same value
 434         'eq': (1, 0b100),
 435         'ne': (1, 0b101),
 436         'so': (1, 0b110), 'un': (1, 0b110),  # same value
 437         'ns': (1, 0b111), 'nu': (1, 0b111),  # same value
 438     }
 439     assert encoding in pmap, \
 440         "encoding %s for predicate not recognised" % encoding
 441     return pmap[encoding]
 442
 443
 444 # decodes "Mode" in similar way to BO field (supposed to, anyway)
 445 def decode_bo(encoding):
 446     pmap = {  # TODO: double-check that these are the same as Branch BO
 447         'lt': 0b000,
 448         'nl': 0b001, 'ge': 0b001,  # same value
 449         'gt': 0b010,
 450         'ng': 0b011, 'le': 0b011,  # same value
 451         'eq': 0b100,
 452         'ne': 0b101,
 453         'so': 0b110, 'un': 0b110,  # same value
 454         'ns': 0b111, 'nu': 0b111,  # same value
 455     }
 456     assert encoding in pmap, \
 457         "encoding %s for BO Mode not recognised" % encoding
 458     return pmap[encoding]
 459
 460 # partial-decode fail-first mode
 461
 462
 463 def decode_ffirst(encoding):
 464     if encoding in ['RC1', '~RC1']:
 465         return encoding
 466     return decode_bo(encoding)
 467
 468
 469 def decode_reg(field):
 470     # decode the field number. "5.v" or "3.s" or "9"
 471     field = field.split(".")
 472     regmode = 'scalar'  # default
 473     if len(field) == 2:
 474         if field[1] == 's':
 475             regmode = 'scalar'
 476         elif field[1] == 'v':
 477             regmode = 'vector'
 478     field = int(field[0])  # actual register number
 479     return field, regmode
 480
 481
 482 def decode_imm(field):
 483     ldst_imm = "(" in field and field[-1] == ')'
 484     if ldst_imm:
 485         return field[:-1].split("(")
 486     else:
 487         return None, field
 488
 489
 490 def crf_extra(etype, regmode, field, extras):
 491     """takes a CR Field number (CR0-CR127), splits into EXTRA2/3 and v3.0
 492     the scalar/vector mode (crNN.v or crNN.s) changes both the format
 493     of the EXTRA2/3 encoding as well as what range of registers is possible.
 494     this function can be used for both BF/BFA and BA/BB/BT by first removing
 495     the bottom 2 bits of BA/BB/BT then re-instating them after encoding.
 496     see https://libre-soc.org/openpower/sv/svp64/appendix/#cr_extra
 497     for specification
 498     """
 499     sv_extra, field = get_extra_cr_3bit(etype, regmode, field)
 500     # now sanity-check (and shrink afterwards)
 501     if etype == 'EXTRA2':
 502         # 3-bit CR Field (BF, BFA) EXTRA2 encoding
 503         if regmode == 'scalar':
 504             # range is CR0-CR15 in increments of 1
 505             assert (sv_extra >> 1) == 0, \
 506                 "scalar CR %s cannot fit into EXTRA2 %s" % \
 507                 (rname, str(extras[extra_idx]))
 508             # all good: encode as scalar
 509             sv_extra = sv_extra & 0b01
 510         else: # vector
 511             # range is CR0-CR127 in increments of 16
 512             assert sv_extra & 0b111 == 0, \
 513                 "vector CR %s cannot fit into EXTRA2 %s" % \
 514                 (rname, str(extras[extra_idx]))
 515             # all good: encode as vector (bit 2 set)
 516             sv_extra = 0b10 | (sv_extra >> 3)
 517     else:
 518         # 3-bit CR Field (BF, BFA) EXTRA3 encoding
 519         if regmode == 'scalar':
 520             # range is CR0-CR31 in increments of 1
 521             assert (sv_extra >> 2) == 0, \
 522                 "scalar CR %s cannot fit into EXTRA3 %s" % \
 523                 (rname, str(extras[extra_idx]))
 524             # all good: encode as scalar
 525             sv_extra = sv_extra & 0b11
 526         else: # vector
 527             # range is CR0-CR127 in increments of 8
 528             assert sv_extra & 0b11 == 0, \
 529                 "vector CR %s cannot fit into EXTRA3 %s" % \
 530                 (rname, str(extras[extra_idx]))
 531             # all good: encode as vector (bit 3 set)
 532             sv_extra = 0b100 | (sv_extra >> 2)
 533     return sv_extra, field
 534
 535
 536 # decodes svp64 assembly listings and creates EXT001 svp64 prefixes
 537 class SVP64Asm:
 538     def __init__(self, lst, bigendian=False, macros=None):
 539         if macros is None:
 540             macros = {}
 541         self.macros = macros
 542         self.lst = lst
 543         self.trans = self.translate(lst)
 544         self.isa = ISA()  # reads the v3.0B pseudo-code markdown files
 545         self.svp64 = SVP64RM()  # reads the svp64 Remap entries for registers
 546         assert bigendian == False, "error, bigendian not supported yet"
 547
 548     def __iter__(self):
 549         yield from self.trans
 550
 551     def translate_one(self, insn, macros=None):
 552         if macros is None:
 553             macros = {}
 554         macros.update(self.macros)
 555         isa = self.isa
 556         svp64 = self.svp64
 557         # find first space, to get opcode
 558         ls = insn.split(' ')
 559         opcode = ls[0]
 560         # now find opcode fields
 561         fields = ''.join(ls[1:]).split(',')
 562         mfields = list(map(str.strip, fields))
 563         log("opcode, fields", ls, opcode, mfields)
 564         fields = []
 565         # macro substitution
 566         for field in mfields:
 567             fields.append(macro_subst(macros, field))
 568         log("opcode, fields substed", ls, opcode, fields)
 569
 570         # identify if it is a special instruction
 571         custom_insn_hook = CUSTOM_INSNS.get(opcode)
 572         if custom_insn_hook is not None:
 573             fields = tuple(map(int, fields))
 574             insn = custom_insn_hook(fields)
 575             log(opcode, bin(insn))
 576             yield ".long 0x%x" % insn
 577             return
 578
 579         # identify if is a svp64 mnemonic
 580         if not opcode.startswith('sv.'):
 581             yield insn  # unaltered
 582             return
 583         opcode = opcode[3:]  # strip leading "sv"
 584
 585         # start working on decoding the svp64 op: sv.basev30Bop/vec2/mode
 586         opmodes = opcode.split("/")  # split at "/"
 587         v30b_op = opmodes.pop(0)    # first is the v3.0B
 588         # check instruction ends with dot
 589         rc_mode = v30b_op.endswith('.')
 590         if rc_mode:
 591             v30b_op = v30b_op[:-1]
 592
 593         # sigh again, have to recognised LD/ST bit-reverse instructions
 594         # this has to be "processed" to fit into a v3.0B without the "sh"
 595         # e.g. ldsh is actually ld
 596         ldst_shift = v30b_op.startswith("l") and v30b_op.endswith("sh")
 597
 598         if v30b_op not in isa.instr:
 599             raise Exception("opcode %s of '%s' not supported" %
 600                             (v30b_op, insn))
 601
 602         if ldst_shift:
 603             # okaay we need to process the fields and make this:
 604             #     ldsh RT, SVD(RA), RC  - 11 bits for SVD, 5 for RC
 605             # into this:
 606             #     ld RT, D(RA)          - 16 bits
 607             # likewise same for SVDS (9 bits for SVDS, 5 for RC, 14 bits for DS)
 608             form = isa.instr[v30b_op].form  # get form (SVD-Form, SVDS-Form)
 609
 610             newfields = []
 611             for field in fields:
 612                 # identify if this is a ld/st immediate(reg) thing
 613                 ldst_imm = "(" in field and field[-1] == ')'
 614                 if ldst_imm:
 615                     newfields.append(field[:-1].split("("))
 616                 else:
 617                     newfields.append(field)
 618
 619             immed, RA = newfields[1]
 620             immed = int(immed)
 621             RC = int(newfields.pop(2))  # better be an integer number!
 622             if form == 'SVD':  # 16 bit: immed 11 bits, RC shift up 11
 623                 immed = (immed & 0b11111111111) | (RC << 11)
 624                 if immed & (1 << 15):  # should be negative
 625                     immed -= 1 << 16
 626             if form == 'SVDS':  # 14 bit: immed 9 bits, RC shift up 9
 627                 immed = (immed & 0b111111111) | (RC << 9)
 628                 if immed & (1 << 13):  # should be negative
 629                     immed -= 1 << 14
 630             newfields[1] = "%d(%s)" % (immed, RA)
 631             fields = newfields
 632
 633             # and strip off "sh" from end, and add "sh" to opmodes, instead
 634             v30b_op = v30b_op[:-2]
 635             opmodes.append("sh")
 636             log("rewritten", v30b_op, opmodes, fields)
 637
 638         if v30b_op not in svp64.instrs:
 639             raise Exception("opcode %s of '%s' not an svp64 instruction" %
 640                             (v30b_op, insn))
 641         v30b_regs = isa.instr[v30b_op].regs[0]  # get regs info "RT, RA, RB"
 642         rm = svp64.instrs[v30b_op]             # one row of the svp64 RM CSV
 643         log("v3.0B op", v30b_op, "Rc=1" if rc_mode else '')
 644         log("v3.0B regs", opcode, v30b_regs)
 645         log("RM", rm)
 646
 647         # right.  the first thing to do is identify the ordering of
 648         # the registers, by name.  the EXTRA2/3 ordering is in
 649         # rm['0']..rm['3'] but those fields contain the names RA, BB
 650         # etc.  we have to read the pseudocode to understand which
 651         # reg is which in our instruction. sigh.
 652
 653         # first turn the svp64 rm into a "by name" dict, recording
 654         # which position in the RM EXTRA it goes into
 655         # also: record if the src or dest was a CR, for sanity-checking
 656         # (elwidth overrides on CRs are banned)
 657         decode = decode_extra(rm)
 658         dest_reg_cr, src_reg_cr, svp64_src, svp64_dest = decode
 659
 660         log("EXTRA field index, src", svp64_src)
 661         log("EXTRA field index, dest", svp64_dest)
 662
 663         # okaaay now we identify the field value (opcode N,N,N) with
 664         # the pseudo-code info (opcode RT, RA, RB)
 665         assert len(fields) == len(v30b_regs), \
 666             "length of fields %s must match insn `%s` fields %s" % \
 667             (str(v30b_regs), insn, str(fields))
 668         opregfields = zip(fields, v30b_regs)  # err that was easy
 669
 670         # now for each of those find its place in the EXTRA encoding
 671         # note there is the possibility (for LD/ST-with-update) of
 672         # RA occurring **TWICE**.  to avoid it getting added to the
 673         # v3.0B suffix twice, we spot it as a duplicate, here
 674         extras = OrderedDict()
 675         for idx, (field, regname) in enumerate(opregfields):
 676             imm, regname = decode_imm(regname)
 677             rtype = get_regtype(regname)
 678             log("    idx find", rtype, idx, field, regname, imm)
 679             if rtype is None:
 680                 # probably an immediate field, append it straight
 681                 extras[('imm', idx, False)] = (idx, field, None, None, None)
 682                 continue
 683             extra = svp64_src.get(regname, None)
 684             if extra is not None:
 685                 extra = ('s', extra, False)  # not a duplicate
 686                 extras[extra] = (idx, field, regname, rtype, imm)
 687                 log("    idx src", idx, extra, extras[extra])
 688             dextra = svp64_dest.get(regname, None)
 689             log("regname in", regname, dextra)
 690             if dextra is not None:
 691                 is_a_duplicate = extra is not None  # duplicate spotted
 692                 dextra = ('d', dextra, is_a_duplicate)
 693                 extras[dextra] = (idx, field, regname, rtype, imm)
 694                 log("    idx dst", idx, extra, extras[dextra])
 695
 696         # great! got the extra fields in their associated positions:
 697         # also we know the register type. now to create the EXTRA encodings
 698         etype = rm['Etype']  # Extra type: EXTRA3/EXTRA2
 699         ptype = rm['Ptype']  # Predication type: Twin / Single
 700         extra_bits = 0
 701         v30b_newfields = []
 702         for extra_idx, (idx, field, rname, rtype, iname) in extras.items():
 703             # is it a field we don't alter/examine?  if so just put it
 704             # into newfields
 705             if rtype is None:
 706                 v30b_newfields.append(field)
 707                 continue
 708
 709             # identify if this is a ld/st immediate(reg) thing
 710             ldst_imm = "(" in field and field[-1] == ')'
 711             if ldst_imm:
 712                 immed, field = field[:-1].split("(")
 713
 714             field, regmode = decode_reg(field)
 715             log("    ", extra_idx, rname, rtype,
 716                 regmode, iname, field, end=" ")
 717
 718             # see Mode field https://libre-soc.org/openpower/sv/svp64/
 719             # XXX TODO: the following is a bit of a laborious repeated
 720             # mess, which could (and should) easily be parameterised.
 721             # XXX also TODO: the LD/ST modes which are different
 722             # https://libre-soc.org/openpower/sv/ldst/
 723
 724             # rright.  SVP64 register numbering is from 0 to 127
 725             # for GPRs, FPRs *and* CR Fields, where for v3.0 the GPRs and RPFs
 726             # are 0-31 and CR Fields are only 0-7.  the SVP64 RM "Extra"
 727             # area is used to extend the numbering from the 32-bit
 728             # instruction, and also to record whether the register
 729             # is scalar or vector. on a per-operand basis.  this
 730             # results in a slightly finnicky encoding: here we go...
 731
 732             # encode SV-GPR and SV-FPR field into extra, v3.0field
 733             if rtype in ['GPR', 'FPR']:
 734                 sv_extra, field = get_extra_gpr(etype, regmode, field)
 735                 # now sanity-check. EXTRA3 is ok, EXTRA2 has limits
 736                 # (and shrink to a single bit if ok)
 737                 if etype == 'EXTRA2':
 738                     if regmode == 'scalar':
 739                         # range is r0-r63 in increments of 1
 740                         assert (sv_extra >> 1) == 0, \
 741                             "scalar GPR %s cannot fit into EXTRA2 %s" % \
 742                             (rname, str(extras[extra_idx]))
 743                         # all good: encode as scalar
 744                         sv_extra = sv_extra & 0b01
 745                     else:
 746                         # range is r0-r127 in increments of 2 (r0 r2 ... r126)
 747                         assert sv_extra & 0b01 == 0, \
 748                             "%s: vector field %s cannot fit " \
 749                             "into EXTRA2 %s" % \
 750                             (insn, rname, str(extras[extra_idx]))
 751                         # all good: encode as vector (bit 2 set)
 752                         sv_extra = 0b10 | (sv_extra >> 1)
 753                 elif regmode == 'vector':
 754                     # EXTRA3 vector bit needs marking
 755                     sv_extra |= 0b100
 756
 757             # encode SV-CR 3-bit field into extra, v3.0field.
 758             # 3-bit is for things like BF and BFA
 759             elif rtype == 'CR_3bit':
 760                 sv_extra, field =  crf_extra(etype, regmode, field, extras)
 761
 762             # encode SV-CR 5-bit field into extra, v3.0field
 763             # 5-bit is for things like BA BB BC BT etc.
 764             # *sigh* this is the same as 3-bit except the 2 LSBs of the
 765             # 5-bit field are passed through unaltered.
 766             elif rtype == 'CR_5bit':
 767                 cr_subfield = field & 0b11 # record bottom 2 bits for later
 768                 field = field >> 2         # strip bottom 2 bits
 769                 # use the exact same 3-bit function for the top 3 bits
 770                 sv_extra, field =  crf_extra(etype, regmode, field, extras)
 771                 # reconstruct the actual 5-bit CR field (preserving the
 772                 # bottom 2 bits, unaltered)
 773                 field = (field << 2) | cr_subfield
 774
 775             else:
 776                 raise Exception("no type match: %s" % rtype)
 777
 778             # capture the extra field info
 779             log("=>", "%5s" % bin(sv_extra), field)
 780             extras[extra_idx] = sv_extra
 781
 782             # append altered field value to v3.0b, differs for LDST
 783             # note that duplicates are skipped e.g. EXTRA2 contains
 784             # *BOTH* s:RA *AND* d:RA which happens on LD/ST-with-update
 785             srcdest, idx, duplicate = extra_idx
 786             if duplicate:  # skip adding to v3.0b fields, already added
 787                 continue
 788             if ldst_imm:
 789                 v30b_newfields.append(("%s(%s)" % (immed, str(field))))
 790             else:
 791                 v30b_newfields.append(str(field))
 792
 793         log("new v3.0B fields", v30b_op, v30b_newfields)
 794         log("extras", extras)
 795
 796         # rright.  now we have all the info. start creating SVP64 RM
 797         svp64_rm = SVP64RMFields()
 798
 799         # begin with EXTRA fields
 800         for idx, sv_extra in extras.items():
 801             log(idx)
 802             if idx is None:
 803                 continue
 804             if idx[0] == 'imm':
 805                 continue
 806             srcdest, idx, duplicate = idx
 807             if etype == 'EXTRA2':
 808                 svp64_rm.extra2[idx].eq(
 809                     SelectableInt(sv_extra, SVP64RM_EXTRA2_SPEC_SIZE))
 810             else:
 811                 svp64_rm.extra3[idx].eq(
 812                     SelectableInt(sv_extra, SVP64RM_EXTRA3_SPEC_SIZE))
 813
 814         # identify if the op is a LD/ST. the "blegh" way. copied
 815         # from power_enums.  TODO, split the list _insns down.
 816         is_ld = v30b_op in [
 817             "lbarx", "lbz", "lbzu", "lbzux", "lbzx",            # load byte
 818             "ld", "ldarx", "ldbrx", "ldu", "ldux", "ldx",       # load double
 819             "lfs", "lfsx", "lfsu", "lfsux",                     # FP load single
 820             "lfd", "lfdx", "lfdu", "lfdux", "lfiwzx", "lfiwax",  # FP load dbl
 821             "lha", "lharx", "lhau", "lhaux", "lhax",            # load half
 822             "lhbrx", "lhz", "lhzu", "lhzux", "lhzx",            # more load half
 823             "lwa", "lwarx", "lwaux", "lwax", "lwbrx",           # load word
 824             "lwz", "lwzcix", "lwzu", "lwzux", "lwzx",           # more load word
 825         ]
 826         is_st = v30b_op in [
 827             "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
 828             "std", "stdbrx", "stdcx", "stdu", "stdux", "stdx",
 829             "stfs", "stfsx", "stfsu", "stfux",                  # FP store sgl
 830             "stfd", "stfdx", "stfdu", "stfdux", "stfiwx",       # FP store dbl
 831             "sth", "sthbrx", "sthcx", "sthu", "sthux", "sthx",
 832             "stw", "stwbrx", "stwcx", "stwu", "stwux", "stwx",
 833         ]
 834         # use this to determine if the SVP64 RM format is different.
 835         # see https://libre-soc.org/openpower/sv/ldst/
 836         is_ldst = is_ld or is_st
 837
 838         # branch-conditional detection
 839         is_bc = v30b_op in [
 840             "bc", "bclr",
 841         ]
 842
 843         # parts of svp64_rm
 844         mmode = 0  # bit 0
 845         pmask = 0  # bits 1-3
 846         destwid = 0  # bits 4-5
 847         srcwid = 0  # bits 6-7
 848         subvl = 0   # bits 8-9
 849         smask = 0  # bits 16-18 but only for twin-predication
 850         mode = 0  # bits 19-23
 851
 852         mask_m_specified = False
 853         has_pmask = False
 854         has_smask = False
 855
 856         saturation = None
 857         src_zero = 0
 858         dst_zero = 0
 859         sv_mode = None
 860
 861         mapreduce = False
 862         reverse_gear = False
 863         mapreduce_crm = False
 864         mapreduce_svm = False
 865
 866         predresult = False
 867         failfirst = False
 868         ldst_elstride = 0
 869
 870         # branch-conditional bits
 871         bc_all = 0
 872         bc_lru = 0
 873         bc_brc = 0
 874         bc_svstep = 0
 875         bc_vsb = 0
 876         bc_vlset = 0
 877         bc_vli = 0
 878         bc_snz = 0
 879
 880         # ok let's start identifying opcode augmentation fields
 881         for encmode in opmodes:
 882             # predicate mask (src and dest)
 883             if encmode.startswith("m="):
 884                 pme = encmode
 885                 pmmode, pmask = decode_predicate(encmode[2:])
 886                 smmode, smask = pmmode, pmask
 887                 mmode = pmmode
 888                 mask_m_specified = True
 889             # predicate mask (dest)
 890             elif encmode.startswith("dm="):
 891                 pme = encmode
 892                 pmmode, pmask = decode_predicate(encmode[3:])
 893                 mmode = pmmode
 894                 has_pmask = True
 895             # predicate mask (src, twin-pred)
 896             elif encmode.startswith("sm="):
 897                 sme = encmode
 898                 smmode, smask = decode_predicate(encmode[3:])
 899                 mmode = smmode
 900                 has_smask = True
 901             # shifted LD/ST
 902             elif encmode.startswith("sh"):
 903                 ldst_shift = True
 904             # vec2/3/4
 905             elif encmode.startswith("vec"):
 906                 subvl = decode_subvl(encmode[3:])
 907             # elwidth
 908             elif encmode.startswith("ew="):
 909                 destwid = decode_elwidth(encmode[3:])
 910             elif encmode.startswith("sw="):
 911                 srcwid = decode_elwidth(encmode[3:])
 912             # element-strided LD/ST
 913             elif encmode == 'els':
 914                 ldst_elstride = 1
 915             # saturation
 916             elif encmode == 'sats':
 917                 assert sv_mode is None
 918                 saturation = 1
 919                 sv_mode = 0b10
 920             elif encmode == 'satu':
 921                 assert sv_mode is None
 922                 sv_mode = 0b10
 923                 saturation = 0
 924             # predicate zeroing
 925             elif encmode == 'sz':
 926                 src_zero = 1
 927             elif encmode == 'dz':
 928                 dst_zero = 1
 929             # failfirst
 930             elif encmode.startswith("ff="):
 931                 assert sv_mode is None
 932                 sv_mode = 0b01
 933                 failfirst = decode_ffirst(encmode[3:])
 934             # predicate-result, interestingly same as fail-first
 935             elif encmode.startswith("pr="):
 936                 assert sv_mode is None
 937                 sv_mode = 0b11
 938                 predresult = decode_ffirst(encmode[3:])
 939             # map-reduce mode, reverse-gear
 940             elif encmode == 'mrr':
 941                 assert sv_mode is None
 942                 sv_mode = 0b00
 943                 mapreduce = True
 944                 reverse_gear = True
 945             # map-reduce mode
 946             elif encmode == 'mr':
 947                 assert sv_mode is None
 948                 sv_mode = 0b00
 949                 mapreduce = True
 950             elif encmode == 'crm':  # CR on map-reduce
 951                 assert sv_mode is None
 952                 sv_mode = 0b00
 953                 mapreduce_crm = True
 954             elif encmode == 'svm':  # sub-vector mode
 955                 mapreduce_svm = True
 956             elif is_bc:
 957                 if encmode == 'all':
 958                     bc_all = 1
 959                 elif encmode == 'st':  # svstep mode
 960                     bc_step = 1
 961                 elif encmode == 'sr':  # svstep BRc mode
 962                     bc_step = 1
 963                     bc_brc = 1
 964                 elif encmode == 'vs':  # VLSET mode
 965                     bc_vlset = 1
 966                 elif encmode == 'vsi':  # VLSET mode with VLI (VL inclusives)
 967                     bc_vlset = 1
 968                     bc_vli = 1
 969                 elif encmode == 'vsb':  # VLSET mode with VSb
 970                     bc_vlset = 1
 971                     bc_vsb = 1
 972                 elif encmode == 'vsbi':  # VLSET mode with VLI and VSb
 973                     bc_vlset = 1
 974                     bc_vli = 1
 975                     bc_vsb = 1
 976                 elif encmode == 'snz':  # sz (only) already set above
 977                     src_zero = 1
 978                     bc_snz = 1
 979                 elif encmode == 'lu':  # LR update mode
 980                     bc_lru = 1
 981                 else:
 982                     raise AssertionError("unknown encmode %s" % encmode)
 983             else:
 984                 raise AssertionError("unknown encmode %s" % encmode)
 985
 986         if ptype == '2P':
 987             # since m=xx takes precedence (overrides) sm=xx and dm=xx,
 988             # treat them as mutually exclusive
 989             if mask_m_specified:
 990                 assert not has_smask,\
 991                     "cannot have both source-mask and predicate mask"
 992                 assert not has_pmask,\
 993                     "cannot have both dest-mask and predicate mask"
 994             # since the default is INT predication (ALWAYS), if you
 995             # specify one CR mask, you must specify both, to avoid
 996             # mixing INT and CR reg types
 997             if has_pmask and pmmode == 1:
 998                 assert has_smask, \
 999                     "need explicit source-mask in CR twin predication"
1000             if has_smask and smmode == 1:
1001                 assert has_pmask, \
1002                     "need explicit dest-mask in CR twin predication"
1003             # sanity-check that 2Pred mask is same mode
1004             if has_pmask and has_smask:
1005                 assert smmode == pmmode, \
1006                     "predicate masks %s and %s must be same reg type" % \
1007                     (pme, sme)
1008
1009         # sanity-check that twin-predication mask only specified in 2P mode
1010         if ptype == '1P':
1011             assert not has_smask, \
1012                 "source-mask can only be specified on Twin-predicate ops"
1013             assert not has_pmask, \
1014                 "dest-mask can only be specified on Twin-predicate ops"
1015
1016         # construct the mode field, doing sanity-checking along the way
1017         if mapreduce_svm:
1018             assert sv_mode == 0b00, "sub-vector mode in mapreduce only"
1019             assert subvl != 0, "sub-vector mode not possible on SUBVL=1"
1020
1021         if src_zero:
1022             assert has_smask or mask_m_specified, \
1023                 "src zeroing requires a source predicate"
1024         if dst_zero:
1025             assert has_pmask or mask_m_specified, \
1026                 "dest zeroing requires a dest predicate"
1027
1028         # check LDST shifted, only available in "normal" mode
1029         if is_ldst and ldst_shift:
1030             assert sv_mode is None, \
1031                 "LD shift cannot have modes (%s) applied" % sv_mode
1032
1033         # okaaay, so there are 4 different modes, here, which will be
1034         # partly-merged-in: is_ldst is merged in with "normal", but
1035         # is_bc is so different it's done separately.  likewise is_cr
1036         # (when it is done).  here are the maps:
1037
1038         # for "normal" arithmetic: https://libre-soc.org/openpower/sv/normal/
1039         """
1040             | 0-1 |  2  |  3   4  |  description              |
1041             | --- | --- |---------|-------------------------- |
1042             | 00  |   0 |  dz  sz | normal mode                      |
1043             | 00  |   1 | 0  RG   | scalar reduce mode (mapreduce), SUBVL=1 |
1044             | 00  |   1 | 1  /    | parallel reduce mode (mapreduce), SUBVL=1 |
1045             | 00  |   1 | SVM RG  | subvector reduce mode, SUBVL>1   |
1046             | 01  | inv | CR-bit  | Rc=1: ffirst CR sel              |
1047             | 01  | inv | VLi RC1 |  Rc=0: ffirst z/nonz |
1048             | 10  |   N | dz   sz |  sat mode: N=0/1 u/s |
1049             | 11  | inv | CR-bit  |  Rc=1: pred-result CR sel |
1050             | 11  | inv | dz  RC1 |  Rc=0: pred-result z/nonz |
1051         """
1052
1053         # https://libre-soc.org/openpower/sv/ldst/
1054         # for LD/ST-immediate:
1055         """
1056             | 0-1 |  2  |  3   4  |  description               |
1057             | --- | --- |---------|--------------------------- |
1058             | 00  | 0   |  dz els | normal mode                |
1059             | 00  | 1   |  dz shf | shift mode                 |
1060             | 01  | inv | CR-bit  | Rc=1: ffirst CR sel        |
1061             | 01  | inv | els RC1 |  Rc=0: ffirst z/nonz       |
1062             | 10  |   N | dz  els |  sat mode: N=0/1 u/s       |
1063             | 11  | inv | CR-bit  |  Rc=1: pred-result CR sel  |
1064             | 11  | inv | els RC1 |  Rc=0: pred-result z/nonz  |
1065         """
1066
1067         # for LD/ST-indexed (RA+RB):
1068         """
1069             | 0-1 |  2  |  3   4  |  description              |
1070             | --- | --- |---------|-------------------------- |
1071             | 00  | SEA |  dz  sz | normal mode        |
1072             | 01  | SEA | dz sz  | Strided (scalar only source)   |
1073             | 10  |   N | dz   sz |  sat mode: N=0/1 u/s |
1074             | 11  | inv | CR-bit  |  Rc=1: pred-result CR sel |
1075             | 11  | inv | dz  RC1 |  Rc=0: pred-result z/nonz |
1076         """
1077
1078         # and leaving out branches and cr_ops for now because they're
1079         # under development
1080         """ TODO branches and cr_ops
1081         """
1082
1083         # now create mode and (overridden) src/dst widths
1084         # XXX TODO: sanity-check bc modes
1085         if is_bc:
1086             sv_mode = ((bc_svstep << SVP64MODE.MOD2_MSB) |
1087                        (bc_vlset << SVP64MODE.MOD2_LSB) |
1088                        (bc_snz << SVP64MODE.BC_SNZ))
1089             srcwid = (bc_vsb << 1) | bc_lru
1090             destwid = (bc_lru << 1) | bc_all
1091
1092         else:
1093
1094             ######################################
1095             # "normal" mode
1096             if sv_mode is None:
1097                 mode |= src_zero << SVP64MODE.SZ  # predicate zeroing
1098                 mode |= dst_zero << SVP64MODE.DZ  # predicate zeroing
1099                 if is_ldst:
1100                     # TODO: for now, LD/ST-indexed is ignored.
1101                     mode |= ldst_elstride << SVP64MODE.ELS_NORMAL  # el-strided
1102                     # shifted mode
1103                     if ldst_shift:
1104                         mode |= 1 << SVP64MODE.LDST_SHIFT
1105                 else:
1106                     # TODO, reduce and subvector mode
1107                     # 00  1   dz CRM  reduce mode (mapreduce), SUBVL=1
1108                     # 00  1   SVM CRM subvector reduce mode, SUBVL>1
1109                     pass
1110                 sv_mode = 0b00
1111
1112             ######################################
1113             # "mapreduce" modes
1114             elif sv_mode == 0b00:
1115                 mode |= (0b1 << SVP64MODE.REDUCE)  # sets mapreduce
1116                 assert dst_zero == 0, "dest-zero not allowed in mapreduce mode"
1117                 if reverse_gear:
1118                     mode |= (0b1 << SVP64MODE.RG)  # sets Reverse-gear mode
1119                 if mapreduce_crm:
1120                     mode |= (0b1 << SVP64MODE.CRM)  # sets CRM mode
1121                     assert rc_mode, "CRM only allowed when Rc=1"
1122                 # bit of weird encoding to jam zero-pred or SVM mode in.
1123                 # SVM mode can be enabled only when SUBVL=2/3/4 (vec2/3/4)
1124                 if subvl == 0:
1125                     mode |= dst_zero << SVP64MODE.DZ  # predicate zeroing
1126                 elif mapreduce_svm:
1127                     mode |= (0b1 << SVP64MODE.SVM)  # sets SVM mode
1128
1129             ######################################
1130             # "failfirst" modes
1131             elif sv_mode == 0b01:
1132                 assert src_zero == 0, "dest-zero not allowed in failfirst mode"
1133                 if failfirst == 'RC1':
1134                     mode |= (0b1 << SVP64MODE.RC1)  # sets RC1 mode
1135                     mode |= (dst_zero << SVP64MODE.DZ)  # predicate dst-zeroing
1136                     assert rc_mode == False, "ffirst RC1 only ok when Rc=0"
1137                 elif failfirst == '~RC1':
1138                     mode |= (0b1 << SVP64MODE.RC1)  # sets RC1 mode
1139                     mode |= (dst_zero << SVP64MODE.DZ)  # predicate dst-zeroing
1140                     mode |= (0b1 << SVP64MODE.INV)  # ... with inversion
1141                     assert rc_mode == False, "ffirst RC1 only ok when Rc=0"
1142                 else:
1143                     assert dst_zero == 0, "dst-zero not allowed in ffirst BO"
1144                     assert rc_mode, "ffirst BO only possible when Rc=1"
1145                     mode |= (failfirst << SVP64MODE.BO_LSB)  # set BO
1146
1147             ######################################
1148             # "saturation" modes
1149             elif sv_mode == 0b10:
1150                 mode |= src_zero << SVP64MODE.SZ  # predicate zeroing
1151                 mode |= dst_zero << SVP64MODE.DZ  # predicate zeroing
1152                 mode |= (saturation << SVP64MODE.N)  # signed/us saturation
1153
1154             ######################################
1155             # "predicate-result" modes.  err... code-duplication from ffirst
1156             elif sv_mode == 0b11:
1157                 assert src_zero == 0, "dest-zero not allowed in predresult mode"
1158                 if predresult == 'RC1':
1159                     mode |= (0b1 << SVP64MODE.RC1)  # sets RC1 mode
1160                     mode |= (dst_zero << SVP64MODE.DZ)  # predicate dst-zeroing
1161                     assert rc_mode == False, "pr-mode RC1 only ok when Rc=0"
1162                 elif predresult == '~RC1':
1163                     mode |= (0b1 << SVP64MODE.RC1)  # sets RC1 mode
1164                     mode |= (dst_zero << SVP64MODE.DZ)  # predicate dst-zeroing
1165                     mode |= (0b1 << SVP64MODE.INV)  # ... with inversion
1166                     assert rc_mode == False, "pr-mode RC1 only ok when Rc=0"
1167                 else:
1168                     assert dst_zero == 0, "dst-zero not allowed in pr-mode BO"
1169                     assert rc_mode, "pr-mode BO only possible when Rc=1"
1170                     mode |= (predresult << SVP64MODE.BO_LSB)  # set BO
1171
1172         # whewww.... modes all done :)
1173         # now put into svp64_rm
1174         mode |= sv_mode
1175         # mode: bits 19-23
1176         svp64_rm.mode.eq(SelectableInt(mode, SVP64RM_MODE_SIZE))
1177
1178         # put in predicate masks into svp64_rm
1179         if ptype == '2P':
1180             # source pred: bits 16-18
1181             svp64_rm.smask.eq(SelectableInt(smask, SVP64RM_SMASK_SIZE))
1182         # mask mode: bit 0
1183         svp64_rm.mmode.eq(SelectableInt(mmode, SVP64RM_MMODE_SIZE))
1184         # 1-pred: bits 1-3
1185         svp64_rm.mask.eq(SelectableInt(pmask, SVP64RM_MASK_SIZE))
1186
1187         # and subvl: bits 8-9
1188         svp64_rm.subvl.eq(SelectableInt(subvl, SVP64RM_SUBVL_SIZE))
1189
1190         # put in elwidths
1191         # srcwid: bits 6-7
1192         svp64_rm.ewsrc.eq(SelectableInt(srcwid, SVP64RM_EWSRC_SIZE))
1193         # destwid: bits 4-5
1194         svp64_rm.elwidth.eq(SelectableInt(destwid, SVP64RM_ELWIDTH_SIZE))
1195
1196         # nice debug printout. (and now for something completely different)
1197         # https://youtu.be/u0WOIwlXE9g?t=146
1198         svp64_rm_value = svp64_rm.spr.value
1199         log("svp64_rm", hex(svp64_rm_value), bin(svp64_rm_value))
1200         log("    mmode  0    :", bin(mmode))
1201         log("    pmask  1-3  :", bin(pmask))
1202         log("    dstwid 4-5  :", bin(destwid))
1203         log("    srcwid 6-7  :", bin(srcwid))
1204         log("    subvl  8-9  :", bin(subvl))
1205         log("    mode   19-23:", bin(mode))
1206         offs = 2 if etype == 'EXTRA2' else 3  # 2 or 3 bits
1207         for idx, sv_extra in extras.items():
1208             if idx is None:
1209                 continue
1210             if idx[0] == 'imm':
1211                 continue
1212             srcdest, idx, duplicate = idx
1213             start = (10+idx*offs)
1214             end = start + offs-1
1215             log("    extra%d %2d-%2d:" % (idx, start, end),
1216                 bin(sv_extra))
1217         if ptype == '2P':
1218             log("    smask  16-17:", bin(smask))
1219         log()
1220
1221         # first, construct the prefix from its subfields
1222         svp64_prefix = SVP64PrefixFields()
1223         svp64_prefix.major.eq(SelectableInt(0x1, SV64P_MAJOR_SIZE))
1224         svp64_prefix.pid.eq(SelectableInt(0b11, SV64P_PID_SIZE))
1225         svp64_prefix.rm.eq(svp64_rm.spr)
1226
1227         # fiinally yield the svp64 prefix and the thingy.  v3.0b opcode
1228         rc = '.' if rc_mode else ''
1229         yield ".long 0x%08x" % svp64_prefix.insn.value
1230         log(v30b_op, v30b_newfields)
1231         # argh, sv.fmadds etc. need to be done manually
1232         if v30b_op == 'ffmadds':
1233             opcode = 59 << (32-6)    # bits 0..6 (MSB0)
1234             opcode |= int(v30b_newfields[0]) << (32-11)  # FRT
1235             opcode |= int(v30b_newfields[1]) << (32-16)  # FRA
1236             opcode |= int(v30b_newfields[2]) << (32-21)  # FRB
1237             opcode |= int(v30b_newfields[3]) << (32-26)  # FRC
1238             opcode |= 0b00101 << (32-31)   # bits 26-30
1239             if rc:
1240                 opcode |= 1  # Rc, bit 31.
1241             yield ".long 0x%x" % opcode
1242         # argh, sv.fdmadds need to be done manually
1243         elif v30b_op == 'fdmadds':
1244             opcode = 59 << (32-6)    # bits 0..6 (MSB0)
1245             opcode |= int(v30b_newfields[0]) << (32-11)  # FRT
1246             opcode |= int(v30b_newfields[1]) << (32-16)  # FRA
1247             opcode |= int(v30b_newfields[2]) << (32-21)  # FRB
1248             opcode |= int(v30b_newfields[3]) << (32-26)  # FRC
1249             opcode |= 0b01111 << (32-31)   # bits 26-30
1250             if rc:
1251                 opcode |= 1  # Rc, bit 31.
1252             yield ".long 0x%x" % opcode
1253         # argh, sv.ffadds etc. need to be done manually
1254         elif v30b_op == 'ffadds':
1255             opcode = 59 << (32-6)    # bits 0..6 (MSB0)
1256             opcode |= int(v30b_newfields[0]) << (32-11)  # FRT
1257             opcode |= int(v30b_newfields[1]) << (32-16)  # FRA
1258             opcode |= int(v30b_newfields[2]) << (32-21)  # FRB
1259             opcode |= 0b01101 << (32-31)   # bits 26-30
1260             if rc:
1261                 opcode |= 1  # Rc, bit 31.
1262             yield ".long 0x%x" % opcode
1263         # sigh have to do svstep here manually for now...
1264         elif v30b_op in ["svstep", "svstep."]:
1265             insn = 22 << (31-5)          # opcode 22, bits 0-5
1266             insn |= int(v30b_newfields[0]) << (31-10)  # RT       , bits 6-10
1267             insn |= int(v30b_newfields[1]) << (31-22)  # SVi      , bits 16-22
1268             insn |= int(v30b_newfields[2]) << (31-25)  # vf       , bit  25
1269             insn |= 0b10011 << (31-30)  # XO       , bits 26..30
1270             if opcode == 'svstep.':
1271                 insn |= 1 << (31-31)     # Rc=1     , bit 31
1272             log("svstep", bin(insn))
1273             yield ".long 0x%x" % insn
1274         # argh, sv.fcoss etc. need to be done manually
1275         elif v30b_op in ["fcoss", "fcoss."]:
1276             insn = 59 << (31-5)  # opcode 59, bits 0-5
1277             insn |= int(v30b_newfields[0]) << (31-10)  # RT       , bits 6-10
1278             insn |= int(v30b_newfields[1]) << (31-20)  # RB       , bits 16-20
1279             insn |= 0b1000101110 << (31-30)  # XO       , bits 21..30
1280             if opcode == 'fcoss.':
1281                 insn |= 1 << (31-31)     # Rc=1     , bit 31
1282             log("fcoss", bin(insn))
1283             yield ".long 0x%x" % insn
1284
1285         else:
1286             yield "%s %s" % (v30b_op+rc, ", ".join(v30b_newfields))
1287         log("new v3.0B fields", v30b_op, v30b_newfields)
1288
1289     def translate(self, lst):
1290         for insn in lst:
1291             yield from self.translate_one(insn)
1292
1293
1294 def macro_subst(macros, txt):
1295     again = True
1296     log("subst", txt, macros)
1297     while again:
1298         again = False
1299         for macro, value in macros.items():
1300             if macro == txt:
1301                 again = True
1302                 replaced = txt.replace(macro, value)
1303                 log("macro", txt, "replaced", replaced, macro, value)
1304                 txt = replaced
1305                 continue
1306             toreplace = '%s.s' % macro
1307             if toreplace == txt:
1308                 again = True
1309                 replaced = txt.replace(toreplace, "%s.s" % value)
1310                 log("macro", txt, "replaced", replaced, toreplace, value)
1311                 txt = replaced
1312                 continue
1313             toreplace = '%s.v' % macro
1314             if toreplace == txt:
1315                 again = True
1316                 replaced = txt.replace(toreplace, "%s.v" % value)
1317                 log("macro", txt, "replaced", replaced, toreplace, value)
1318                 txt = replaced
1319                 continue
1320             toreplace = '(%s)' % macro
1321             if toreplace in txt:
1322                 again = True
1323                 replaced = txt.replace(toreplace, '(%s)' % value)
1324                 log("macro", txt, "replaced", replaced, toreplace, value)
1325                 txt = replaced
1326                 continue
1327     log("    processed", txt)
1328     return txt
1329
1330
1331 def get_ws(line):
1332     # find whitespace
1333     ws = ''
1334     while line:
1335         if not line[0].isspace():
1336             break
1337         ws += line[0]
1338         line = line[1:]
1339     return ws, line
1340
1341
1342 def asm_process():
1343     # get an input file and an output file
1344     args = sys.argv[1:]
1345     if len(args) == 0:
1346         infile = sys.stdin
1347         outfile = sys.stdout
1348         # read the whole lot in advance in case of in-place
1349         lines = list(infile.readlines())
1350     elif len(args) != 2:
1351         print("pysvp64asm [infile | -] [outfile | -]", file=sys.stderr)
1352         exit(0)
1353     else:
1354         if args[0] == '--':
1355             infile = sys.stdin
1356         else:
1357             infile = open(args[0], "r")
1358         # read the whole lot in advance in case of in-place overwrite
1359         lines = list(infile.readlines())
1360
1361         if args[1] == '--':
1362             outfile = sys.stdout
1363         else:
1364             outfile = open(args[1], "w")
1365
1366     # read the line, look for custom insn, process it
1367     macros = {}  # macros which start ".set"
1368     isa = SVP64Asm([])
1369     for line in lines:
1370         op = line.split("#")[0].strip()
1371         # identify macros
1372         if op.startswith(".set"):
1373             macro = op[4:].split(",")
1374             (macro, value) = map(str.strip, macro)
1375             macros[macro] = value
1376         if not op.startswith('sv.') and not op.startswith(tuple(CUSTOM_INSNS)):
1377             outfile.write(line)
1378             continue
1379
1380         (ws, line) = get_ws(line)
1381         lst = isa.translate_one(op, macros)
1382         lst = '; '.join(lst)
1383         outfile.write("%s%s # %s\n" % (ws, lst, op))
1384
1385
1386 if __name__ == '__main__':
1387     lst = ['slw 3, 1, 4',
1388            'extsw 5, 3',
1389            'sv.extsw 5, 3',
1390            'sv.cmpi 5, 1, 3, 2',
1391            'sv.setb 5, 31',
1392            'sv.isel 64.v, 3, 2, 65.v',
1393            'sv.setb/dm=r3/sm=1<<r3 5, 31',
1394            'sv.setb/m=r3 5, 31',
1395            'sv.setb/vec2 5, 31',
1396            'sv.setb/sw=8/ew=16 5, 31',
1397            'sv.extsw./ff=eq 5, 31',
1398            'sv.extsw./satu/sz/dz/sm=r3/dm=r3 5, 31',
1399            'sv.extsw./pr=eq 5.v, 31',
1400            'sv.add. 5.v, 2.v, 1.v',
1401            'sv.add./m=r3 5.v, 2.v, 1.v',
1402            ]
1403     lst += [
1404         'sv.stw 5.v, 4(1.v)',
1405         'sv.ld 5.v, 4(1.v)',
1406         'setvl. 2, 3, 4, 0, 1, 1',
1407         'sv.setvl. 2, 3, 4, 0, 1, 1',
1408     ]
1409     lst = [
1410         "sv.stfsu 0.v, 16(4.v)",
1411     ]
1412     lst = [
1413         "sv.stfsu/els 0.v, 16(4)",
1414     ]
1415     lst = [
1416         'sv.add./mr 5.v, 2.v, 1.v',
1417     ]
1418     macros = {'win2': '50', 'win': '60'}
1419     lst = [
1420         'sv.addi win2.v, win.v, -1',
1421         'sv.add./mrr 5.v, 2.v, 1.v',
1422         #'sv.lhzsh 5.v, 11(9.v), 15',
1423         #'sv.lwzsh 5.v, 11(9.v), 15',
1424         'sv.ffmadds 6.v, 2.v, 4.v, 6.v',
1425     ]
1426     lst = [
1427         #'sv.fmadds 0.v, 8.v, 16.v, 4.v',
1428         #'sv.ffadds 0.v, 8.v, 4.v',
1429         'svremap 11, 0, 1, 2, 3, 2, 1',
1430         'svshape 8, 1, 1, 1, 0',
1431         'svshape 8, 1, 1, 1, 1',
1432     ]
1433     lst = [
1434         #'sv.lfssh 4.v, 11(8.v), 15',
1435         #'sv.lwzsh 4.v, 11(8.v), 15',
1436         #'sv.svstep. 2.v, 4, 0',
1437         #'sv.fcfids. 48.v, 64.v',
1438         'sv.fcoss. 80.v, 0.v',
1439         'sv.fcoss. 20.v, 0.v',
1440     ]
1441     lst = [
1442         'sv.bc/all 3,12,192',
1443         'sv.bclr/vsbi 3,81.v,192',
1444         'sv.ld 5.v, 4(1.v)',
1445         'sv.svstep. 2.v, 4, 0',
1446     ]
1447     lst = [
1448         'maxs 3,12,5',
1449         'maxs. 3,12,5',
1450         'avgadd 3,12,5',
1451         'absdu 3,12,5',
1452         'absds 3,12,5',
1453         'absdacu 3,12,5',
1454         'absdacs 3,12,5',
1455         'cprop 3,12,5',
1456         'svindex 0,0,1,0,0,0,0',
1457     ]
1458     lst = [
1459         'sv.svstep./m=r3 2.v, 4, 0',
1460     ]
1461     isa = SVP64Asm(lst, macros=macros)
1462     log("list", list(isa))
1463     asm_process()