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remove non-orthogonal ldst_shift
[openpower-isa.git] / src / openpower / sv / trans / svp64.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Funded by NLnet http://nlnet.nl
4
5 """SVP64 OpenPOWER v3.0B assembly translator
6
7 This class takes raw svp64 assembly mnemonics (aliases excluded) and creates
8 an EXT001-encoded "svp64 prefix" (as a .long) followed by a v3.0B opcode.
9
10 It is very simple and straightforward, the only weirdness being the
11 extraction of the register information and conversion to v3.0B numbering.
12
13 Encoding format of svp64: https://libre-soc.org/openpower/sv/svp64/
14 Encoding format of arithmetic: https://libre-soc.org/openpower/sv/normal/
15 Encoding format of LDST: https://libre-soc.org/openpower/sv/ldst/
16 **TODO format of branches: https://libre-soc.org/openpower/sv/branches/**
17 **TODO format of CRs: https://libre-soc.org/openpower/sv/cr_ops/**
18 Bugtracker: https://bugs.libre-soc.org/show_bug.cgi?id=578
19 """
20
21 import functools
22 import os
23 import sys
24 from collections import OrderedDict
25
26 from openpower.decoder.isa.caller import (SVP64PrefixFields, SV64P_MAJOR_SIZE,
27 SV64P_PID_SIZE, SVP64RMFields,
28 SVP64RM_EXTRA2_SPEC_SIZE,
29 SVP64RM_EXTRA3_SPEC_SIZE,
30 SVP64RM_MODE_SIZE,
31 SVP64RM_SMASK_SIZE,
32 SVP64RM_MMODE_SIZE,
33 SVP64RM_MASK_SIZE,
34 SVP64RM_SUBVL_SIZE,
35 SVP64RM_EWSRC_SIZE,
36 SVP64RM_ELWIDTH_SIZE)
37 from openpower.decoder.pseudo.pagereader import ISA
38 from openpower.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra
39 from openpower.decoder.selectable_int import SelectableInt
40 from openpower.consts import SVP64MODE
41
42 # for debug logging
43 from openpower.util import log
44
45
46 def instruction(*fields):
47 def instruction(insn, desc):
48 (value, start, end) = desc
49 bits = ((1,) * ((end + 1) - start))
50 mask = 0
51 for bit in bits:
52 mask = ((mask << 1) | bit)
53 return (insn | ((value & mask) << (31 - end)))
54
55 return functools.reduce(instruction, fields, 0)
56
57
58 def setvl(fields, Rc):
59 """
60 setvl is a *32-bit-only* instruction. It controls SVSTATE.
61 It is *not* a 64-bit-prefixed Vector instruction (no sv.setvl, yet),
62 it is a Vector *control* instruction.
63
64 * setvl RT,RA,SVi,vf,vs,ms
65
66 1.6.28 SVL-FORM - from fields.txt
67 |0 |6 |11 |16 |23 |24 |25 |26 |31 |
68 | PO | RT | RA | SVi |ms |vs |vf | XO |Rc |
69 """
70 PO = 22
71 XO = 0b11011
72 # ARRRGH these are in a non-obvious order in openpower/isa/simplev.mdwn
73 # compared to the SVL-Form above. sigh
74 # setvl RT,RA,SVi,vf,vs,ms
75 (RT, RA, SVi, vf, vs, ms) = fields
76 SVi -= 1
77 return instruction(
78 (PO , 0 , 5 ),
79 (RT , 6 , 10),
80 (RA , 11, 15),
81 (SVi, 16, 22),
82 (ms , 23, 23),
83 (vs , 24, 24),
84 (vf , 25, 25),
85 (XO , 26, 30),
86 (Rc , 31, 31),
87 )
88
89
90 def svstep(fields, Rc):
91 """
92 svstep is a 32-bit instruction. It updates SVSTATE.
93 It *can* be SVP64-prefixed, to indicate that its registers
94 are Vectorised.
95
96 * svstep RT,SVi,vf
97
98 # 1.6.28 SVL-FORM - from fields.txt
99 # |0 |6 |11 |16 |23 |24 |25 |26 |31 |
100 # | PO | RT | / | SVi |/ |/ |vf | XO |Rc |
101
102 """
103 PO = 22
104 XO = 0b10011
105 (RT, SVi, vf) = fields
106 SVi -= 1
107 return instruction(
108 (PO , 0 , 5 ),
109 (RT , 6 , 10),
110 (0 , 11, 15),
111 (SVi, 16, 22),
112 (0 , 23, 23),
113 (0 , 24, 24),
114 (vf , 25, 25),
115 (XO , 26, 30),
116 (Rc , 31, 31),
117 )
118
119
120 def svshape(fields):
121 """
122 svshape is a *32-bit-only* instruction. It updates SVSHAPE and SVSTATE.
123 It is *not* a 64-bit-prefixed Vector instruction (no sv.svshape, yet),
124 it is a Vector *control* instruction.
125
126 * svshape SVxd,SVyd,SVzd,SVrm,vf
127
128 # 1.6.33 SVM-FORM from fields.txt
129 # |0 |6 |11 |16 |21 |25 |26 |31 |
130 # | PO | SVxd | SVyd | SVzd | SVrm |vf | XO |
131
132 """
133 PO = 22
134 XO = 0b011001
135 (SVxd, SVyd, SVzd, SVrm, vf) = fields
136 SVxd -= 1
137 SVyd -= 1
138 SVzd -= 1
139 return instruction(
140 (PO , 0 , 5 ),
141 (SVxd, 6 , 10),
142 (SVyd, 11, 15),
143 (SVzd, 16, 20),
144 (SVrm, 21, 24),
145 (vf , 25, 25),
146 (XO , 26, 31),
147 )
148
149
150 def svindex(fields):
151 """
152 svindex is a *32-bit-only* instruction. It is a convenience
153 instruction that reduces instruction count for Indexed REMAP
154 Mode.
155 It is *not* a 64-bit-prefixed Vector instruction (no sv.svindex, yet),
156 it is a Vector *control* instruction.
157
158 1.6.28 SVI-FORM
159 |0 |6 |11 |16 |21 |23|24|25|26 31|
160 | PO | SVG|rmm | SVd |ew |yx|mm|sk| XO |
161 """
162 # note that the dimension field one subtracted
163 PO = 22
164 XO = 0b101001
165 (SVG, rmm, SVd, ew, yx, mm, sk) = fields
166 SVd -= 1
167 return instruction(
168 (PO , 0 , 5 ),
169 (SVG, 6 , 10),
170 (rmm, 11, 15),
171 (SVd, 16, 20),
172 (ew , 21, 22),
173 (yx , 23, 23),
174 (mm , 24, 24),
175 (sk , 25, 25),
176 (XO , 26, 31),
177 )
178
179
180 def svremap(fields):
181 """
182 this is a *32-bit-only* instruction. It updates the SVSHAPE SPR
183 it is *not* a 64-bit-prefixed Vector instruction (no sv.svremap),
184 it is a Vector *control* instruction.
185
186 * svremap SVme,mi0,mi1,mi2,mo0,mo1,pst
187
188 # 1.6.34 SVRM-FORM
189 |0 |6 |11 |13 |15 |17 |19 |21 |22 |26 |31 |
190 | PO | SVme |mi0 | mi1 | mi2 | mo0 | mo1 |pst |/// | XO |
191
192 """
193 PO = 22
194 XO = 0b111001
195 (SVme, mi0, mi1, mi2, mo0, mo1, pst) = fields
196 return instruction(
197 (PO , 0 , 5 ),
198 (SVme, 6 , 10),
199 (mi0 , 11, 12),
200 (mi1 , 13, 14),
201 (mi2 , 15, 16),
202 (mo0 , 17, 18),
203 (mo1 , 19, 20),
204 (pst , 21, 21),
205 (0 , 22, 25),
206 (XO , 26, 31),
207 )
208
209
210 # ok from here-on down these are added as 32-bit instructions
211 # and are here only because binutils (at present) doesn't have
212 # them (that's being fixed!)
213 # they can - if implementations then choose - be Vectorised
214 # because they are general-purpose scalar instructions
215 def bmask(fields):
216 """
217 1.6.2.2 BM2-FORM
218 |0 |6 |11 |16 |21 |26 |27 31|
219 | PO | RT | RA | RB |bm |L | XO |
220 """
221 PO = 22
222 XO = 0b010001
223 (RT, RA, RB, bm, L) = fields
224 return instruction(
225 (PO, 0 , 5 ),
226 (RT, 6 , 10),
227 (RA, 11, 15),
228 (RB, 16, 20),
229 (bm, 21, 25),
230 (L , 26, 26),
231 (XO, 27, 31),
232 )
233
234
235 def fsins(fields, Rc):
236 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
237 # however we are out of space with opcode 22
238 # 1.6.7 X-FORM
239 # |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 |
240 # | PO | FRT | /// | FRB | XO |Rc |
241 PO = 59
242 XO = 0b1000001110
243 (FRT, FRB) = fields
244 return instruction(
245 (PO , 0 , 5 ),
246 (FRT, 6 , 10),
247 (0 , 11, 15),
248 (FRB, 16, 20),
249 (XO , 21, 30),
250 (Rc , 31, 31),
251 )
252
253
254 def fcoss(fields, Rc):
255 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
256 # however we are out of space with opcode 22
257 # 1.6.7 X-FORM
258 # |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 |
259 # | PO | FRT | /// | FRB | XO |Rc |
260 PO = 59
261 XO = 0b1000101110
262 (FRT, FRB) = fields
263 return instruction(
264 (PO , 0 , 5 ),
265 (FRT, 6 , 10),
266 (0 , 11, 15),
267 (FRB, 16, 20),
268 (XO , 21, 30),
269 (Rc , 31, 31),
270 )
271
272
273 def ternlogi(fields, Rc):
274 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
275 # however we are out of space with opcode 22
276 # 1.6.34 TLI-FORM
277 # |0 |6 |11 |16 |21 |29 |31 |
278 # | PO | RT | RA | RB | TLI | XO |Rc |
279 PO = 5
280 XO = 0
281 (RT, RA, RB, TLI) = fields
282 return instruction(
283 (PO , 0 , 5 ),
284 (RT , 6 , 10),
285 (RA , 11, 15),
286 (RB , 16, 20),
287 (TLI, 21, 28),
288 (XO , 29, 30),
289 (Rc , 31, 31),
290 )
291
292
293 def grev(fields, Rc, imm, wide):
294 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
295 # however we are out of space with opcode 22
296 insn = PO = 5
297 # _ matches fields in table at:
298 # https://libre-soc.org/openPOwer/sv/bitmanip/
299 XO = 0b1_0010_110
300 if wide:
301 XO |= 0b100_000
302 if imm:
303 XO |= 0b1000_000
304 (RT, RA, XBI) = fields
305 insn = (insn << 5) | RT
306 insn = (insn << 5) | RA
307 if imm and not wide:
308 assert 0 <= XBI < 64
309 insn = (insn << 6) | XBI
310 insn = (insn << 9) | XO
311 else:
312 assert 0 <= XBI < 32
313 insn = (insn << 5) | XBI
314 insn = (insn << 10) | XO
315 insn = (insn << 1) | Rc
316 return insn
317
318
319 def av(fields, XO, Rc):
320 # 1.6.7 X-FORM
321 # |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 |
322 # | PO | RT | RA | RB | XO |Rc |
323 PO = 22
324 (RT, RA, RB) = fields
325 return instruction(
326 (PO, 0 , 5 ),
327 (RT, 6 , 10),
328 (RA, 11, 15),
329 (RB, 16, 20),
330 (XO, 21, 30),
331 (Rc, 31, 31),
332 )
333
334
335 def fmvis(fields):
336 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
337 # V3.0B 1.6.6 DX-FORM
338 # |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |26|27 |31 |
339 # | PO | FRS | d1 | d0 | XO |d2 |
340 PO = 22
341 XO = 0b00011
342 (FRS, imm) = fields
343 # first split imm into d1, d0 and d2. sigh
344 d2 = (imm & 1) # LSB (0)
345 d1 = (imm >> 1) & 0b11111 # bits 1-5
346 d0 = (imm >> 6) # MSBs 6-15
347 return instruction(
348 (PO , 0 , 5),
349 (FRS, 6 , 10),
350 (d1, 11, 15),
351 (d0, 16, 25),
352 (XO , 26, 30),
353 (d2 , 31, 31),
354 )
355
356
357 def fishmv(fields):
358 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
359 # V3.0B 1.6.6 DX-FORM
360 # |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |26|27 |31 |
361 # | PO | FRS | d1 | d0 | XO |d2 |
362 PO = 22
363 XO = 0b01011
364 (FRS, imm) = fields
365 # first split imm into d1, d0 and d2. sigh
366 d2 = (imm & 1) # LSB (0)
367 d1 = (imm >> 1) & 0b11111 # bits 1-5
368 d0 = (imm >> 6) # MSBs 6-15
369 return instruction(
370 (PO , 0 , 5),
371 (FRS, 6 , 10),
372 (d1, 11, 15),
373 (d0, 16, 25),
374 (XO , 26, 30),
375 (d2 , 31, 31),
376 )
377
378
379 CUSTOM_INSNS = {}
380 for (name, hook) in (
381 ("setvl", setvl),
382 ("svstep", svstep),
383 ("fsins", fsins),
384 ("fcoss", fcoss),
385 ("ternlogi", ternlogi),
386 ):
387 CUSTOM_INSNS[name] = functools.partial(hook, Rc=False)
388 CUSTOM_INSNS[f"{name}."] = functools.partial(hook, Rc=True)
389 CUSTOM_INSNS["bmask"] = bmask
390 CUSTOM_INSNS["svshape"] = svshape
391 CUSTOM_INSNS["svindex"] = svindex
392 CUSTOM_INSNS["svremap"] = svremap
393 CUSTOM_INSNS["fmvis"] = fmvis
394 CUSTOM_INSNS["fishmv"] = fishmv
395
396 for (name, imm, wide) in (
397 ("grev", False, False),
398 ("grevi", True, False),
399 ("grevw", False, True),
400 ("grevwi", True, True),
401 ):
402 CUSTOM_INSNS[name] = functools.partial(grev,
403 imm=("i" in name), wide=("w" in name), Rc=False)
404 CUSTOM_INSNS[f"{name}."] = functools.partial(grev,
405 imm=("i" in name), wide=("w" in name), Rc=True)
406
407 for (name, XO) in (
408 ("maxs" , 0b0111001110),
409 ("maxu" , 0b0011001110),
410 ("minu" , 0b0001001110),
411 ("mins" , 0b0101001110),
412 ("absdu" , 0b1011110110),
413 ("absds" , 0b1001110110),
414 ("avgadd" , 0b1101001110),
415 ("absdacu", 0b1111110110),
416 ("absdacs", 0b0111110110),
417 ("cprop" , 0b0110001110),
418 ):
419 CUSTOM_INSNS[name] = functools.partial(av, XO=XO, Rc=False)
420 CUSTOM_INSNS[f"{name}."] = functools.partial(av, XO=XO, Rc=True)
421
422
423 # decode GPR into sv extra
424 def get_extra_gpr(etype, regmode, field):
425 if regmode == 'scalar':
426 # cut into 2-bits 5-bits SS FFFFF
427 sv_extra = field >> 5
428 field = field & 0b11111
429 else:
430 # cut into 5-bits 2-bits FFFFF SS
431 sv_extra = field & 0b11
432 field = field >> 2
433 return sv_extra, field
434
435
436 # decode 3-bit CR into sv extra
437 def get_extra_cr_3bit(etype, regmode, field):
438 if regmode == 'scalar':
439 # cut into 2-bits 3-bits SS FFF
440 sv_extra = field >> 3
441 field = field & 0b111
442 else:
443 # cut into 3-bits 4-bits FFF SSSS but will cut 2 zeros off later
444 sv_extra = field & 0b1111
445 field = field >> 4
446 return sv_extra, field
447
448
449 # decodes SUBVL
450 def decode_subvl(encoding):
451 pmap = {'2': 0b01, '3': 0b10, '4': 0b11}
452 assert encoding in pmap, \
453 "encoding %s for SUBVL not recognised" % encoding
454 return pmap[encoding]
455
456
457 # decodes elwidth
458 def decode_elwidth(encoding):
459 pmap = {'8': 0b11, '16': 0b10, '32': 0b01}
460 assert encoding in pmap, \
461 "encoding %s for elwidth not recognised" % encoding
462 return pmap[encoding]
463
464
465 # decodes predicate register encoding
466 def decode_predicate(encoding):
467 pmap = { # integer
468 '1<<r3': (0, 0b001),
469 'r3': (0, 0b010),
470 '~r3': (0, 0b011),
471 'r10': (0, 0b100),
472 '~r10': (0, 0b101),
473 'r30': (0, 0b110),
474 '~r30': (0, 0b111),
475 # CR
476 'lt': (1, 0b000),
477 'nl': (1, 0b001), 'ge': (1, 0b001), # same value
478 'gt': (1, 0b010),
479 'ng': (1, 0b011), 'le': (1, 0b011), # same value
480 'eq': (1, 0b100),
481 'ne': (1, 0b101),
482 'so': (1, 0b110), 'un': (1, 0b110), # same value
483 'ns': (1, 0b111), 'nu': (1, 0b111), # same value
484 }
485 assert encoding in pmap, \
486 "encoding %s for predicate not recognised" % encoding
487 return pmap[encoding]
488
489
490 # decodes "Mode" in similar way to BO field (supposed to, anyway)
491 def decode_bo(encoding):
492 pmap = { # TODO: double-check that these are the same as Branch BO
493 'lt': 0b000,
494 'nl': 0b001, 'ge': 0b001, # same value
495 'gt': 0b010,
496 'ng': 0b011, 'le': 0b011, # same value
497 'eq': 0b100,
498 'ne': 0b101,
499 'so': 0b110, 'un': 0b110, # same value
500 'ns': 0b111, 'nu': 0b111, # same value
501 }
502 assert encoding in pmap, \
503 "encoding %s for BO Mode not recognised" % encoding
504 return pmap[encoding]
505
506 # partial-decode fail-first mode
507
508
509 def decode_ffirst(encoding):
510 if encoding in ['RC1', '~RC1']:
511 return encoding
512 return decode_bo(encoding)
513
514
515 def decode_reg(field, macros=None):
516 if macros is None:
517 macros = {}
518 # decode the field number. "5.v" or "3.s" or "9"
519 # and now also "*0", and "*%0". note: *NOT* to add "*%rNNN" etc.
520 # https://bugs.libre-soc.org/show_bug.cgi?id=884#c0
521 if field.startswith(("*%", "*")):
522 if field.startswith("*%"):
523 field = field[2:]
524 else:
525 field = field[1:]
526 while field in macros:
527 field = macros[field]
528 return int(field), "vector" # actual register number
529
530 # try old convention (to be retired)
531 field = field.split(".")
532 regmode = 'scalar' # default
533 if len(field) == 2:
534 if field[1] == 's':
535 regmode = 'scalar'
536 elif field[1] == 'v':
537 regmode = 'vector'
538 field = int(field[0]) # actual register number
539 return field, regmode
540
541
542 def decode_imm(field):
543 ldst_imm = "(" in field and field[-1] == ')'
544 if ldst_imm:
545 return field[:-1].split("(")
546 else:
547 return None, field
548
549
550 def crf_extra(etype, regmode, field, extras):
551 """takes a CR Field number (CR0-CR127), splits into EXTRA2/3 and v3.0
552 the scalar/vector mode (crNN.v or crNN.s) changes both the format
553 of the EXTRA2/3 encoding as well as what range of registers is possible.
554 this function can be used for both BF/BFA and BA/BB/BT by first removing
555 the bottom 2 bits of BA/BB/BT then re-instating them after encoding.
556 see https://libre-soc.org/openpower/sv/svp64/appendix/#cr_extra
557 for specification
558 """
559 sv_extra, field = get_extra_cr_3bit(etype, regmode, field)
560 # now sanity-check (and shrink afterwards)
561 if etype == 'EXTRA2':
562 # 3-bit CR Field (BF, BFA) EXTRA2 encoding
563 if regmode == 'scalar':
564 # range is CR0-CR15 in increments of 1
565 assert (sv_extra >> 1) == 0, \
566 "scalar CR %s cannot fit into EXTRA2 %s" % \
567 (rname, str(extras[extra_idx]))
568 # all good: encode as scalar
569 sv_extra = sv_extra & 0b01
570 else: # vector
571 # range is CR0-CR127 in increments of 16
572 assert sv_extra & 0b111 == 0, \
573 "vector CR %s cannot fit into EXTRA2 %s" % \
574 (rname, str(extras[extra_idx]))
575 # all good: encode as vector (bit 2 set)
576 sv_extra = 0b10 | (sv_extra >> 3)
577 else:
578 # 3-bit CR Field (BF, BFA) EXTRA3 encoding
579 if regmode == 'scalar':
580 # range is CR0-CR31 in increments of 1
581 assert (sv_extra >> 2) == 0, \
582 "scalar CR %s cannot fit into EXTRA3 %s" % \
583 (rname, str(extras[extra_idx]))
584 # all good: encode as scalar
585 sv_extra = sv_extra & 0b11
586 else: # vector
587 # range is CR0-CR127 in increments of 8
588 assert sv_extra & 0b11 == 0, \
589 "vector CR %s cannot fit into EXTRA3 %s" % \
590 (rname, str(extras[extra_idx]))
591 # all good: encode as vector (bit 3 set)
592 sv_extra = 0b100 | (sv_extra >> 2)
593 return sv_extra, field
594
595
596 def to_number(field):
597 if field.startswith("0x"):
598 return eval(field)
599 if field.startswith("0b"):
600 return eval(field)
601 return int(field)
602
603
604 # decodes svp64 assembly listings and creates EXT001 svp64 prefixes
605 class SVP64Asm:
606 def __init__(self, lst, bigendian=False, macros=None):
607 if macros is None:
608 macros = {}
609 self.macros = macros
610 self.lst = lst
611 self.trans = self.translate(lst)
612 self.isa = ISA() # reads the v3.0B pseudo-code markdown files
613 self.svp64 = SVP64RM() # reads the svp64 Remap entries for registers
614 assert bigendian == False, "error, bigendian not supported yet"
615
616 def __iter__(self):
617 yield from self.trans
618
619 def translate_one(self, insn, macros=None):
620 if macros is None:
621 macros = {}
622 macros.update(self.macros)
623 isa = self.isa
624 svp64 = self.svp64
625 # find first space, to get opcode
626 ls = insn.split(' ')
627 opcode = ls[0]
628 # now find opcode fields
629 fields = ''.join(ls[1:]).split(',')
630 mfields = list(map(str.strip, fields))
631 log("opcode, fields", ls, opcode, mfields)
632 fields = []
633 # macro substitution
634 for field in mfields:
635 fields.append(macro_subst(macros, field))
636 log("opcode, fields substed", ls, opcode, fields)
637
638 # identify if it is a special instruction
639 custom_insn_hook = CUSTOM_INSNS.get(opcode)
640 if custom_insn_hook is not None:
641 fields = tuple(map(to_number, fields))
642 insn = custom_insn_hook(fields)
643 log(opcode, bin(insn))
644 yield ".long 0x%x" % insn
645 return
646
647 # identify if is a svp64 mnemonic
648 if not opcode.startswith('sv.'):
649 yield insn # unaltered
650 return
651 opcode = opcode[3:] # strip leading "sv"
652
653 # start working on decoding the svp64 op: sv.basev30Bop/vec2/mode
654 opmodes = opcode.split("/") # split at "/"
655 v30b_op_orig = opmodes.pop(0) # first is the v3.0B
656 # check instruction ends with dot
657 rc_mode = v30b_op_orig.endswith('.')
658 if rc_mode:
659 v30b_op = v30b_op_orig[:-1]
660 else:
661 v30b_op = v30b_op_orig
662
663 if v30b_op_orig not in isa.instr:
664 raise Exception("opcode %s of '%s' not supported" %
665 (v30b_op, insn))
666
667 if v30b_op_orig not in svp64.instrs:
668 raise Exception("opcode %s of '%s' not an svp64 instruction" %
669 (v30b_op, insn))
670 v30b_regs = isa.instr[v30b_op_orig].regs[0] # get regs info "RT, RA, RB"
671 rm = svp64.instrs[v30b_op_orig] # one row of the svp64 RM CSV
672 log("v3.0B op", v30b_op, "Rc=1" if rc_mode else '')
673 log("v3.0B regs", opcode, v30b_regs)
674 log("RM", rm)
675
676 # right. the first thing to do is identify the ordering of
677 # the registers, by name. the EXTRA2/3 ordering is in
678 # rm['0']..rm['3'] but those fields contain the names RA, BB
679 # etc. we have to read the pseudocode to understand which
680 # reg is which in our instruction. sigh.
681
682 # first turn the svp64 rm into a "by name" dict, recording
683 # which position in the RM EXTRA it goes into
684 # also: record if the src or dest was a CR, for sanity-checking
685 # (elwidth overrides on CRs are banned)
686 decode = decode_extra(rm)
687 dest_reg_cr, src_reg_cr, svp64_src, svp64_dest = decode
688
689 log("EXTRA field index, src", svp64_src)
690 log("EXTRA field index, dest", svp64_dest)
691
692 # okaaay now we identify the field value (opcode N,N,N) with
693 # the pseudo-code info (opcode RT, RA, RB)
694 assert len(fields) == len(v30b_regs), \
695 "length of fields %s must match insn `%s` fields %s" % \
696 (str(v30b_regs), insn, str(fields))
697 opregfields = zip(fields, v30b_regs) # err that was easy
698
699 # now for each of those find its place in the EXTRA encoding
700 # note there is the possibility (for LD/ST-with-update) of
701 # RA occurring **TWICE**. to avoid it getting added to the
702 # v3.0B suffix twice, we spot it as a duplicate, here
703 extras = OrderedDict()
704 for idx, (field, regname) in enumerate(opregfields):
705 imm, regname = decode_imm(regname)
706 rtype = get_regtype(regname)
707 log(" idx find", rtype, idx, field, regname, imm)
708 if rtype is None:
709 # probably an immediate field, append it straight
710 extras[('imm', idx, False)] = (idx, field, None, None, None)
711 continue
712 extra = svp64_src.get(regname, None)
713 if extra is not None:
714 extra = ('s', extra, False) # not a duplicate
715 extras[extra] = (idx, field, regname, rtype, imm)
716 log(" idx src", idx, extra, extras[extra])
717 dextra = svp64_dest.get(regname, None)
718 log("regname in", regname, dextra)
719 if dextra is not None:
720 is_a_duplicate = extra is not None # duplicate spotted
721 dextra = ('d', dextra, is_a_duplicate)
722 extras[dextra] = (idx, field, regname, rtype, imm)
723 log(" idx dst", idx, extra, extras[dextra])
724
725 # great! got the extra fields in their associated positions:
726 # also we know the register type. now to create the EXTRA encodings
727 etype = rm['Etype'] # Extra type: EXTRA3/EXTRA2
728 ptype = rm['Ptype'] # Predication type: Twin / Single
729 extra_bits = 0
730 v30b_newfields = []
731 for extra_idx, (idx, field, rname, rtype, iname) in extras.items():
732 # is it a field we don't alter/examine? if so just put it
733 # into newfields
734 if rtype is None:
735 v30b_newfields.append(field)
736 continue
737
738 # identify if this is a ld/st immediate(reg) thing
739 ldst_imm = "(" in field and field[-1] == ')'
740 if ldst_imm:
741 immed, field = field[:-1].split("(")
742
743 field, regmode = decode_reg(field, macros=macros)
744 log(" ", extra_idx, rname, rtype,
745 regmode, iname, field, end=" ")
746
747 # see Mode field https://libre-soc.org/openpower/sv/svp64/
748 # XXX TODO: the following is a bit of a laborious repeated
749 # mess, which could (and should) easily be parameterised.
750 # XXX also TODO: the LD/ST modes which are different
751 # https://libre-soc.org/openpower/sv/ldst/
752
753 # rright. SVP64 register numbering is from 0 to 127
754 # for GPRs, FPRs *and* CR Fields, where for v3.0 the GPRs and RPFs
755 # are 0-31 and CR Fields are only 0-7. the SVP64 RM "Extra"
756 # area is used to extend the numbering from the 32-bit
757 # instruction, and also to record whether the register
758 # is scalar or vector. on a per-operand basis. this
759 # results in a slightly finnicky encoding: here we go...
760
761 # encode SV-GPR and SV-FPR field into extra, v3.0field
762 if rtype in ['GPR', 'FPR']:
763 sv_extra, field = get_extra_gpr(etype, regmode, field)
764 # now sanity-check. EXTRA3 is ok, EXTRA2 has limits
765 # (and shrink to a single bit if ok)
766 if etype == 'EXTRA2':
767 if regmode == 'scalar':
768 # range is r0-r63 in increments of 1
769 assert (sv_extra >> 1) == 0, \
770 "scalar GPR %s cannot fit into EXTRA2 %s" % \
771 (rname, str(extras[extra_idx]))
772 # all good: encode as scalar
773 sv_extra = sv_extra & 0b01
774 else:
775 # range is r0-r127 in increments of 2 (r0 r2 ... r126)
776 assert sv_extra & 0b01 == 0, \
777 "%s: vector field %s cannot fit " \
778 "into EXTRA2 %s" % \
779 (insn, rname, str(extras[extra_idx]))
780 # all good: encode as vector (bit 2 set)
781 sv_extra = 0b10 | (sv_extra >> 1)
782 elif regmode == 'vector':
783 # EXTRA3 vector bit needs marking
784 sv_extra |= 0b100
785
786 # encode SV-CR 3-bit field into extra, v3.0field.
787 # 3-bit is for things like BF and BFA
788 elif rtype == 'CR_3bit':
789 sv_extra, field = crf_extra(etype, regmode, field, extras)
790
791 # encode SV-CR 5-bit field into extra, v3.0field
792 # 5-bit is for things like BA BB BC BT etc.
793 # *sigh* this is the same as 3-bit except the 2 LSBs of the
794 # 5-bit field are passed through unaltered.
795 elif rtype == 'CR_5bit':
796 cr_subfield = field & 0b11 # record bottom 2 bits for later
797 field = field >> 2 # strip bottom 2 bits
798 # use the exact same 3-bit function for the top 3 bits
799 sv_extra, field = crf_extra(etype, regmode, field, extras)
800 # reconstruct the actual 5-bit CR field (preserving the
801 # bottom 2 bits, unaltered)
802 field = (field << 2) | cr_subfield
803
804 else:
805 raise Exception("no type match: %s" % rtype)
806
807 # capture the extra field info
808 log("=>", "%5s" % bin(sv_extra), field)
809 extras[extra_idx] = sv_extra
810
811 # append altered field value to v3.0b, differs for LDST
812 # note that duplicates are skipped e.g. EXTRA2 contains
813 # *BOTH* s:RA *AND* d:RA which happens on LD/ST-with-update
814 srcdest, idx, duplicate = extra_idx
815 if duplicate: # skip adding to v3.0b fields, already added
816 continue
817 if ldst_imm:
818 v30b_newfields.append(("%s(%s)" % (immed, str(field))))
819 else:
820 v30b_newfields.append(str(field))
821
822 log("new v3.0B fields", v30b_op, v30b_newfields)
823 log("extras", extras)
824
825 # rright. now we have all the info. start creating SVP64 RM
826 svp64_rm = SVP64RMFields()
827
828 # begin with EXTRA fields
829 for idx, sv_extra in extras.items():
830 log(idx)
831 if idx is None:
832 continue
833 if idx[0] == 'imm':
834 continue
835 srcdest, idx, duplicate = idx
836 if etype == 'EXTRA2':
837 svp64_rm.extra2[idx].eq(
838 SelectableInt(sv_extra, SVP64RM_EXTRA2_SPEC_SIZE))
839 else:
840 svp64_rm.extra3[idx].eq(
841 SelectableInt(sv_extra, SVP64RM_EXTRA3_SPEC_SIZE))
842
843 # identify if the op is a LD/ST. the "blegh" way. copied
844 # from power_enums. TODO, split the list _insns down.
845 is_ld = v30b_op in [
846 "lbarx", "lbz", "lbzu", "lbzux", "lbzx", # load byte
847 "ld", "ldarx", "ldbrx", "ldu", "ldux", "ldx", # load double
848 "lfs", "lfsx", "lfsu", "lfsux", # FP load single
849 "lfd", "lfdx", "lfdu", "lfdux", "lfiwzx", "lfiwax", # FP load dbl
850 "lha", "lharx", "lhau", "lhaux", "lhax", # load half
851 "lhbrx", "lhz", "lhzu", "lhzux", "lhzx", # more load half
852 "lwa", "lwarx", "lwaux", "lwax", "lwbrx", # load word
853 "lwz", "lwzcix", "lwzu", "lwzux", "lwzx", # more load word
854 ]
855 is_st = v30b_op in [
856 "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
857 "std", "stdbrx", "stdcx", "stdu", "stdux", "stdx",
858 "stfs", "stfsx", "stfsu", "stfux", # FP store sgl
859 "stfd", "stfdx", "stfdu", "stfdux", "stfiwx", # FP store dbl
860 "sth", "sthbrx", "sthcx", "sthu", "sthux", "sthx",
861 "stw", "stwbrx", "stwcx", "stwu", "stwux", "stwx",
862 ]
863 # use this to determine if the SVP64 RM format is different.
864 # see https://libre-soc.org/openpower/sv/ldst/
865 is_ldst = is_ld or is_st
866
867 # branch-conditional detection
868 is_bc = v30b_op in [
869 "bc", "bclr",
870 ]
871
872 # parts of svp64_rm
873 mmode = 0 # bit 0
874 pmask = 0 # bits 1-3
875 destwid = 0 # bits 4-5
876 srcwid = 0 # bits 6-7
877 subvl = 0 # bits 8-9
878 smask = 0 # bits 16-18 but only for twin-predication
879 mode = 0 # bits 19-23
880
881 mask_m_specified = False
882 has_pmask = False
883 has_smask = False
884
885 saturation = None
886 src_zero = 0
887 dst_zero = 0
888 sv_mode = None
889
890 mapreduce = False
891 reverse_gear = False
892 mapreduce_crm = False
893 mapreduce_svm = False
894
895 predresult = False
896 failfirst = False
897 ldst_elstride = 0
898
899 # branch-conditional bits
900 bc_all = 0
901 bc_lru = 0
902 bc_brc = 0
903 bc_svstep = 0
904 bc_vsb = 0
905 bc_vlset = 0
906 bc_vli = 0
907 bc_snz = 0
908
909 # ok let's start identifying opcode augmentation fields
910 for encmode in opmodes:
911 # predicate mask (src and dest)
912 if encmode.startswith("m="):
913 pme = encmode
914 pmmode, pmask = decode_predicate(encmode[2:])
915 smmode, smask = pmmode, pmask
916 mmode = pmmode
917 mask_m_specified = True
918 # predicate mask (dest)
919 elif encmode.startswith("dm="):
920 pme = encmode
921 pmmode, pmask = decode_predicate(encmode[3:])
922 mmode = pmmode
923 has_pmask = True
924 # predicate mask (src, twin-pred)
925 elif encmode.startswith("sm="):
926 sme = encmode
927 smmode, smask = decode_predicate(encmode[3:])
928 mmode = smmode
929 has_smask = True
930 # vec2/3/4
931 elif encmode.startswith("vec"):
932 subvl = decode_subvl(encmode[3:])
933 # elwidth
934 elif encmode.startswith("ew="):
935 destwid = decode_elwidth(encmode[3:])
936 elif encmode.startswith("sw="):
937 srcwid = decode_elwidth(encmode[3:])
938 # element-strided LD/ST
939 elif encmode == 'els':
940 ldst_elstride = 1
941 # saturation
942 elif encmode == 'sats':
943 assert sv_mode is None
944 saturation = 1
945 sv_mode = 0b10
946 elif encmode == 'satu':
947 assert sv_mode is None
948 sv_mode = 0b10
949 saturation = 0
950 # predicate zeroing
951 elif encmode == 'sz':
952 src_zero = 1
953 elif encmode == 'dz':
954 dst_zero = 1
955 # failfirst
956 elif encmode.startswith("ff="):
957 assert sv_mode is None
958 sv_mode = 0b01
959 failfirst = decode_ffirst(encmode[3:])
960 # predicate-result, interestingly same as fail-first
961 elif encmode.startswith("pr="):
962 assert sv_mode is None
963 sv_mode = 0b11
964 predresult = decode_ffirst(encmode[3:])
965 # map-reduce mode, reverse-gear
966 elif encmode == 'mrr':
967 assert sv_mode is None
968 sv_mode = 0b00
969 mapreduce = True
970 reverse_gear = True
971 # map-reduce mode
972 elif encmode == 'mr':
973 assert sv_mode is None
974 sv_mode = 0b00
975 mapreduce = True
976 elif encmode == 'crm': # CR on map-reduce
977 assert sv_mode is None
978 sv_mode = 0b00
979 mapreduce_crm = True
980 elif encmode == 'svm': # sub-vector mode
981 mapreduce_svm = True
982 elif is_bc:
983 if encmode == 'all':
984 bc_all = 1
985 elif encmode == 'st': # svstep mode
986 bc_step = 1
987 elif encmode == 'sr': # svstep BRc mode
988 bc_step = 1
989 bc_brc = 1
990 elif encmode == 'vs': # VLSET mode
991 bc_vlset = 1
992 elif encmode == 'vsi': # VLSET mode with VLI (VL inclusives)
993 bc_vlset = 1
994 bc_vli = 1
995 elif encmode == 'vsb': # VLSET mode with VSb
996 bc_vlset = 1
997 bc_vsb = 1
998 elif encmode == 'vsbi': # VLSET mode with VLI and VSb
999 bc_vlset = 1
1000 bc_vli = 1
1001 bc_vsb = 1
1002 elif encmode == 'snz': # sz (only) already set above
1003 src_zero = 1
1004 bc_snz = 1
1005 elif encmode == 'lu': # LR update mode
1006 bc_lru = 1
1007 else:
1008 raise AssertionError("unknown encmode %s" % encmode)
1009 else:
1010 raise AssertionError("unknown encmode %s" % encmode)
1011
1012 if ptype == '2P':
1013 # since m=xx takes precedence (overrides) sm=xx and dm=xx,
1014 # treat them as mutually exclusive
1015 if mask_m_specified:
1016 assert not has_smask,\
1017 "cannot have both source-mask and predicate mask"
1018 assert not has_pmask,\
1019 "cannot have both dest-mask and predicate mask"
1020 # since the default is INT predication (ALWAYS), if you
1021 # specify one CR mask, you must specify both, to avoid
1022 # mixing INT and CR reg types
1023 if has_pmask and pmmode == 1:
1024 assert has_smask, \
1025 "need explicit source-mask in CR twin predication"
1026 if has_smask and smmode == 1:
1027 assert has_pmask, \
1028 "need explicit dest-mask in CR twin predication"
1029 # sanity-check that 2Pred mask is same mode
1030 if has_pmask and has_smask:
1031 assert smmode == pmmode, \
1032 "predicate masks %s and %s must be same reg type" % \
1033 (pme, sme)
1034
1035 # sanity-check that twin-predication mask only specified in 2P mode
1036 if ptype == '1P':
1037 assert not has_smask, \
1038 "source-mask can only be specified on Twin-predicate ops"
1039 assert not has_pmask, \
1040 "dest-mask can only be specified on Twin-predicate ops"
1041
1042 # construct the mode field, doing sanity-checking along the way
1043 if mapreduce_svm:
1044 assert sv_mode == 0b00, "sub-vector mode in mapreduce only"
1045 assert subvl != 0, "sub-vector mode not possible on SUBVL=1"
1046
1047 if src_zero:
1048 assert has_smask or mask_m_specified, \
1049 "src zeroing requires a source predicate"
1050 if dst_zero:
1051 assert has_pmask or mask_m_specified, \
1052 "dest zeroing requires a dest predicate"
1053
1054 # okaaay, so there are 4 different modes, here, which will be
1055 # partly-merged-in: is_ldst is merged in with "normal", but
1056 # is_bc is so different it's done separately. likewise is_cr
1057 # (when it is done). here are the maps:
1058
1059 # for "normal" arithmetic: https://libre-soc.org/openpower/sv/normal/
1060 """
1061 | 0-1 | 2 | 3 4 | description |
1062 | --- | --- |---------|-------------------------- |
1063 | 00 | 0 | dz sz | normal mode |
1064 | 00 | 1 | 0 RG | scalar reduce mode (mapreduce), SUBVL=1 |
1065 | 00 | 1 | 1 / | parallel reduce mode (mapreduce), SUBVL=1 |
1066 | 00 | 1 | SVM RG | subvector reduce mode, SUBVL>1 |
1067 | 01 | inv | CR-bit | Rc=1: ffirst CR sel |
1068 | 01 | inv | VLi RC1 | Rc=0: ffirst z/nonz |
1069 | 10 | N | dz sz | sat mode: N=0/1 u/s |
1070 | 11 | inv | CR-bit | Rc=1: pred-result CR sel |
1071 | 11 | inv | dz RC1 | Rc=0: pred-result z/nonz |
1072 """
1073
1074 # https://libre-soc.org/openpower/sv/ldst/
1075 # for LD/ST-immediate:
1076 """
1077 | 0-1 | 2 | 3 4 | description |
1078 | --- | --- |---------|--------------------------- |
1079 | 00 | 0 | dz els | normal mode |
1080 | 00 | 1 | dz shf | shift mode |
1081 | 01 | inv | CR-bit | Rc=1: ffirst CR sel |
1082 | 01 | inv | els RC1 | Rc=0: ffirst z/nonz |
1083 | 10 | N | dz els | sat mode: N=0/1 u/s |
1084 | 11 | inv | CR-bit | Rc=1: pred-result CR sel |
1085 | 11 | inv | els RC1 | Rc=0: pred-result z/nonz |
1086 """
1087
1088 # for LD/ST-indexed (RA+RB):
1089 """
1090 | 0-1 | 2 | 3 4 | description |
1091 | --- | --- |---------|-------------------------- |
1092 | 00 | SEA | dz sz | normal mode |
1093 | 01 | SEA | dz sz | Strided (scalar only source) |
1094 | 10 | N | dz sz | sat mode: N=0/1 u/s |
1095 | 11 | inv | CR-bit | Rc=1: pred-result CR sel |
1096 | 11 | inv | dz RC1 | Rc=0: pred-result z/nonz |
1097 """
1098
1099 # and leaving out branches and cr_ops for now because they're
1100 # under development
1101 """ TODO branches and cr_ops
1102 """
1103
1104 # now create mode and (overridden) src/dst widths
1105 # XXX TODO: sanity-check bc modes
1106 if is_bc:
1107 sv_mode = ((bc_svstep << SVP64MODE.MOD2_MSB) |
1108 (bc_vlset << SVP64MODE.MOD2_LSB) |
1109 (bc_snz << SVP64MODE.BC_SNZ))
1110 srcwid = (bc_vsb << 1) | bc_lru
1111 destwid = (bc_lru << 1) | bc_all
1112
1113 else:
1114
1115 ######################################
1116 # "normal" mode
1117 if sv_mode is None:
1118 mode |= src_zero << SVP64MODE.SZ # predicate zeroing
1119 mode |= dst_zero << SVP64MODE.DZ # predicate zeroing
1120 if is_ldst:
1121 # TODO: for now, LD/ST-indexed is ignored.
1122 mode |= ldst_elstride << SVP64MODE.ELS_NORMAL # el-strided
1123 else:
1124 # TODO, reduce and subvector mode
1125 # 00 1 dz CRM reduce mode (mapreduce), SUBVL=1
1126 # 00 1 SVM CRM subvector reduce mode, SUBVL>1
1127 pass
1128 sv_mode = 0b00
1129
1130 ######################################
1131 # "mapreduce" modes
1132 elif sv_mode == 0b00:
1133 mode |= (0b1 << SVP64MODE.REDUCE) # sets mapreduce
1134 assert dst_zero == 0, "dest-zero not allowed in mapreduce mode"
1135 if reverse_gear:
1136 mode |= (0b1 << SVP64MODE.RG) # sets Reverse-gear mode
1137 if mapreduce_crm:
1138 mode |= (0b1 << SVP64MODE.CRM) # sets CRM mode
1139 assert rc_mode, "CRM only allowed when Rc=1"
1140 # bit of weird encoding to jam zero-pred or SVM mode in.
1141 # SVM mode can be enabled only when SUBVL=2/3/4 (vec2/3/4)
1142 if subvl == 0:
1143 mode |= dst_zero << SVP64MODE.DZ # predicate zeroing
1144 elif mapreduce_svm:
1145 mode |= (0b1 << SVP64MODE.SVM) # sets SVM mode
1146
1147 ######################################
1148 # "failfirst" modes
1149 elif sv_mode == 0b01:
1150 assert src_zero == 0, "dest-zero not allowed in failfirst mode"
1151 if failfirst == 'RC1':
1152 mode |= (0b1 << SVP64MODE.RC1) # sets RC1 mode
1153 mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
1154 assert rc_mode == False, "ffirst RC1 only ok when Rc=0"
1155 elif failfirst == '~RC1':
1156 mode |= (0b1 << SVP64MODE.RC1) # sets RC1 mode
1157 mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
1158 mode |= (0b1 << SVP64MODE.INV) # ... with inversion
1159 assert rc_mode == False, "ffirst RC1 only ok when Rc=0"
1160 else:
1161 assert dst_zero == 0, "dst-zero not allowed in ffirst BO"
1162 assert rc_mode, "ffirst BO only possible when Rc=1"
1163 mode |= (failfirst << SVP64MODE.BO_LSB) # set BO
1164
1165 ######################################
1166 # "saturation" modes
1167 elif sv_mode == 0b10:
1168 mode |= src_zero << SVP64MODE.SZ # predicate zeroing
1169 mode |= dst_zero << SVP64MODE.DZ # predicate zeroing
1170 mode |= (saturation << SVP64MODE.N) # signed/us saturation
1171
1172 ######################################
1173 # "predicate-result" modes. err... code-duplication from ffirst
1174 elif sv_mode == 0b11:
1175 assert src_zero == 0, "dest-zero not allowed in predresult mode"
1176 if predresult == 'RC1':
1177 mode |= (0b1 << SVP64MODE.RC1) # sets RC1 mode
1178 mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
1179 assert rc_mode == False, "pr-mode RC1 only ok when Rc=0"
1180 elif predresult == '~RC1':
1181 mode |= (0b1 << SVP64MODE.RC1) # sets RC1 mode
1182 mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
1183 mode |= (0b1 << SVP64MODE.INV) # ... with inversion
1184 assert rc_mode == False, "pr-mode RC1 only ok when Rc=0"
1185 else:
1186 assert dst_zero == 0, "dst-zero not allowed in pr-mode BO"
1187 assert rc_mode, "pr-mode BO only possible when Rc=1"
1188 mode |= (predresult << SVP64MODE.BO_LSB) # set BO
1189
1190 # whewww.... modes all done :)
1191 # now put into svp64_rm
1192 mode |= sv_mode
1193 # mode: bits 19-23
1194 svp64_rm.mode.eq(SelectableInt(mode, SVP64RM_MODE_SIZE))
1195
1196 # put in predicate masks into svp64_rm
1197 if ptype == '2P':
1198 # source pred: bits 16-18
1199 svp64_rm.smask.eq(SelectableInt(smask, SVP64RM_SMASK_SIZE))
1200 # mask mode: bit 0
1201 svp64_rm.mmode.eq(SelectableInt(mmode, SVP64RM_MMODE_SIZE))
1202 # 1-pred: bits 1-3
1203 svp64_rm.mask.eq(SelectableInt(pmask, SVP64RM_MASK_SIZE))
1204
1205 # and subvl: bits 8-9
1206 svp64_rm.subvl.eq(SelectableInt(subvl, SVP64RM_SUBVL_SIZE))
1207
1208 # put in elwidths
1209 # srcwid: bits 6-7
1210 svp64_rm.ewsrc.eq(SelectableInt(srcwid, SVP64RM_EWSRC_SIZE))
1211 # destwid: bits 4-5
1212 svp64_rm.elwidth.eq(SelectableInt(destwid, SVP64RM_ELWIDTH_SIZE))
1213
1214 # nice debug printout. (and now for something completely different)
1215 # https://youtu.be/u0WOIwlXE9g?t=146
1216 svp64_rm_value = svp64_rm.spr.value
1217 log("svp64_rm", hex(svp64_rm_value), bin(svp64_rm_value))
1218 log(" mmode 0 :", bin(mmode))
1219 log(" pmask 1-3 :", bin(pmask))
1220 log(" dstwid 4-5 :", bin(destwid))
1221 log(" srcwid 6-7 :", bin(srcwid))
1222 log(" subvl 8-9 :", bin(subvl))
1223 log(" mode 19-23:", bin(mode))
1224 offs = 2 if etype == 'EXTRA2' else 3 # 2 or 3 bits
1225 for idx, sv_extra in extras.items():
1226 if idx is None:
1227 continue
1228 if idx[0] == 'imm':
1229 continue
1230 srcdest, idx, duplicate = idx
1231 start = (10+idx*offs)
1232 end = start + offs-1
1233 log(" extra%d %2d-%2d:" % (idx, start, end),
1234 bin(sv_extra))
1235 if ptype == '2P':
1236 log(" smask 16-17:", bin(smask))
1237 log()
1238
1239 # first, construct the prefix from its subfields
1240 svp64_prefix = SVP64PrefixFields()
1241 svp64_prefix.major.eq(SelectableInt(0x1, SV64P_MAJOR_SIZE))
1242 svp64_prefix.pid.eq(SelectableInt(0b11, SV64P_PID_SIZE))
1243 svp64_prefix.rm.eq(svp64_rm.spr)
1244
1245 # fiinally yield the svp64 prefix and the thingy. v3.0b opcode
1246 rc = '.' if rc_mode else ''
1247 yield ".long 0x%08x" % svp64_prefix.insn.value
1248 log(v30b_op, v30b_newfields)
1249 # argh, sv.fmadds etc. need to be done manually
1250 if v30b_op == 'ffmadds':
1251 opcode = 59 << (32-6) # bits 0..6 (MSB0)
1252 opcode |= int(v30b_newfields[0]) << (32-11) # FRT
1253 opcode |= int(v30b_newfields[1]) << (32-16) # FRA
1254 opcode |= int(v30b_newfields[2]) << (32-21) # FRB
1255 opcode |= int(v30b_newfields[3]) << (32-26) # FRC
1256 opcode |= 0b00101 << (32-31) # bits 26-30
1257 if rc:
1258 opcode |= 1 # Rc, bit 31.
1259 yield ".long 0x%x" % opcode
1260 # argh, sv.fdmadds need to be done manually
1261 elif v30b_op == 'fdmadds':
1262 opcode = 59 << (32-6) # bits 0..6 (MSB0)
1263 opcode |= int(v30b_newfields[0]) << (32-11) # FRT
1264 opcode |= int(v30b_newfields[1]) << (32-16) # FRA
1265 opcode |= int(v30b_newfields[2]) << (32-21) # FRB
1266 opcode |= int(v30b_newfields[3]) << (32-26) # FRC
1267 opcode |= 0b01111 << (32-31) # bits 26-30
1268 if rc:
1269 opcode |= 1 # Rc, bit 31.
1270 yield ".long 0x%x" % opcode
1271 # argh, sv.ffadds etc. need to be done manually
1272 elif v30b_op == 'ffadds':
1273 opcode = 59 << (32-6) # bits 0..6 (MSB0)
1274 opcode |= int(v30b_newfields[0]) << (32-11) # FRT
1275 opcode |= int(v30b_newfields[1]) << (32-16) # FRA
1276 opcode |= int(v30b_newfields[2]) << (32-21) # FRB
1277 opcode |= 0b01101 << (32-31) # bits 26-30
1278 if rc:
1279 opcode |= 1 # Rc, bit 31.
1280 yield ".long 0x%x" % opcode
1281 # sigh have to do svstep here manually for now...
1282 elif v30b_op in ["svstep", "svstep."]:
1283 insn = 22 << (31-5) # opcode 22, bits 0-5
1284 insn |= int(v30b_newfields[0]) << (31-10) # RT , bits 6-10
1285 insn |= int(v30b_newfields[1]) << (31-22) # SVi , bits 16-22
1286 insn |= int(v30b_newfields[2]) << (31-25) # vf , bit 25
1287 insn |= 0b10011 << (31-30) # XO , bits 26..30
1288 if opcode == 'svstep.':
1289 insn |= 1 << (31-31) # Rc=1 , bit 31
1290 log("svstep", bin(insn))
1291 yield ".long 0x%x" % insn
1292 # argh, sv.fcoss etc. need to be done manually
1293 elif v30b_op in ["fcoss", "fcoss."]:
1294 insn = 59 << (31-5) # opcode 59, bits 0-5
1295 insn |= int(v30b_newfields[0]) << (31-10) # RT , bits 6-10
1296 insn |= int(v30b_newfields[1]) << (31-20) # RB , bits 16-20
1297 insn |= 0b1000101110 << (31-30) # XO , bits 21..30
1298 if opcode == 'fcoss.':
1299 insn |= 1 << (31-31) # Rc=1 , bit 31
1300 log("fcoss", bin(insn))
1301 yield ".long 0x%x" % insn
1302 else:
1303 if not v30b_op.endswith('.'):
1304 v30b_op += rc
1305 yield "%s %s" % (v30b_op, ", ".join(v30b_newfields))
1306 log("new v3.0B fields", v30b_op, v30b_newfields)
1307
1308 def translate(self, lst):
1309 for insn in lst:
1310 yield from self.translate_one(insn)
1311
1312
1313 def macro_subst(macros, txt):
1314 again = True
1315 log("subst", txt, macros)
1316 while again:
1317 again = False
1318 for macro, value in macros.items():
1319 if macro == txt:
1320 again = True
1321 replaced = txt.replace(macro, value)
1322 log("macro", txt, "replaced", replaced, macro, value)
1323 txt = replaced
1324 continue
1325 toreplace = '%s.s' % macro
1326 if toreplace == txt:
1327 again = True
1328 replaced = txt.replace(toreplace, "%s.s" % value)
1329 log("macro", txt, "replaced", replaced, toreplace, value)
1330 txt = replaced
1331 continue
1332 toreplace = '%s.v' % macro
1333 if toreplace == txt:
1334 again = True
1335 replaced = txt.replace(toreplace, "%s.v" % value)
1336 log("macro", txt, "replaced", replaced, toreplace, value)
1337 txt = replaced
1338 continue
1339 toreplace = '(%s)' % macro
1340 if toreplace in txt:
1341 again = True
1342 replaced = txt.replace(toreplace, '(%s)' % value)
1343 log("macro", txt, "replaced", replaced, toreplace, value)
1344 txt = replaced
1345 continue
1346 log(" processed", txt)
1347 return txt
1348
1349
1350 def get_ws(line):
1351 # find whitespace
1352 ws = ''
1353 while line:
1354 if not line[0].isspace():
1355 break
1356 ws += line[0]
1357 line = line[1:]
1358 return ws, line
1359
1360
1361 def asm_process():
1362 # get an input file and an output file
1363 args = sys.argv[1:]
1364 if len(args) == 0:
1365 infile = sys.stdin
1366 outfile = sys.stdout
1367 # read the whole lot in advance in case of in-place
1368 lines = list(infile.readlines())
1369 elif len(args) != 2:
1370 print("pysvp64asm [infile | -] [outfile | -]", file=sys.stderr)
1371 exit(0)
1372 else:
1373 if args[0] == '--':
1374 infile = sys.stdin
1375 else:
1376 infile = open(args[0], "r")
1377 # read the whole lot in advance in case of in-place overwrite
1378 lines = list(infile.readlines())
1379
1380 if args[1] == '--':
1381 outfile = sys.stdout
1382 else:
1383 outfile = open(args[1], "w")
1384
1385 # read the line, look for custom insn, process it
1386 macros = {} # macros which start ".set"
1387 isa = SVP64Asm([])
1388 for line in lines:
1389 op = line.split("#")[0].strip()
1390 # identify macros
1391 if op.startswith(".set"):
1392 macro = op[4:].split(",")
1393 (macro, value) = map(str.strip, macro)
1394 macros[macro] = value
1395 if not op.startswith('sv.') and not op.startswith(tuple(CUSTOM_INSNS)):
1396 outfile.write(line)
1397 continue
1398
1399 (ws, line) = get_ws(line)
1400 lst = isa.translate_one(op, macros)
1401 lst = '; '.join(lst)
1402 outfile.write("%s%s # %s\n" % (ws, lst, op))
1403
1404
1405 if __name__ == '__main__':
1406 lst = ['slw 3, 1, 4',
1407 'extsw 5, 3',
1408 'sv.extsw 5, 3',
1409 'sv.cmpi 5, 1, 3, 2',
1410 'sv.setb 5, 31',
1411 'sv.isel 64.v, 3, 2, 65.v',
1412 'sv.setb/dm=r3/sm=1<<r3 5, 31',
1413 'sv.setb/m=r3 5, 31',
1414 'sv.setb/vec2 5, 31',
1415 'sv.setb/sw=8/ew=16 5, 31',
1416 'sv.extsw./ff=eq 5, 31',
1417 'sv.extsw./satu/sz/dz/sm=r3/dm=r3 5, 31',
1418 'sv.extsw./pr=eq 5.v, 31',
1419 'sv.add. 5.v, 2.v, 1.v',
1420 'sv.add./m=r3 5.v, 2.v, 1.v',
1421 ]
1422 lst += [
1423 'sv.stw 5.v, 4(1.v)',
1424 'sv.ld 5.v, 4(1.v)',
1425 'setvl. 2, 3, 4, 0, 1, 1',
1426 'sv.setvl. 2, 3, 4, 0, 1, 1',
1427 ]
1428 lst = [
1429 "sv.stfsu 0.v, 16(4.v)",
1430 ]
1431 lst = [
1432 "sv.stfsu/els 0.v, 16(4)",
1433 ]
1434 lst = [
1435 'sv.add./mr 5.v, 2.v, 1.v',
1436 ]
1437 macros = {'win2': '50', 'win': '60'}
1438 lst = [
1439 'sv.addi win2.v, win.v, -1',
1440 'sv.add./mrr 5.v, 2.v, 1.v',
1441 #'sv.lhzsh 5.v, 11(9.v), 15',
1442 #'sv.lwzsh 5.v, 11(9.v), 15',
1443 'sv.ffmadds 6.v, 2.v, 4.v, 6.v',
1444 ]
1445 lst = [
1446 #'sv.fmadds 0.v, 8.v, 16.v, 4.v',
1447 #'sv.ffadds 0.v, 8.v, 4.v',
1448 'svremap 11, 0, 1, 2, 3, 2, 1',
1449 'svshape 8, 1, 1, 1, 0',
1450 'svshape 8, 1, 1, 1, 1',
1451 ]
1452 lst = [
1453 #'sv.lfssh 4.v, 11(8.v), 15',
1454 #'sv.lwzsh 4.v, 11(8.v), 15',
1455 #'sv.svstep. 2.v, 4, 0',
1456 #'sv.fcfids. 48.v, 64.v',
1457 'sv.fcoss. 80.v, 0.v',
1458 'sv.fcoss. 20.v, 0.v',
1459 ]
1460 lst = [
1461 'sv.bc/all 3,12,192',
1462 'sv.bclr/vsbi 3,81.v,192',
1463 'sv.ld 5.v, 4(1.v)',
1464 'sv.svstep. 2.v, 4, 0',
1465 ]
1466 lst = [
1467 'maxs 3,12,5',
1468 'maxs. 3,12,5',
1469 'avgadd 3,12,5',
1470 'absdu 3,12,5',
1471 'absds 3,12,5',
1472 'absdacu 3,12,5',
1473 'absdacs 3,12,5',
1474 'cprop 3,12,5',
1475 'svindex 0,0,1,0,0,0,0',
1476 ]
1477 lst = [
1478 'sv.svstep./m=r3 2.v, 4, 0',
1479 'ternlogi 0,0,0,0x5',
1480 'fmvis 5,65535',
1481 'fmvis 5,1',
1482 'fmvis 5,2',
1483 'fmvis 5,4',
1484 'fmvis 5,8',
1485 'fmvis 5,16',
1486 'fmvis 5,32',
1487 'fmvis 5,64',
1488 'fmvis 5,32768',
1489 ]
1490 lst = [
1491 'sv.andi. *80, *80, 1',
1492 ]
1493 isa = SVP64Asm(lst, macros=macros)
1494 log("list", list(isa))
1495 # running svp64.py is designed to test hard-coded lists
1496 # (above) - which strictly speaking should all be unit tests.
1497 # if you need to actually do assembler translation at the
1498 # commandline use "pysvp64asm" - see setup.py
1499 # XXX NO. asm_process()