src/openpower/sv/trans/svp64.py

   1 # SPDX-License-Identifier: LGPLv3+
   2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3 # Funded by NLnet http://nlnet.nl
   4
   5 """SVP64 OpenPOWER v3.0B assembly translator
   6
   7 This class takes raw svp64 assembly mnemonics (aliases excluded) and
   8 creates an EXT001-encoded "svp64 prefix" followed by a v3.0B opcode.
   9
  10 It is very simple and straightforward, the only weirdness being the
  11 extraction of the register information and conversion to v3.0B numbering.
  12
  13 Encoding format of svp64: https://libre-soc.org/openpower/sv/svp64/
  14 Bugtracker: https://bugs.libre-soc.org/show_bug.cgi?id=578
  15 """
  16
  17 import os, sys
  18 from collections import OrderedDict
  19
  20 from openpower.decoder.isa.caller import (SVP64PrefixFields, SV64P_MAJOR_SIZE,
  21                                     SV64P_PID_SIZE, SVP64RMFields,
  22                                     SVP64RM_EXTRA2_SPEC_SIZE,
  23                                     SVP64RM_EXTRA3_SPEC_SIZE,
  24                                     SVP64RM_MODE_SIZE, SVP64RM_SMASK_SIZE,
  25                                     SVP64RM_MMODE_SIZE, SVP64RM_MASK_SIZE,
  26                                     SVP64RM_SUBVL_SIZE, SVP64RM_EWSRC_SIZE,
  27                                     SVP64RM_ELWIDTH_SIZE)
  28 from openpower.decoder.pseudo.pagereader import ISA
  29 from openpower.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra
  30 from openpower.decoder.selectable_int import SelectableInt
  31 from openpower.consts import SVP64MODE
  32
  33 # for debug logging
  34 from openpower.util import log
  35
  36
  37 # decode GPR into sv extra
  38 def  get_extra_gpr(etype, regmode, field):
  39     if regmode == 'scalar':
  40         # cut into 2-bits 5-bits SS FFFFF
  41         sv_extra = field >> 5
  42         field = field & 0b11111
  43     else:
  44         # cut into 5-bits 2-bits FFFFF SS
  45         sv_extra = field & 0b11
  46         field = field >> 2
  47     return sv_extra, field
  48
  49
  50 # decode 3-bit CR into sv extra
  51 def  get_extra_cr_3bit(etype, regmode, field):
  52     if regmode == 'scalar':
  53         # cut into 2-bits 3-bits SS FFF
  54         sv_extra = field >> 3
  55         field = field & 0b111
  56     else:
  57         # cut into 3-bits 4-bits FFF SSSS but will cut 2 zeros off later
  58         sv_extra = field & 0b1111
  59         field = field >> 4
  60     return sv_extra, field
  61
  62
  63 # decodes SUBVL
  64 def decode_subvl(encoding):
  65     pmap = {'2': 0b01, '3': 0b10, '4': 0b11}
  66     assert encoding in pmap, \
  67         "encoding %s for SUBVL not recognised" % encoding
  68     return pmap[encoding]
  69
  70
  71 # decodes elwidth
  72 def decode_elwidth(encoding):
  73     pmap = {'8': 0b11, '16': 0b10, '32': 0b01}
  74     assert encoding in pmap, \
  75         "encoding %s for elwidth not recognised" % encoding
  76     return pmap[encoding]
  77
  78
  79 # decodes predicate register encoding
  80 def decode_predicate(encoding):
  81     pmap = { # integer
  82             '1<<r3': (0, 0b001),
  83             'r3'   : (0, 0b010),
  84             '~r3'   : (0, 0b011),
  85             'r10'   : (0, 0b100),
  86             '~r10'  : (0, 0b101),
  87             'r30'   : (0, 0b110),
  88             '~r30'  : (0, 0b111),
  89             # CR
  90             'lt'    : (1, 0b000),
  91             'nl'    : (1, 0b001), 'ge'    : (1, 0b001), # same value
  92             'gt'    : (1, 0b010),
  93             'ng'    : (1, 0b011), 'le'    : (1, 0b011), # same value
  94             'eq'    : (1, 0b100),
  95             'ne'    : (1, 0b101),
  96             'so'    : (1, 0b110), 'un'    : (1, 0b110), # same value
  97             'ns'    : (1, 0b111), 'nu'    : (1, 0b111), # same value
  98            }
  99     assert encoding in pmap, \
 100         "encoding %s for predicate not recognised" % encoding
 101     return pmap[encoding]
 102
 103
 104 # decodes "Mode" in similar way to BO field (supposed to, anyway)
 105 def decode_bo(encoding):
 106     pmap = { # TODO: double-check that these are the same as Branch BO
 107             'lt'    : 0b000,
 108             'nl'    : 0b001, 'ge'    : 0b001, # same value
 109             'gt'    : 0b010,
 110             'ng'    : 0b011, 'le'    : 0b011, # same value
 111             'eq'    : 0b100,
 112             'ne'    : 0b101,
 113             'so'    : 0b110, 'un'    : 0b110, # same value
 114             'ns'    : 0b111, 'nu'    : 0b111, # same value
 115            }
 116     assert encoding in pmap, \
 117         "encoding %s for BO Mode not recognised" % encoding
 118     return pmap[encoding]
 119
 120 # partial-decode fail-first mode
 121 def decode_ffirst(encoding):
 122     if encoding in ['RC1', '~RC1']:
 123         return encoding
 124     return decode_bo(encoding)
 125
 126
 127 def decode_reg(field):
 128     # decode the field number. "5.v" or "3.s" or "9"
 129     field = field.split(".")
 130     regmode = 'scalar' # default
 131     if len(field) == 2:
 132         if field[1] == 's':
 133             regmode = 'scalar'
 134         elif field[1] == 'v':
 135             regmode = 'vector'
 136     field = int(field[0]) # actual register number
 137     return field, regmode
 138
 139
 140 def decode_imm(field):
 141     ldst_imm = "(" in field and field[-1] == ')'
 142     if ldst_imm:
 143         return field[:-1].split("(")
 144     else:
 145         return None, field
 146
 147 # decodes svp64 assembly listings and creates EXT001 svp64 prefixes
 148 class SVP64Asm:
 149     def __init__(self, lst, bigendian=False):
 150         self.lst = lst
 151         self.trans = self.translate(lst)
 152         assert bigendian == False, "error, bigendian not supported yet"
 153
 154     def __iter__(self):
 155         yield from self.trans
 156
 157     def translate(self, lst):
 158         isa = ISA() # reads the v3.0B pseudo-code markdown files
 159         svp64 = SVP64RM() # reads the svp64 Remap entries for registers
 160         for insn in lst:
 161             # find first space, to get opcode
 162             ls = insn.split(' ')
 163             opcode = ls[0]
 164             # now find opcode fields
 165             fields = ''.join(ls[1:]).split(',')
 166             fields = list(map(str.strip, fields))
 167             log ("opcode, fields", ls, opcode, fields)
 168
 169             # sigh have to do setvl here manually for now...
 170             if opcode in ["setvl", "setvl."]:
 171                 insn = 22 << (31-5)          # opcode 22, bits 0-5
 172                 fields = list(map(int, fields))
 173                 insn |= fields[0] << (31-10) # RT       , bits 6-10
 174                 insn |= fields[1] << (31-15) # RA       , bits 11-15
 175                 insn |= fields[2] << (31-23) # SVi      , bits 16-23
 176                 insn |= fields[3] << (31-24) # vs       , bit  24
 177                 insn |= fields[4] << (31-25) # ms       , bit  25
 178                 insn |= 0b00000   << (31-30) # XO       , bits 26..30
 179                 if opcode == 'setvl.':
 180                     insn |= 1 << (31-31)     # Rc=1     , bit 31
 181                 log ("setvl", bin(insn))
 182                 yield ".long 0x%x" % insn
 183                 continue
 184
 185             # identify if is a svp64 mnemonic
 186             if not opcode.startswith('sv.'):
 187                 yield insn  # unaltered
 188                 continue
 189             opcode = opcode[3:] # strip leading "sv"
 190
 191             # start working on decoding the svp64 op: sv.basev30Bop/vec2/mode
 192             opmodes = opcode.split("/") # split at "/"
 193             v30b_op = opmodes.pop(0)    # first is the v3.0B
 194             # check instruction ends with dot
 195             rc_mode = v30b_op.endswith('.')
 196             if rc_mode:
 197                 v30b_op = v30b_op[:-1]
 198
 199             if v30b_op not in isa.instr:
 200                 raise Exception("opcode %s of '%s' not supported" % \
 201                                 (v30b_op, insn))
 202             if v30b_op not in svp64.instrs:
 203                 raise Exception("opcode %s of '%s' not an svp64 instruction" % \
 204                                 (v30b_op, insn))
 205             v30b_regs = isa.instr[v30b_op].regs[0] # get regs info "RT, RA, RB"
 206             rm = svp64.instrs[v30b_op]             # one row of the svp64 RM CSV
 207             log ("v3.0B op", v30b_op, "Rc=1" if rc_mode else '')
 208             log ("v3.0B regs", opcode, v30b_regs)
 209             log ("RM", rm)
 210
 211             # right.  the first thing to do is identify the ordering of
 212             # the registers, by name.  the EXTRA2/3 ordering is in
 213             # rm['0']..rm['3'] but those fields contain the names RA, BB
 214             # etc.  we have to read the pseudocode to understand which
 215             # reg is which in our instruction. sigh.
 216
 217             # first turn the svp64 rm into a "by name" dict, recording
 218             # which position in the RM EXTRA it goes into
 219             # also: record if the src or dest was a CR, for sanity-checking
 220             # (elwidth overrides on CRs are banned)
 221             decode = decode_extra(rm)
 222             dest_reg_cr, src_reg_cr, svp64_src, svp64_dest = decode
 223
 224             log ("EXTRA field index, src", svp64_src)
 225             log ("EXTRA field index, dest", svp64_dest)
 226
 227             # okaaay now we identify the field value (opcode N,N,N) with
 228             # the pseudo-code info (opcode RT, RA, RB)
 229             assert len(fields) == len(v30b_regs), \
 230                 "length of fields %s must match insn `%s`" % \
 231                         (str(v30b_regs), insn)
 232             opregfields = zip(fields, v30b_regs) # err that was easy
 233
 234             # now for each of those find its place in the EXTRA encoding
 235             # note there is the possibility (for LD/ST-with-update) of
 236             # RA occurring **TWICE**.  to avoid it getting added to the
 237             # v3.0B suffix twice, we spot it as a duplicate, here
 238             extras = OrderedDict()
 239             for idx, (field, regname) in enumerate(opregfields):
 240                 imm, regname = decode_imm(regname)
 241                 rtype = get_regtype(regname)
 242                 log ("    idx find", idx, field, regname, imm)
 243                 extra = svp64_src.get(regname, None)
 244                 if extra is not None:
 245                     extra = ('s', extra, False) # not a duplicate
 246                     extras[extra] = (idx, field, regname, rtype, imm)
 247                     log ("    idx src", idx, extra, extras[extra])
 248                 dextra = svp64_dest.get(regname, None)
 249                 log ("regname in", regname, dextra)
 250                 if dextra is not None:
 251                     is_a_duplicate = extra is not None # duplicate spotted
 252                     dextra = ('d', dextra, is_a_duplicate)
 253                     extras[dextra] = (idx, field, regname, rtype, imm)
 254                     log ("    idx dst", idx, extra, extras[dextra])
 255
 256             # great! got the extra fields in their associated positions:
 257             # also we know the register type. now to create the EXTRA encodings
 258             etype = rm['Etype'] # Extra type: EXTRA3/EXTRA2
 259             ptype = rm['Ptype'] # Predication type: Twin / Single
 260             extra_bits = 0
 261             v30b_newfields = []
 262             for extra_idx, (idx, field, rname, rtype, iname) in extras.items():
 263                 # is it a field we don't alter/examine?  if so just put it
 264                 # into newfields
 265                 if rtype is None:
 266                     v30b_newfields.append(field)
 267
 268                 # identify if this is a ld/st immediate(reg) thing
 269                 ldst_imm = "(" in field and field[-1] == ')'
 270                 if ldst_imm:
 271                     immed, field = field[:-1].split("(")
 272
 273                 field, regmode = decode_reg(field)
 274                 log ("    ", extra_idx, rname, rtype,
 275                                regmode, iname, field, end=" ")
 276
 277                 # see Mode field https://libre-soc.org/openpower/sv/svp64/
 278                 # XXX TODO: the following is a bit of a laborious repeated
 279                 # mess, which could (and should) easily be parameterised.
 280                 # XXX also TODO: the LD/ST modes which are different
 281                 # https://libre-soc.org/openpower/sv/ldst/
 282
 283                 # encode SV-GPR and SV-FPR field into extra, v3.0field
 284                 if rtype in ['GPR', 'FPR']:
 285                     sv_extra, field = get_extra_gpr(etype, regmode, field)
 286                     # now sanity-check. EXTRA3 is ok, EXTRA2 has limits
 287                     # (and shrink to a single bit if ok)
 288                     if etype == 'EXTRA2':
 289                         if regmode == 'scalar':
 290                             # range is r0-r63 in increments of 1
 291                             assert (sv_extra >> 1) == 0, \
 292                                 "scalar GPR %s cannot fit into EXTRA2 %s" % \
 293                                     (rname, str(extras[extra_idx]))
 294                             # all good: encode as scalar
 295                             sv_extra = sv_extra & 0b01
 296                         else:
 297                             # range is r0-r127 in increments of 4
 298                             assert sv_extra & 0b01 == 0, \
 299                                 "%s: vector field %s cannot fit " \
 300                                 "into EXTRA2 %s" % \
 301                                     (insn, rname, str(extras[extra_idx]))
 302                             # all good: encode as vector (bit 2 set)
 303                             sv_extra = 0b10 | (sv_extra >> 1)
 304                     elif regmode == 'vector':
 305                         # EXTRA3 vector bit needs marking
 306                         sv_extra |= 0b100
 307
 308                 # encode SV-CR 3-bit field into extra, v3.0field
 309                 elif rtype == 'CR_3bit':
 310                     sv_extra, field = get_extra_cr_3bit(etype, regmode, field)
 311                     # now sanity-check (and shrink afterwards)
 312                     if etype == 'EXTRA2':
 313                         if regmode == 'scalar':
 314                             # range is CR0-CR15 in increments of 1
 315                             assert (sv_extra >> 1) == 0, \
 316                                 "scalar CR %s cannot fit into EXTRA2 %s" % \
 317                                     (rname, str(extras[extra_idx]))
 318                             # all good: encode as scalar
 319                             sv_extra = sv_extra & 0b01
 320                         else:
 321                             # range is CR0-CR127 in increments of 16
 322                             assert sv_extra & 0b111 == 0, \
 323                                 "vector CR %s cannot fit into EXTRA2 %s" % \
 324                                     (rname, str(extras[extra_idx]))
 325                             # all good: encode as vector (bit 2 set)
 326                             sv_extra = 0b10 | (sv_extra >> 3)
 327                     else:
 328                         if regmode == 'scalar':
 329                             # range is CR0-CR31 in increments of 1
 330                             assert (sv_extra >> 2) == 0, \
 331                                 "scalar CR %s cannot fit into EXTRA2 %s" % \
 332                                     (rname, str(extras[extra_idx]))
 333                             # all good: encode as scalar
 334                             sv_extra = sv_extra & 0b11
 335                         else:
 336                             # range is CR0-CR127 in increments of 8
 337                             assert sv_extra & 0b11 == 0, \
 338                                 "vector CR %s cannot fit into EXTRA2 %s" % \
 339                                     (rname, str(extras[extra_idx]))
 340                             # all good: encode as vector (bit 3 set)
 341                             sv_extra = 0b100 | (sv_extra >> 2)
 342
 343                 # encode SV-CR 5-bit field into extra, v3.0field
 344                 # *sigh* this is the same as 3-bit except the 2 LSBs are
 345                 # passed through
 346                 elif rtype == 'CR_5bit':
 347                     cr_subfield = field & 0b11
 348                     field = field >> 2 # strip bottom 2 bits
 349                     sv_extra, field = get_extra_cr_3bit(etype, regmode, field)
 350                     # now sanity-check (and shrink afterwards)
 351                     if etype == 'EXTRA2':
 352                         if regmode == 'scalar':
 353                             # range is CR0-CR15 in increments of 1
 354                             assert (sv_extra >> 1) == 0, \
 355                                 "scalar CR %s cannot fit into EXTRA2 %s" % \
 356                                     (rname, str(extras[extra_idx]))
 357                             # all good: encode as scalar
 358                             sv_extra = sv_extra & 0b01
 359                         else:
 360                             # range is CR0-CR127 in increments of 16
 361                             assert sv_extra & 0b111 == 0, \
 362                                 "vector CR %s cannot fit into EXTRA2 %s" % \
 363                                     (rname, str(extras[extra_idx]))
 364                             # all good: encode as vector (bit 2 set)
 365                             sv_extra = 0b10 | (sv_extra >> 3)
 366                     else:
 367                         if regmode == 'scalar':
 368                             # range is CR0-CR31 in increments of 1
 369                             assert (sv_extra >> 2) == 0, \
 370                                 "scalar CR %s cannot fit into EXTRA2 %s" % \
 371                                     (rname, str(extras[extra_idx]))
 372                             # all good: encode as scalar
 373                             sv_extra = sv_extra & 0b11
 374                         else:
 375                             # range is CR0-CR127 in increments of 8
 376                             assert sv_extra & 0b11 == 0, \
 377                                 "vector CR %s cannot fit into EXTRA2 %s" % \
 378                                     (rname, str(extras[extra_idx]))
 379                             # all good: encode as vector (bit 3 set)
 380                             sv_extra = 0b100 | (sv_extra >> 2)
 381
 382                     # reconstruct the actual 5-bit CR field
 383                     field = (field << 2) | cr_subfield
 384
 385                 # capture the extra field info
 386                 log ("=>", "%5s" % bin(sv_extra), field)
 387                 extras[extra_idx] = sv_extra
 388
 389                 # append altered field value to v3.0b, differs for LDST
 390                 # note that duplicates are skipped e.g. EXTRA2 contains
 391                 # *BOTH* s:RA *AND* d:RA which happens on LD/ST-with-update
 392                 srcdest, idx, duplicate = extra_idx
 393                 if duplicate: # skip adding to v3.0b fields, already added
 394                     continue
 395                 if ldst_imm:
 396                     v30b_newfields.append(("%s(%s)" % (immed, str(field))))
 397                 else:
 398                     v30b_newfields.append(str(field))
 399
 400             log ("new v3.0B fields", v30b_op, v30b_newfields)
 401             log ("extras", extras)
 402
 403             # rright.  now we have all the info. start creating SVP64 RM
 404             svp64_rm = SVP64RMFields()
 405
 406             # begin with EXTRA fields
 407             for idx, sv_extra in extras.items():
 408                 if idx is None: continue
 409                 log (idx)
 410                 srcdest, idx, duplicate = idx
 411                 if etype == 'EXTRA2':
 412                     svp64_rm.extra2[idx].eq(
 413                         SelectableInt(sv_extra, SVP64RM_EXTRA2_SPEC_SIZE))
 414                 else:
 415                     svp64_rm.extra3[idx].eq(
 416                         SelectableInt(sv_extra, SVP64RM_EXTRA3_SPEC_SIZE))
 417
 418             # parts of svp64_rm
 419             mmode = 0  # bit 0
 420             pmask = 0  # bits 1-3
 421             destwid = 0 # bits 4-5
 422             srcwid = 0 # bits 6-7
 423             subvl = 0   # bits 8-9
 424             smask = 0 # bits 16-18 but only for twin-predication
 425             mode = 0 # bits 19-23
 426
 427             mask_m_specified = False
 428             has_pmask = False
 429             has_smask = False
 430
 431             saturation = None
 432             src_zero = 0
 433             dst_zero = 0
 434             sv_mode = None
 435
 436             mapreduce = False
 437             mapreduce_crm = False
 438             mapreduce_svm = False
 439
 440             predresult = False
 441             failfirst = False
 442
 443             # ok let's start identifying opcode augmentation fields
 444             for encmode in opmodes:
 445                 # predicate mask (src and dest)
 446                 if encmode.startswith("m="):
 447                     pme = encmode
 448                     pmmode, pmask = decode_predicate(encmode[2:])
 449                     smmode, smask = pmmode, pmask
 450                     mmode = pmmode
 451                     mask_m_specified = True
 452                 # predicate mask (dest)
 453                 elif encmode.startswith("dm="):
 454                     pme = encmode
 455                     pmmode, pmask = decode_predicate(encmode[3:])
 456                     mmode = pmmode
 457                     has_pmask = True
 458                 # predicate mask (src, twin-pred)
 459                 elif encmode.startswith("sm="):
 460                     sme = encmode
 461                     smmode, smask = decode_predicate(encmode[3:])
 462                     mmode = smmode
 463                     has_smask = True
 464                 # vec2/3/4
 465                 elif encmode.startswith("vec"):
 466                     subvl = decode_subvl(encmode[3:])
 467                 # elwidth
 468                 elif encmode.startswith("ew="):
 469                     destwid = decode_elwidth(encmode[3:])
 470                 elif encmode.startswith("sw="):
 471                     srcwid = decode_elwidth(encmode[3:])
 472                 # saturation
 473                 elif encmode == 'sats':
 474                     assert sv_mode is None
 475                     saturation = 1
 476                     sv_mode = 0b10
 477                 elif encmode == 'satu':
 478                     assert sv_mode is None
 479                     sv_mode = 0b10
 480                     saturation = 0
 481                 # predicate zeroing
 482                 elif encmode == 'sz':
 483                     src_zero = 1
 484                 elif encmode == 'dz':
 485                     dst_zero = 1
 486                 # failfirst
 487                 elif encmode.startswith("ff="):
 488                     assert sv_mode is None
 489                     sv_mode = 0b01
 490                     failfirst = decode_ffirst(encmode[3:])
 491                 # predicate-result, interestingly same as fail-first
 492                 elif encmode.startswith("pr="):
 493                     assert sv_mode is None
 494                     sv_mode = 0b11
 495                     predresult = decode_ffirst(encmode[3:])
 496                 # map-reduce mode
 497                 elif encmode == 'mr':
 498                     assert sv_mode is None
 499                     sv_mode = 0b00
 500                     mapreduce = True
 501                 elif encmode == 'crm': # CR on map-reduce
 502                     assert sv_mode is None
 503                     sv_mode = 0b00
 504                     mapreduce_crm = True
 505                 elif encmode == 'svm': # sub-vector mode
 506                     mapreduce_svm = True
 507                 else:
 508                     raise AssertionError("unknown encmode %s" % encmode)
 509
 510             if ptype == '2P':
 511                 # since m=xx takes precedence (overrides) sm=xx and dm=xx,
 512                 # treat them as mutually exclusive
 513                 if mask_m_specified:
 514                     assert not has_smask,\
 515                         "cannot have both source-mask and predicate mask"
 516                     assert not has_pmask,\
 517                         "cannot have both dest-mask and predicate mask"
 518                 # since the default is INT predication (ALWAYS), if you
 519                 # specify one CR mask, you must specify both, to avoid
 520                 # mixing INT and CR reg types
 521                 if has_pmask and pmmode == 1:
 522                     assert has_smask, \
 523                         "need explicit source-mask in CR twin predication"
 524                 if has_smask and smmode == 1:
 525                     assert has_pmask, \
 526                         "need explicit dest-mask in CR twin predication"
 527                 # sanity-check that 2Pred mask is same mode
 528                 if has_pmask and has_smask:
 529                     assert smmode == pmmode, \
 530                         "predicate masks %s and %s must be same reg type" % \
 531                             (pme, sme)
 532
 533             # sanity-check that twin-predication mask only specified in 2P mode
 534             if ptype == '1P':
 535                 assert not has_smask, \
 536                     "source-mask can only be specified on Twin-predicate ops"
 537                 assert not has_pmask, \
 538                     "dest-mask can only be specified on Twin-predicate ops"
 539
 540             # construct the mode field, doing sanity-checking along the way
 541
 542             if mapreduce_svm:
 543                 assert sv_mode == 0b00, "sub-vector mode in mapreduce only"
 544                 assert subvl != 0, "sub-vector mode not possible on SUBVL=1"
 545
 546             if src_zero:
 547                 assert has_smask or mask_m_specified, \
 548                     "src zeroing requires a source predicate"
 549             if dst_zero:
 550                 assert has_pmask or mask_m_specified, \
 551                     "dest zeroing requires a dest predicate"
 552
 553             # "normal" mode
 554             if sv_mode is None:
 555                 mode |= src_zero << SVP64MODE.SZ # predicate zeroing
 556                 mode |= dst_zero << SVP64MODE.DZ # predicate zeroing
 557                 sv_mode = 0b00
 558
 559             # "mapreduce" modes
 560             elif sv_mode == 0b00:
 561                 mode |= (0b1<<SVP64MODE.REDUCE) # sets mapreduce
 562                 assert dst_zero == 0, "dest-zero not allowed in mapreduce mode"
 563                 if mapreduce_crm:
 564                     mode |= (0b1<<SVP64MODE.CRM) # sets CRM mode
 565                     assert rc_mode, "CRM only allowed when Rc=1"
 566                 # bit of weird encoding to jam zero-pred or SVM mode in.
 567                 # SVM mode can be enabled only when SUBVL=2/3/4 (vec2/3/4)
 568                 if subvl == 0:
 569                     mode |= dst_zero << SVP64MODE.DZ # predicate zeroing
 570                 elif mapreduce_svm:
 571                     mode |= (0b1<<SVP64MODE.SVM) # sets SVM mode
 572
 573             # "failfirst" modes
 574             elif sv_mode == 0b01:
 575                 assert src_zero == 0, "dest-zero not allowed in failfirst mode"
 576                 if failfirst == 'RC1':
 577                     mode |= (0b1<<SVP64MODE.RC1) # sets RC1 mode
 578                     mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
 579                     assert rc_mode==False, "ffirst RC1 only possible when Rc=0"
 580                 elif failfirst == '~RC1':
 581                     mode |= (0b1<<SVP64MODE.RC1) # sets RC1 mode
 582                     mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
 583                     mode |= (0b1<<SVP64MODE.INV) # ... with inversion
 584                     assert rc_mode==False, "ffirst RC1 only possible when Rc=0"
 585                 else:
 586                     assert dst_zero == 0, "dst-zero not allowed in ffirst BO"
 587                     assert rc_mode, "ffirst BO only possible when Rc=1"
 588                     mode |= (failfirst << SVP64MODE.BO_LSB) # set BO
 589
 590             # "saturation" modes
 591             elif sv_mode == 0b10:
 592                 mode |= src_zero << SVP64MODE.SZ # predicate zeroing
 593                 mode |= dst_zero << SVP64MODE.DZ # predicate zeroing
 594                 mode |= (saturation << SVP64MODE.N) # signed/unsigned saturation
 595
 596             # "predicate-result" modes.  err... code-duplication from ffirst
 597             elif sv_mode == 0b11:
 598                 assert src_zero == 0, "dest-zero not allowed in predresult mode"
 599                 if predresult == 'RC1':
 600                     mode |= (0b1<<SVP64MODE.RC1) # sets RC1 mode
 601                     mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
 602                     assert rc_mode==False, "pr-mode RC1 only possible when Rc=0"
 603                 elif predresult == '~RC1':
 604                     mode |= (0b1<<SVP64MODE.RC1) # sets RC1 mode
 605                     mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
 606                     mode |= (0b1<<SVP64MODE.INV) # ... with inversion
 607                     assert rc_mode==False, "pr-mode RC1 only possible when Rc=0"
 608                 else:
 609                     assert dst_zero == 0, "dst-zero not allowed in pr-mode BO"
 610                     assert rc_mode, "pr-mode BO only possible when Rc=1"
 611                     mode |= (predresult << SVP64MODE.BO_LSB) # set BO
 612
 613             # whewww.... modes all done :)
 614             # now put into svp64_rm
 615             mode |= sv_mode
 616             # mode: bits 19-23
 617             svp64_rm.mode.eq(SelectableInt(mode, SVP64RM_MODE_SIZE))
 618
 619             # put in predicate masks into svp64_rm
 620             if ptype == '2P':
 621                 # source pred: bits 16-18
 622                 svp64_rm.smask.eq(SelectableInt(smask, SVP64RM_SMASK_SIZE))
 623             # mask mode: bit 0
 624             svp64_rm.mmode.eq(SelectableInt(mmode, SVP64RM_MMODE_SIZE))
 625             # 1-pred: bits 1-3
 626             svp64_rm.mask.eq(SelectableInt(pmask, SVP64RM_MASK_SIZE))
 627
 628             # and subvl: bits 8-9
 629             svp64_rm.subvl.eq(SelectableInt(subvl, SVP64RM_SUBVL_SIZE))
 630
 631             # put in elwidths
 632             # srcwid: bits 6-7
 633             svp64_rm.ewsrc.eq(SelectableInt(srcwid, SVP64RM_EWSRC_SIZE))
 634             # destwid: bits 4-5
 635             svp64_rm.elwidth.eq(SelectableInt(destwid, SVP64RM_ELWIDTH_SIZE))
 636
 637             # nice debug printout. (and now for something completely different)
 638             # https://youtu.be/u0WOIwlXE9g?t=146
 639             svp64_rm_value = svp64_rm.spr.value
 640             log ("svp64_rm", hex(svp64_rm_value), bin(svp64_rm_value))
 641             log ("    mmode  0    :", bin(mmode))
 642             log ("    pmask  1-3  :", bin(pmask))
 643             log ("    dstwid 4-5  :", bin(destwid))
 644             log ("    srcwid 6-7  :", bin(srcwid))
 645             log ("    subvl  8-9  :", bin(subvl))
 646             log ("    mode   19-23:", bin(mode))
 647             offs = 2 if etype == 'EXTRA2' else 3 # 2 or 3 bits
 648             for idx, sv_extra in extras.items():
 649                 if idx is None: continue
 650                 srcdest, idx, duplicate = idx
 651                 start = (10+idx*offs)
 652                 end = start + offs-1
 653                 log ("    extra%d %2d-%2d:" % (idx, start, end),
 654                         bin(sv_extra))
 655             if ptype == '2P':
 656                 log ("    smask  16-17:", bin(smask))
 657             log ()
 658
 659             # first, construct the prefix from its subfields
 660             svp64_prefix = SVP64PrefixFields()
 661             svp64_prefix.major.eq(SelectableInt(0x1, SV64P_MAJOR_SIZE))
 662             svp64_prefix.pid.eq(SelectableInt(0b11, SV64P_PID_SIZE))
 663             svp64_prefix.rm.eq(svp64_rm.spr)
 664
 665             # fiinally yield the svp64 prefix and the thingy.  v3.0b opcode
 666             rc = '.' if rc_mode else ''
 667             yield ".long 0x%x" % svp64_prefix.insn.value
 668             yield "%s %s" % (v30b_op+rc, ", ".join(v30b_newfields))
 669             log ("new v3.0B fields", v30b_op, v30b_newfields)
 670
 671 if __name__ == '__main__':
 672     lst = ['slw 3, 1, 4',
 673                  'extsw 5, 3',
 674                  'sv.extsw 5, 3',
 675                  'sv.cmpi 5, 1, 3, 2',
 676                  'sv.setb 5, 31',
 677                  'sv.isel 64.v, 3, 2, 65.v',
 678                  'sv.setb/dm=r3/sm=1<<r3 5, 31',
 679                  'sv.setb/m=r3 5, 31',
 680                  'sv.setb/vec2 5, 31',
 681                  'sv.setb/sw=8/ew=16 5, 31',
 682                  'sv.extsw./ff=eq 5, 31',
 683                  'sv.extsw./satu/sz/dz/sm=r3/dm=r3 5, 31',
 684                  'sv.extsw./pr=eq 5.v, 31',
 685                  'sv.add. 5.v, 2.v, 1.v',
 686                  'sv.add./m=r3 5.v, 2.v, 1.v',
 687                 ]
 688     lst += [
 689                  'sv.stw 5.v, 4(1.v)',
 690                  'sv.ld 5.v, 4(1.v)',
 691                  'setvl. 2, 3, 4, 1, 1',
 692           ]
 693     lst = [
 694             "sv.stfsu 0.v, 16(4.v)",
 695     ]
 696     isa = SVP64Asm(lst)
 697     print ("list", list(isa))
 698     csvs = SVP64RM()