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fix wrong shift in fmvis, use correct immediates in test
[openpower-isa.git] / src / openpower / sv / trans / svp64.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Funded by NLnet http://nlnet.nl
4
5 """SVP64 OpenPOWER v3.0B assembly translator
6
7 This class takes raw svp64 assembly mnemonics (aliases excluded) and creates
8 an EXT001-encoded "svp64 prefix" (as a .long) followed by a v3.0B opcode.
9
10 It is very simple and straightforward, the only weirdness being the
11 extraction of the register information and conversion to v3.0B numbering.
12
13 Encoding format of svp64: https://libre-soc.org/openpower/sv/svp64/
14 Encoding format of arithmetic: https://libre-soc.org/openpower/sv/normal/
15 Encoding format of LDST: https://libre-soc.org/openpower/sv/ldst/
16 **TODO format of branches: https://libre-soc.org/openpower/sv/branches/**
17 **TODO format of CRs: https://libre-soc.org/openpower/sv/cr_ops/**
18 Bugtracker: https://bugs.libre-soc.org/show_bug.cgi?id=578
19 """
20
21 import functools
22 import os
23 import sys
24 from collections import OrderedDict
25
26 from openpower.decoder.isa.caller import (SVP64PrefixFields, SV64P_MAJOR_SIZE,
27 SV64P_PID_SIZE, SVP64RMFields,
28 SVP64RM_EXTRA2_SPEC_SIZE,
29 SVP64RM_EXTRA3_SPEC_SIZE,
30 SVP64RM_MODE_SIZE,
31 SVP64RM_SMASK_SIZE,
32 SVP64RM_MMODE_SIZE,
33 SVP64RM_MASK_SIZE,
34 SVP64RM_SUBVL_SIZE,
35 SVP64RM_EWSRC_SIZE,
36 SVP64RM_ELWIDTH_SIZE)
37 from openpower.decoder.pseudo.pagereader import ISA
38 from openpower.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra
39 from openpower.decoder.selectable_int import SelectableInt
40 from openpower.consts import SVP64MODE
41
42 # for debug logging
43 from openpower.util import log
44
45
46 def instruction(*fields):
47 def instruction(insn, desc):
48 (value, start, end) = desc
49 bits = ((1,) * ((end + 1) - start))
50 mask = 0
51 for bit in bits:
52 mask = ((mask << 1) | bit)
53 return (insn | ((value & mask) << (31 - end)))
54
55 return functools.reduce(instruction, fields, 0)
56
57
58 def setvl(fields, Rc):
59 """
60 setvl is a *32-bit-only* instruction. It controls SVSTATE.
61 It is *not* a 64-bit-prefixed Vector instruction (no sv.setvl, yet),
62 it is a Vector *control* instruction.
63
64 * setvl RT,RA,SVi,vf,vs,ms
65
66 1.6.28 SVL-FORM - from fields.txt
67 |0 |6 |11 |16 |23 |24 |25 |26 |31 |
68 | PO | RT | RA | SVi |ms |vs |vf | XO |Rc |
69 """
70 PO = 22
71 XO = 0b11011
72 # ARRRGH these are in a non-obvious order in openpower/isa/simplev.mdwn
73 # compared to the SVL-Form above. sigh
74 # setvl RT,RA,SVi,vf,vs,ms
75 (RT, RA, SVi, vf, vs, ms) = fields
76 SVi -= 1
77 return instruction(
78 (PO , 0 , 5 ),
79 (RT , 6 , 10),
80 (RA , 11, 15),
81 (SVi, 16, 22),
82 (ms , 23, 23),
83 (vs , 24, 24),
84 (vf , 25, 25),
85 (XO , 26, 30),
86 (Rc , 31, 31),
87 )
88
89
90 def svstep(fields, Rc):
91 """
92 svstep is a 32-bit instruction. It updates SVSTATE.
93 It *can* be SVP64-prefixed, to indicate that its registers
94 are Vectorised.
95
96 * svstep RT,SVi,vf
97
98 # 1.6.28 SVL-FORM - from fields.txt
99 # |0 |6 |11 |16 |23 |24 |25 |26 |31 |
100 # | PO | RT | / | SVi |/ |/ |vf | XO |Rc |
101
102 """
103 PO = 22
104 XO = 0b10011
105 (RT, SVi, vf) = fields
106 SVi -= 1
107 return instruction(
108 (PO , 0 , 5 ),
109 (RT , 6 , 10),
110 (0 , 11, 15),
111 (SVi, 16, 22),
112 (0 , 23, 23),
113 (0 , 24, 24),
114 (vf , 25, 25),
115 (XO , 26, 30),
116 (Rc , 31, 31),
117 )
118
119
120 def svshape(fields):
121 """
122 svshape is a *32-bit-only* instruction. It updates SVSHAPE and SVSTATE.
123 It is *not* a 64-bit-prefixed Vector instruction (no sv.svshape, yet),
124 it is a Vector *control* instruction.
125
126 * svshape SVxd,SVyd,SVzd,SVrm,vf
127
128 # 1.6.33 SVM-FORM from fields.txt
129 # |0 |6 |11 |16 |21 |25 |26 |31 |
130 # | PO | SVxd | SVyd | SVzd | SVrm |vf | XO |
131
132 """
133 PO = 22
134 XO = 0b011001
135 (SVxd, SVyd, SVzd, SVrm, vf) = fields
136 SVxd -= 1
137 SVyd -= 1
138 SVzd -= 1
139 return instruction(
140 (PO , 0 , 5 ),
141 (SVxd, 6 , 10),
142 (SVyd, 11, 15),
143 (SVzd, 16, 20),
144 (SVrm, 21, 24),
145 (vf , 25, 25),
146 (XO , 26, 31),
147 )
148
149
150 def svindex(fields):
151 """
152 svindex is a *32-bit-only* instruction. It is a convenience
153 instruction that reduces instruction count for Indexed REMAP
154 Mode.
155 It is *not* a 64-bit-prefixed Vector instruction (no sv.svindex, yet),
156 it is a Vector *control* instruction.
157
158 1.6.28 SVI-FORM
159 |0 |6 |11 |16 |21 |23|24|25|26 31|
160 | PO | SVG|rmm | SVd |ew |yx|mm|sk| XO |
161 """
162 # note that the dimension field one subtracted
163 PO = 22
164 XO = 0b101001
165 (SVG, rmm, SVd, ew, yx, mm, sk) = fields
166 SVd -= 1
167 return instruction(
168 (PO , 0 , 5 ),
169 (SVG, 6 , 10),
170 (rmm, 11, 15),
171 (SVd, 16, 20),
172 (ew , 21, 22),
173 (yx , 23, 23),
174 (mm , 24, 24),
175 (sk , 25, 25),
176 (XO , 26, 31),
177 )
178
179
180 def svremap(fields):
181 """
182 this is a *32-bit-only* instruction. It updates the SVSHAPE SPR
183 it is *not* a 64-bit-prefixed Vector instruction (no sv.svremap),
184 it is a Vector *control* instruction.
185
186 * svremap SVme,mi0,mi1,mi2,mo0,mo1,pst
187
188 # 1.6.34 SVRM-FORM
189 |0 |6 |11 |13 |15 |17 |19 |21 |22 |26 |31 |
190 | PO | SVme |mi0 | mi1 | mi2 | mo0 | mo1 |pst |/// | XO |
191
192 """
193 PO = 22
194 XO = 0b111001
195 (SVme, mi0, mi1, mi2, mo0, mo1, pst) = fields
196 return instruction(
197 (PO , 0 , 5 ),
198 (SVme, 6 , 10),
199 (mi0 , 11, 12),
200 (mi1 , 13, 14),
201 (mi2 , 15, 16),
202 (mo0 , 17, 18),
203 (mo1 , 19, 20),
204 (pst , 21, 21),
205 (0 , 22, 25),
206 (XO , 26, 31),
207 )
208
209
210 # ok from here-on down these are added as 32-bit instructions
211 # and are here only because binutils (at present) doesn't have
212 # them (that's being fixed!)
213 # they can - if implementations then choose - be Vectorised
214 # because they are general-purpose scalar instructions
215 def bmask(fields):
216 """
217 1.6.2.2 BM2-FORM
218 |0 |6 |11 |16 |21 |26 |27 31|
219 | PO | RT | RA | RB |bm |L | XO |
220 """
221 PO = 22
222 XO = 0b010001
223 (RT, RA, RB, bm, L) = fields
224 return instruction(
225 (PO, 0 , 5 ),
226 (RT, 6 , 10),
227 (RA, 11, 15),
228 (RB, 16, 20),
229 (bm, 21, 25),
230 (L , 26, 26),
231 (XO, 27, 31),
232 )
233
234
235 def fsins(fields, Rc):
236 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
237 # however we are out of space with opcode 22
238 # 1.6.7 X-FORM
239 # |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 |
240 # | PO | FRT | /// | FRB | XO |Rc |
241 PO = 59
242 XO = 0b1000001110
243 (FRT, FRB) = fields
244 return instruction(
245 (PO , 0 , 5 ),
246 (FRT, 6 , 10),
247 (0 , 11, 15),
248 (FRB, 16, 20),
249 (XO , 21, 30),
250 (Rc , 31, 31),
251 )
252
253
254 def fcoss(fields, Rc):
255 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
256 # however we are out of space with opcode 22
257 # 1.6.7 X-FORM
258 # |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 |
259 # | PO | FRT | /// | FRB | XO |Rc |
260 PO = 59
261 XO = 0b1000101110
262 (FRT, FRB) = fields
263 return instruction(
264 (PO , 0 , 5 ),
265 (FRT, 6 , 10),
266 (0 , 11, 15),
267 (FRB, 16, 20),
268 (XO , 21, 30),
269 (Rc , 31, 31),
270 )
271
272
273 def ternlogi(fields, Rc):
274 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
275 # however we are out of space with opcode 22
276 # 1.6.34 TLI-FORM
277 # |0 |6 |11 |16 |21 |29 |31 |
278 # | PO | RT | RA | RB | TLI | XO |Rc |
279 PO = 5
280 XO = 0
281 (RT, RA, RB, TLI) = fields
282 return instruction(
283 (PO , 0 , 5 ),
284 (RT , 6 , 10),
285 (RA , 11, 15),
286 (RB , 16, 20),
287 (TLI, 21, 28),
288 (XO , 29, 30),
289 (Rc , 31, 31),
290 )
291
292
293 def grev(fields, Rc, imm, wide):
294 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
295 # however we are out of space with opcode 22
296 insn = PO = 5
297 # _ matches fields in table at:
298 # https://libre-soc.org/openPOwer/sv/bitmanip/
299 XO = 0b1_0010_110
300 if wide:
301 XO |= 0b100_000
302 if imm:
303 XO |= 0b1000_000
304 (RT, RA, XBI) = fields
305 insn = (insn << 5) | RT
306 insn = (insn << 5) | RA
307 if imm and not wide:
308 assert 0 <= XBI < 64
309 insn = (insn << 6) | XBI
310 insn = (insn << 9) | XO
311 else:
312 assert 0 <= XBI < 32
313 insn = (insn << 5) | XBI
314 insn = (insn << 10) | XO
315 insn = (insn << 1) | Rc
316 return insn
317
318
319 def av(fields, XO, Rc):
320 # 1.6.7 X-FORM
321 # |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 |
322 # | PO | RT | RA | RB | XO |Rc |
323 PO = 22
324 (RT, RA, RB) = fields
325 return instruction(
326 (PO, 0 , 5 ),
327 (RT, 6 , 10),
328 (RA, 11, 15),
329 (RB, 16, 20),
330 (XO, 21, 30),
331 (Rc, 31, 31),
332 )
333
334
335 def fmvis(fields):
336 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
337 # V3.0B 1.6.6 DX-FORM
338 # |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |26|27 |31 |
339 # | PO | FRS | d1 | d0 | XO |d2 |
340 PO = 22
341 XO = 0b00011
342 Rc = 0
343 (FRS, imm) = fields
344 # first split imm into d1, d0 and d2. sigh
345 d2 = (imm & 1) # LSB (0)
346 d1 = (imm >> 1) & 0b11111 # bits 1-5
347 d0 = (imm >> 5) # MSBs 6-15
348 return instruction(
349 (PO , 0 , 5),
350 (FRS, 6 , 10),
351 (d1, 11, 15),
352 (d0, 16, 26),
353 (XO , 27, 30),
354 (d2 , 31, 31),
355 )
356
357
358 CUSTOM_INSNS = {}
359 for (name, hook) in (
360 ("setvl", setvl),
361 ("svstep", svstep),
362 ("fsins", fsins),
363 ("fcoss", fcoss),
364 ("ternlogi", ternlogi),
365 ):
366 CUSTOM_INSNS[name] = functools.partial(hook, Rc=False)
367 CUSTOM_INSNS[f"{name}."] = functools.partial(hook, Rc=True)
368 CUSTOM_INSNS["bmask"] = bmask
369 CUSTOM_INSNS["svshape"] = svshape
370 CUSTOM_INSNS["svindex"] = svindex
371 CUSTOM_INSNS["svremap"] = svremap
372 CUSTOM_INSNS["fmvis"] = fmvis
373
374 for (name, imm, wide) in (
375 ("grev", False, False),
376 ("grevi", True, False),
377 ("grevw", False, True),
378 ("grevwi", True, True),
379 ):
380 CUSTOM_INSNS[name] = functools.partial(grev,
381 imm=("i" in name), wide=("w" in name), Rc=False)
382 CUSTOM_INSNS[f"{name}."] = functools.partial(grev,
383 imm=("i" in name), wide=("w" in name), Rc=True)
384
385 for (name, XO) in (
386 ("maxs" , 0b0111001110),
387 ("maxu" , 0b0011001110),
388 ("minu" , 0b0001001110),
389 ("mins" , 0b0101001110),
390 ("absdu" , 0b1011110110),
391 ("absds" , 0b1001110110),
392 ("avgadd" , 0b1101001110),
393 ("absdacu", 0b1111110110),
394 ("absdacs", 0b0111110110),
395 ("cprop" , 0b0110001110),
396 ):
397 CUSTOM_INSNS[name] = functools.partial(av, XO=XO, Rc=False)
398 CUSTOM_INSNS[f"{name}."] = functools.partial(av, XO=XO, Rc=True)
399
400
401 # decode GPR into sv extra
402 def get_extra_gpr(etype, regmode, field):
403 if regmode == 'scalar':
404 # cut into 2-bits 5-bits SS FFFFF
405 sv_extra = field >> 5
406 field = field & 0b11111
407 else:
408 # cut into 5-bits 2-bits FFFFF SS
409 sv_extra = field & 0b11
410 field = field >> 2
411 return sv_extra, field
412
413
414 # decode 3-bit CR into sv extra
415 def get_extra_cr_3bit(etype, regmode, field):
416 if regmode == 'scalar':
417 # cut into 2-bits 3-bits SS FFF
418 sv_extra = field >> 3
419 field = field & 0b111
420 else:
421 # cut into 3-bits 4-bits FFF SSSS but will cut 2 zeros off later
422 sv_extra = field & 0b1111
423 field = field >> 4
424 return sv_extra, field
425
426
427 # decodes SUBVL
428 def decode_subvl(encoding):
429 pmap = {'2': 0b01, '3': 0b10, '4': 0b11}
430 assert encoding in pmap, \
431 "encoding %s for SUBVL not recognised" % encoding
432 return pmap[encoding]
433
434
435 # decodes elwidth
436 def decode_elwidth(encoding):
437 pmap = {'8': 0b11, '16': 0b10, '32': 0b01}
438 assert encoding in pmap, \
439 "encoding %s for elwidth not recognised" % encoding
440 return pmap[encoding]
441
442
443 # decodes predicate register encoding
444 def decode_predicate(encoding):
445 pmap = { # integer
446 '1<<r3': (0, 0b001),
447 'r3': (0, 0b010),
448 '~r3': (0, 0b011),
449 'r10': (0, 0b100),
450 '~r10': (0, 0b101),
451 'r30': (0, 0b110),
452 '~r30': (0, 0b111),
453 # CR
454 'lt': (1, 0b000),
455 'nl': (1, 0b001), 'ge': (1, 0b001), # same value
456 'gt': (1, 0b010),
457 'ng': (1, 0b011), 'le': (1, 0b011), # same value
458 'eq': (1, 0b100),
459 'ne': (1, 0b101),
460 'so': (1, 0b110), 'un': (1, 0b110), # same value
461 'ns': (1, 0b111), 'nu': (1, 0b111), # same value
462 }
463 assert encoding in pmap, \
464 "encoding %s for predicate not recognised" % encoding
465 return pmap[encoding]
466
467
468 # decodes "Mode" in similar way to BO field (supposed to, anyway)
469 def decode_bo(encoding):
470 pmap = { # TODO: double-check that these are the same as Branch BO
471 'lt': 0b000,
472 'nl': 0b001, 'ge': 0b001, # same value
473 'gt': 0b010,
474 'ng': 0b011, 'le': 0b011, # same value
475 'eq': 0b100,
476 'ne': 0b101,
477 'so': 0b110, 'un': 0b110, # same value
478 'ns': 0b111, 'nu': 0b111, # same value
479 }
480 assert encoding in pmap, \
481 "encoding %s for BO Mode not recognised" % encoding
482 return pmap[encoding]
483
484 # partial-decode fail-first mode
485
486
487 def decode_ffirst(encoding):
488 if encoding in ['RC1', '~RC1']:
489 return encoding
490 return decode_bo(encoding)
491
492
493 def decode_reg(field, macros=None):
494 if macros is None:
495 macros = {}
496 # decode the field number. "5.v" or "3.s" or "9"
497 # and now also "*0", and "*%0". note: *NOT* to add "*%rNNN" etc.
498 # https://bugs.libre-soc.org/show_bug.cgi?id=884#c0
499 if field.startswith(("*%", "*")):
500 if field.startswith("*%"):
501 field = field[2:]
502 else:
503 field = field[1:]
504 while field in macros:
505 field = macros[field]
506 return int(field), "vector" # actual register number
507
508 # try old convention (to be retired)
509 field = field.split(".")
510 regmode = 'scalar' # default
511 if len(field) == 2:
512 if field[1] == 's':
513 regmode = 'scalar'
514 elif field[1] == 'v':
515 regmode = 'vector'
516 field = int(field[0]) # actual register number
517 return field, regmode
518
519
520 def decode_imm(field):
521 ldst_imm = "(" in field and field[-1] == ')'
522 if ldst_imm:
523 return field[:-1].split("(")
524 else:
525 return None, field
526
527
528 def crf_extra(etype, regmode, field, extras):
529 """takes a CR Field number (CR0-CR127), splits into EXTRA2/3 and v3.0
530 the scalar/vector mode (crNN.v or crNN.s) changes both the format
531 of the EXTRA2/3 encoding as well as what range of registers is possible.
532 this function can be used for both BF/BFA and BA/BB/BT by first removing
533 the bottom 2 bits of BA/BB/BT then re-instating them after encoding.
534 see https://libre-soc.org/openpower/sv/svp64/appendix/#cr_extra
535 for specification
536 """
537 sv_extra, field = get_extra_cr_3bit(etype, regmode, field)
538 # now sanity-check (and shrink afterwards)
539 if etype == 'EXTRA2':
540 # 3-bit CR Field (BF, BFA) EXTRA2 encoding
541 if regmode == 'scalar':
542 # range is CR0-CR15 in increments of 1
543 assert (sv_extra >> 1) == 0, \
544 "scalar CR %s cannot fit into EXTRA2 %s" % \
545 (rname, str(extras[extra_idx]))
546 # all good: encode as scalar
547 sv_extra = sv_extra & 0b01
548 else: # vector
549 # range is CR0-CR127 in increments of 16
550 assert sv_extra & 0b111 == 0, \
551 "vector CR %s cannot fit into EXTRA2 %s" % \
552 (rname, str(extras[extra_idx]))
553 # all good: encode as vector (bit 2 set)
554 sv_extra = 0b10 | (sv_extra >> 3)
555 else:
556 # 3-bit CR Field (BF, BFA) EXTRA3 encoding
557 if regmode == 'scalar':
558 # range is CR0-CR31 in increments of 1
559 assert (sv_extra >> 2) == 0, \
560 "scalar CR %s cannot fit into EXTRA3 %s" % \
561 (rname, str(extras[extra_idx]))
562 # all good: encode as scalar
563 sv_extra = sv_extra & 0b11
564 else: # vector
565 # range is CR0-CR127 in increments of 8
566 assert sv_extra & 0b11 == 0, \
567 "vector CR %s cannot fit into EXTRA3 %s" % \
568 (rname, str(extras[extra_idx]))
569 # all good: encode as vector (bit 3 set)
570 sv_extra = 0b100 | (sv_extra >> 2)
571 return sv_extra, field
572
573
574 def to_number(field):
575 if field.startswith("0x"):
576 return eval(field)
577 if field.startswith("0b"):
578 return eval(field)
579 return int(field)
580
581
582 # decodes svp64 assembly listings and creates EXT001 svp64 prefixes
583 class SVP64Asm:
584 def __init__(self, lst, bigendian=False, macros=None):
585 if macros is None:
586 macros = {}
587 self.macros = macros
588 self.lst = lst
589 self.trans = self.translate(lst)
590 self.isa = ISA() # reads the v3.0B pseudo-code markdown files
591 self.svp64 = SVP64RM() # reads the svp64 Remap entries for registers
592 assert bigendian == False, "error, bigendian not supported yet"
593
594 def __iter__(self):
595 yield from self.trans
596
597 def translate_one(self, insn, macros=None):
598 if macros is None:
599 macros = {}
600 macros.update(self.macros)
601 isa = self.isa
602 svp64 = self.svp64
603 # find first space, to get opcode
604 ls = insn.split(' ')
605 opcode = ls[0]
606 # now find opcode fields
607 fields = ''.join(ls[1:]).split(',')
608 mfields = list(map(str.strip, fields))
609 log("opcode, fields", ls, opcode, mfields)
610 fields = []
611 # macro substitution
612 for field in mfields:
613 fields.append(macro_subst(macros, field))
614 log("opcode, fields substed", ls, opcode, fields)
615
616 # identify if it is a special instruction
617 custom_insn_hook = CUSTOM_INSNS.get(opcode)
618 if custom_insn_hook is not None:
619 fields = tuple(map(to_number, fields))
620 insn = custom_insn_hook(fields)
621 log(opcode, bin(insn))
622 yield ".long 0x%x" % insn
623 return
624
625 # identify if is a svp64 mnemonic
626 if not opcode.startswith('sv.'):
627 yield insn # unaltered
628 return
629 opcode = opcode[3:] # strip leading "sv"
630
631 # start working on decoding the svp64 op: sv.basev30Bop/vec2/mode
632 opmodes = opcode.split("/") # split at "/"
633 v30b_op = opmodes.pop(0) # first is the v3.0B
634 # check instruction ends with dot
635 rc_mode = v30b_op.endswith('.')
636 if rc_mode:
637 v30b_op = v30b_op[:-1]
638
639 # sigh again, have to recognised LD/ST bit-reverse instructions
640 # this has to be "processed" to fit into a v3.0B without the "sh"
641 # e.g. ldsh is actually ld
642 ldst_shift = v30b_op.startswith("l") and v30b_op.endswith("sh")
643
644 if v30b_op not in isa.instr:
645 raise Exception("opcode %s of '%s' not supported" %
646 (v30b_op, insn))
647
648 if ldst_shift:
649 # okaay we need to process the fields and make this:
650 # ldsh RT, SVD(RA), RC - 11 bits for SVD, 5 for RC
651 # into this:
652 # ld RT, D(RA) - 16 bits
653 # likewise same for SVDS (9 bits for SVDS, 5 for RC, 14 bits for DS)
654 form = isa.instr[v30b_op].form # get form (SVD-Form, SVDS-Form)
655
656 newfields = []
657 for field in fields:
658 # identify if this is a ld/st immediate(reg) thing
659 ldst_imm = "(" in field and field[-1] == ')'
660 if ldst_imm:
661 newfields.append(field[:-1].split("("))
662 else:
663 newfields.append(field)
664
665 immed, RA = newfields[1]
666 immed = int(immed)
667 RC = int(newfields.pop(2)) # better be an integer number!
668 if form == 'SVD': # 16 bit: immed 11 bits, RC shift up 11
669 immed = (immed & 0b11111111111) | (RC << 11)
670 if immed & (1 << 15): # should be negative
671 immed -= 1 << 16
672 if form == 'SVDS': # 14 bit: immed 9 bits, RC shift up 9
673 immed = (immed & 0b111111111) | (RC << 9)
674 if immed & (1 << 13): # should be negative
675 immed -= 1 << 14
676 newfields[1] = "%d(%s)" % (immed, RA)
677 fields = newfields
678
679 # and strip off "sh" from end, and add "sh" to opmodes, instead
680 v30b_op = v30b_op[:-2]
681 opmodes.append("sh")
682 log("rewritten", v30b_op, opmodes, fields)
683
684 if v30b_op not in svp64.instrs:
685 raise Exception("opcode %s of '%s' not an svp64 instruction" %
686 (v30b_op, insn))
687 v30b_regs = isa.instr[v30b_op].regs[0] # get regs info "RT, RA, RB"
688 rm = svp64.instrs[v30b_op] # one row of the svp64 RM CSV
689 log("v3.0B op", v30b_op, "Rc=1" if rc_mode else '')
690 log("v3.0B regs", opcode, v30b_regs)
691 log("RM", rm)
692
693 # right. the first thing to do is identify the ordering of
694 # the registers, by name. the EXTRA2/3 ordering is in
695 # rm['0']..rm['3'] but those fields contain the names RA, BB
696 # etc. we have to read the pseudocode to understand which
697 # reg is which in our instruction. sigh.
698
699 # first turn the svp64 rm into a "by name" dict, recording
700 # which position in the RM EXTRA it goes into
701 # also: record if the src or dest was a CR, for sanity-checking
702 # (elwidth overrides on CRs are banned)
703 decode = decode_extra(rm)
704 dest_reg_cr, src_reg_cr, svp64_src, svp64_dest = decode
705
706 log("EXTRA field index, src", svp64_src)
707 log("EXTRA field index, dest", svp64_dest)
708
709 # okaaay now we identify the field value (opcode N,N,N) with
710 # the pseudo-code info (opcode RT, RA, RB)
711 assert len(fields) == len(v30b_regs), \
712 "length of fields %s must match insn `%s` fields %s" % \
713 (str(v30b_regs), insn, str(fields))
714 opregfields = zip(fields, v30b_regs) # err that was easy
715
716 # now for each of those find its place in the EXTRA encoding
717 # note there is the possibility (for LD/ST-with-update) of
718 # RA occurring **TWICE**. to avoid it getting added to the
719 # v3.0B suffix twice, we spot it as a duplicate, here
720 extras = OrderedDict()
721 for idx, (field, regname) in enumerate(opregfields):
722 imm, regname = decode_imm(regname)
723 rtype = get_regtype(regname)
724 log(" idx find", rtype, idx, field, regname, imm)
725 if rtype is None:
726 # probably an immediate field, append it straight
727 extras[('imm', idx, False)] = (idx, field, None, None, None)
728 continue
729 extra = svp64_src.get(regname, None)
730 if extra is not None:
731 extra = ('s', extra, False) # not a duplicate
732 extras[extra] = (idx, field, regname, rtype, imm)
733 log(" idx src", idx, extra, extras[extra])
734 dextra = svp64_dest.get(regname, None)
735 log("regname in", regname, dextra)
736 if dextra is not None:
737 is_a_duplicate = extra is not None # duplicate spotted
738 dextra = ('d', dextra, is_a_duplicate)
739 extras[dextra] = (idx, field, regname, rtype, imm)
740 log(" idx dst", idx, extra, extras[dextra])
741
742 # great! got the extra fields in their associated positions:
743 # also we know the register type. now to create the EXTRA encodings
744 etype = rm['Etype'] # Extra type: EXTRA3/EXTRA2
745 ptype = rm['Ptype'] # Predication type: Twin / Single
746 extra_bits = 0
747 v30b_newfields = []
748 for extra_idx, (idx, field, rname, rtype, iname) in extras.items():
749 # is it a field we don't alter/examine? if so just put it
750 # into newfields
751 if rtype is None:
752 v30b_newfields.append(field)
753 continue
754
755 # identify if this is a ld/st immediate(reg) thing
756 ldst_imm = "(" in field and field[-1] == ')'
757 if ldst_imm:
758 immed, field = field[:-1].split("(")
759
760 field, regmode = decode_reg(field, macros=macros)
761 log(" ", extra_idx, rname, rtype,
762 regmode, iname, field, end=" ")
763
764 # see Mode field https://libre-soc.org/openpower/sv/svp64/
765 # XXX TODO: the following is a bit of a laborious repeated
766 # mess, which could (and should) easily be parameterised.
767 # XXX also TODO: the LD/ST modes which are different
768 # https://libre-soc.org/openpower/sv/ldst/
769
770 # rright. SVP64 register numbering is from 0 to 127
771 # for GPRs, FPRs *and* CR Fields, where for v3.0 the GPRs and RPFs
772 # are 0-31 and CR Fields are only 0-7. the SVP64 RM "Extra"
773 # area is used to extend the numbering from the 32-bit
774 # instruction, and also to record whether the register
775 # is scalar or vector. on a per-operand basis. this
776 # results in a slightly finnicky encoding: here we go...
777
778 # encode SV-GPR and SV-FPR field into extra, v3.0field
779 if rtype in ['GPR', 'FPR']:
780 sv_extra, field = get_extra_gpr(etype, regmode, field)
781 # now sanity-check. EXTRA3 is ok, EXTRA2 has limits
782 # (and shrink to a single bit if ok)
783 if etype == 'EXTRA2':
784 if regmode == 'scalar':
785 # range is r0-r63 in increments of 1
786 assert (sv_extra >> 1) == 0, \
787 "scalar GPR %s cannot fit into EXTRA2 %s" % \
788 (rname, str(extras[extra_idx]))
789 # all good: encode as scalar
790 sv_extra = sv_extra & 0b01
791 else:
792 # range is r0-r127 in increments of 2 (r0 r2 ... r126)
793 assert sv_extra & 0b01 == 0, \
794 "%s: vector field %s cannot fit " \
795 "into EXTRA2 %s" % \
796 (insn, rname, str(extras[extra_idx]))
797 # all good: encode as vector (bit 2 set)
798 sv_extra = 0b10 | (sv_extra >> 1)
799 elif regmode == 'vector':
800 # EXTRA3 vector bit needs marking
801 sv_extra |= 0b100
802
803 # encode SV-CR 3-bit field into extra, v3.0field.
804 # 3-bit is for things like BF and BFA
805 elif rtype == 'CR_3bit':
806 sv_extra, field = crf_extra(etype, regmode, field, extras)
807
808 # encode SV-CR 5-bit field into extra, v3.0field
809 # 5-bit is for things like BA BB BC BT etc.
810 # *sigh* this is the same as 3-bit except the 2 LSBs of the
811 # 5-bit field are passed through unaltered.
812 elif rtype == 'CR_5bit':
813 cr_subfield = field & 0b11 # record bottom 2 bits for later
814 field = field >> 2 # strip bottom 2 bits
815 # use the exact same 3-bit function for the top 3 bits
816 sv_extra, field = crf_extra(etype, regmode, field, extras)
817 # reconstruct the actual 5-bit CR field (preserving the
818 # bottom 2 bits, unaltered)
819 field = (field << 2) | cr_subfield
820
821 else:
822 raise Exception("no type match: %s" % rtype)
823
824 # capture the extra field info
825 log("=>", "%5s" % bin(sv_extra), field)
826 extras[extra_idx] = sv_extra
827
828 # append altered field value to v3.0b, differs for LDST
829 # note that duplicates are skipped e.g. EXTRA2 contains
830 # *BOTH* s:RA *AND* d:RA which happens on LD/ST-with-update
831 srcdest, idx, duplicate = extra_idx
832 if duplicate: # skip adding to v3.0b fields, already added
833 continue
834 if ldst_imm:
835 v30b_newfields.append(("%s(%s)" % (immed, str(field))))
836 else:
837 v30b_newfields.append(str(field))
838
839 log("new v3.0B fields", v30b_op, v30b_newfields)
840 log("extras", extras)
841
842 # rright. now we have all the info. start creating SVP64 RM
843 svp64_rm = SVP64RMFields()
844
845 # begin with EXTRA fields
846 for idx, sv_extra in extras.items():
847 log(idx)
848 if idx is None:
849 continue
850 if idx[0] == 'imm':
851 continue
852 srcdest, idx, duplicate = idx
853 if etype == 'EXTRA2':
854 svp64_rm.extra2[idx].eq(
855 SelectableInt(sv_extra, SVP64RM_EXTRA2_SPEC_SIZE))
856 else:
857 svp64_rm.extra3[idx].eq(
858 SelectableInt(sv_extra, SVP64RM_EXTRA3_SPEC_SIZE))
859
860 # identify if the op is a LD/ST. the "blegh" way. copied
861 # from power_enums. TODO, split the list _insns down.
862 is_ld = v30b_op in [
863 "lbarx", "lbz", "lbzu", "lbzux", "lbzx", # load byte
864 "ld", "ldarx", "ldbrx", "ldu", "ldux", "ldx", # load double
865 "lfs", "lfsx", "lfsu", "lfsux", # FP load single
866 "lfd", "lfdx", "lfdu", "lfdux", "lfiwzx", "lfiwax", # FP load dbl
867 "lha", "lharx", "lhau", "lhaux", "lhax", # load half
868 "lhbrx", "lhz", "lhzu", "lhzux", "lhzx", # more load half
869 "lwa", "lwarx", "lwaux", "lwax", "lwbrx", # load word
870 "lwz", "lwzcix", "lwzu", "lwzux", "lwzx", # more load word
871 ]
872 is_st = v30b_op in [
873 "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
874 "std", "stdbrx", "stdcx", "stdu", "stdux", "stdx",
875 "stfs", "stfsx", "stfsu", "stfux", # FP store sgl
876 "stfd", "stfdx", "stfdu", "stfdux", "stfiwx", # FP store dbl
877 "sth", "sthbrx", "sthcx", "sthu", "sthux", "sthx",
878 "stw", "stwbrx", "stwcx", "stwu", "stwux", "stwx",
879 ]
880 # use this to determine if the SVP64 RM format is different.
881 # see https://libre-soc.org/openpower/sv/ldst/
882 is_ldst = is_ld or is_st
883
884 # branch-conditional detection
885 is_bc = v30b_op in [
886 "bc", "bclr",
887 ]
888
889 # parts of svp64_rm
890 mmode = 0 # bit 0
891 pmask = 0 # bits 1-3
892 destwid = 0 # bits 4-5
893 srcwid = 0 # bits 6-7
894 subvl = 0 # bits 8-9
895 smask = 0 # bits 16-18 but only for twin-predication
896 mode = 0 # bits 19-23
897
898 mask_m_specified = False
899 has_pmask = False
900 has_smask = False
901
902 saturation = None
903 src_zero = 0
904 dst_zero = 0
905 sv_mode = None
906
907 mapreduce = False
908 reverse_gear = False
909 mapreduce_crm = False
910 mapreduce_svm = False
911
912 predresult = False
913 failfirst = False
914 ldst_elstride = 0
915
916 # branch-conditional bits
917 bc_all = 0
918 bc_lru = 0
919 bc_brc = 0
920 bc_svstep = 0
921 bc_vsb = 0
922 bc_vlset = 0
923 bc_vli = 0
924 bc_snz = 0
925
926 # ok let's start identifying opcode augmentation fields
927 for encmode in opmodes:
928 # predicate mask (src and dest)
929 if encmode.startswith("m="):
930 pme = encmode
931 pmmode, pmask = decode_predicate(encmode[2:])
932 smmode, smask = pmmode, pmask
933 mmode = pmmode
934 mask_m_specified = True
935 # predicate mask (dest)
936 elif encmode.startswith("dm="):
937 pme = encmode
938 pmmode, pmask = decode_predicate(encmode[3:])
939 mmode = pmmode
940 has_pmask = True
941 # predicate mask (src, twin-pred)
942 elif encmode.startswith("sm="):
943 sme = encmode
944 smmode, smask = decode_predicate(encmode[3:])
945 mmode = smmode
946 has_smask = True
947 # shifted LD/ST
948 elif encmode.startswith("sh"):
949 ldst_shift = True
950 # vec2/3/4
951 elif encmode.startswith("vec"):
952 subvl = decode_subvl(encmode[3:])
953 # elwidth
954 elif encmode.startswith("ew="):
955 destwid = decode_elwidth(encmode[3:])
956 elif encmode.startswith("sw="):
957 srcwid = decode_elwidth(encmode[3:])
958 # element-strided LD/ST
959 elif encmode == 'els':
960 ldst_elstride = 1
961 # saturation
962 elif encmode == 'sats':
963 assert sv_mode is None
964 saturation = 1
965 sv_mode = 0b10
966 elif encmode == 'satu':
967 assert sv_mode is None
968 sv_mode = 0b10
969 saturation = 0
970 # predicate zeroing
971 elif encmode == 'sz':
972 src_zero = 1
973 elif encmode == 'dz':
974 dst_zero = 1
975 # failfirst
976 elif encmode.startswith("ff="):
977 assert sv_mode is None
978 sv_mode = 0b01
979 failfirst = decode_ffirst(encmode[3:])
980 # predicate-result, interestingly same as fail-first
981 elif encmode.startswith("pr="):
982 assert sv_mode is None
983 sv_mode = 0b11
984 predresult = decode_ffirst(encmode[3:])
985 # map-reduce mode, reverse-gear
986 elif encmode == 'mrr':
987 assert sv_mode is None
988 sv_mode = 0b00
989 mapreduce = True
990 reverse_gear = True
991 # map-reduce mode
992 elif encmode == 'mr':
993 assert sv_mode is None
994 sv_mode = 0b00
995 mapreduce = True
996 elif encmode == 'crm': # CR on map-reduce
997 assert sv_mode is None
998 sv_mode = 0b00
999 mapreduce_crm = True
1000 elif encmode == 'svm': # sub-vector mode
1001 mapreduce_svm = True
1002 elif is_bc:
1003 if encmode == 'all':
1004 bc_all = 1
1005 elif encmode == 'st': # svstep mode
1006 bc_step = 1
1007 elif encmode == 'sr': # svstep BRc mode
1008 bc_step = 1
1009 bc_brc = 1
1010 elif encmode == 'vs': # VLSET mode
1011 bc_vlset = 1
1012 elif encmode == 'vsi': # VLSET mode with VLI (VL inclusives)
1013 bc_vlset = 1
1014 bc_vli = 1
1015 elif encmode == 'vsb': # VLSET mode with VSb
1016 bc_vlset = 1
1017 bc_vsb = 1
1018 elif encmode == 'vsbi': # VLSET mode with VLI and VSb
1019 bc_vlset = 1
1020 bc_vli = 1
1021 bc_vsb = 1
1022 elif encmode == 'snz': # sz (only) already set above
1023 src_zero = 1
1024 bc_snz = 1
1025 elif encmode == 'lu': # LR update mode
1026 bc_lru = 1
1027 else:
1028 raise AssertionError("unknown encmode %s" % encmode)
1029 else:
1030 raise AssertionError("unknown encmode %s" % encmode)
1031
1032 if ptype == '2P':
1033 # since m=xx takes precedence (overrides) sm=xx and dm=xx,
1034 # treat them as mutually exclusive
1035 if mask_m_specified:
1036 assert not has_smask,\
1037 "cannot have both source-mask and predicate mask"
1038 assert not has_pmask,\
1039 "cannot have both dest-mask and predicate mask"
1040 # since the default is INT predication (ALWAYS), if you
1041 # specify one CR mask, you must specify both, to avoid
1042 # mixing INT and CR reg types
1043 if has_pmask and pmmode == 1:
1044 assert has_smask, \
1045 "need explicit source-mask in CR twin predication"
1046 if has_smask and smmode == 1:
1047 assert has_pmask, \
1048 "need explicit dest-mask in CR twin predication"
1049 # sanity-check that 2Pred mask is same mode
1050 if has_pmask and has_smask:
1051 assert smmode == pmmode, \
1052 "predicate masks %s and %s must be same reg type" % \
1053 (pme, sme)
1054
1055 # sanity-check that twin-predication mask only specified in 2P mode
1056 if ptype == '1P':
1057 assert not has_smask, \
1058 "source-mask can only be specified on Twin-predicate ops"
1059 assert not has_pmask, \
1060 "dest-mask can only be specified on Twin-predicate ops"
1061
1062 # construct the mode field, doing sanity-checking along the way
1063 if mapreduce_svm:
1064 assert sv_mode == 0b00, "sub-vector mode in mapreduce only"
1065 assert subvl != 0, "sub-vector mode not possible on SUBVL=1"
1066
1067 if src_zero:
1068 assert has_smask or mask_m_specified, \
1069 "src zeroing requires a source predicate"
1070 if dst_zero:
1071 assert has_pmask or mask_m_specified, \
1072 "dest zeroing requires a dest predicate"
1073
1074 # check LDST shifted, only available in "normal" mode
1075 if is_ldst and ldst_shift:
1076 assert sv_mode is None, \
1077 "LD shift cannot have modes (%s) applied" % sv_mode
1078
1079 # okaaay, so there are 4 different modes, here, which will be
1080 # partly-merged-in: is_ldst is merged in with "normal", but
1081 # is_bc is so different it's done separately. likewise is_cr
1082 # (when it is done). here are the maps:
1083
1084 # for "normal" arithmetic: https://libre-soc.org/openpower/sv/normal/
1085 """
1086 | 0-1 | 2 | 3 4 | description |
1087 | --- | --- |---------|-------------------------- |
1088 | 00 | 0 | dz sz | normal mode |
1089 | 00 | 1 | 0 RG | scalar reduce mode (mapreduce), SUBVL=1 |
1090 | 00 | 1 | 1 / | parallel reduce mode (mapreduce), SUBVL=1 |
1091 | 00 | 1 | SVM RG | subvector reduce mode, SUBVL>1 |
1092 | 01 | inv | CR-bit | Rc=1: ffirst CR sel |
1093 | 01 | inv | VLi RC1 | Rc=0: ffirst z/nonz |
1094 | 10 | N | dz sz | sat mode: N=0/1 u/s |
1095 | 11 | inv | CR-bit | Rc=1: pred-result CR sel |
1096 | 11 | inv | dz RC1 | Rc=0: pred-result z/nonz |
1097 """
1098
1099 # https://libre-soc.org/openpower/sv/ldst/
1100 # for LD/ST-immediate:
1101 """
1102 | 0-1 | 2 | 3 4 | description |
1103 | --- | --- |---------|--------------------------- |
1104 | 00 | 0 | dz els | normal mode |
1105 | 00 | 1 | dz shf | shift mode |
1106 | 01 | inv | CR-bit | Rc=1: ffirst CR sel |
1107 | 01 | inv | els RC1 | Rc=0: ffirst z/nonz |
1108 | 10 | N | dz els | sat mode: N=0/1 u/s |
1109 | 11 | inv | CR-bit | Rc=1: pred-result CR sel |
1110 | 11 | inv | els RC1 | Rc=0: pred-result z/nonz |
1111 """
1112
1113 # for LD/ST-indexed (RA+RB):
1114 """
1115 | 0-1 | 2 | 3 4 | description |
1116 | --- | --- |---------|-------------------------- |
1117 | 00 | SEA | dz sz | normal mode |
1118 | 01 | SEA | dz sz | Strided (scalar only source) |
1119 | 10 | N | dz sz | sat mode: N=0/1 u/s |
1120 | 11 | inv | CR-bit | Rc=1: pred-result CR sel |
1121 | 11 | inv | dz RC1 | Rc=0: pred-result z/nonz |
1122 """
1123
1124 # and leaving out branches and cr_ops for now because they're
1125 # under development
1126 """ TODO branches and cr_ops
1127 """
1128
1129 # now create mode and (overridden) src/dst widths
1130 # XXX TODO: sanity-check bc modes
1131 if is_bc:
1132 sv_mode = ((bc_svstep << SVP64MODE.MOD2_MSB) |
1133 (bc_vlset << SVP64MODE.MOD2_LSB) |
1134 (bc_snz << SVP64MODE.BC_SNZ))
1135 srcwid = (bc_vsb << 1) | bc_lru
1136 destwid = (bc_lru << 1) | bc_all
1137
1138 else:
1139
1140 ######################################
1141 # "normal" mode
1142 if sv_mode is None:
1143 mode |= src_zero << SVP64MODE.SZ # predicate zeroing
1144 mode |= dst_zero << SVP64MODE.DZ # predicate zeroing
1145 if is_ldst:
1146 # TODO: for now, LD/ST-indexed is ignored.
1147 mode |= ldst_elstride << SVP64MODE.ELS_NORMAL # el-strided
1148 # shifted mode
1149 if ldst_shift:
1150 mode |= 1 << SVP64MODE.LDST_SHIFT
1151 else:
1152 # TODO, reduce and subvector mode
1153 # 00 1 dz CRM reduce mode (mapreduce), SUBVL=1
1154 # 00 1 SVM CRM subvector reduce mode, SUBVL>1
1155 pass
1156 sv_mode = 0b00
1157
1158 ######################################
1159 # "mapreduce" modes
1160 elif sv_mode == 0b00:
1161 mode |= (0b1 << SVP64MODE.REDUCE) # sets mapreduce
1162 assert dst_zero == 0, "dest-zero not allowed in mapreduce mode"
1163 if reverse_gear:
1164 mode |= (0b1 << SVP64MODE.RG) # sets Reverse-gear mode
1165 if mapreduce_crm:
1166 mode |= (0b1 << SVP64MODE.CRM) # sets CRM mode
1167 assert rc_mode, "CRM only allowed when Rc=1"
1168 # bit of weird encoding to jam zero-pred or SVM mode in.
1169 # SVM mode can be enabled only when SUBVL=2/3/4 (vec2/3/4)
1170 if subvl == 0:
1171 mode |= dst_zero << SVP64MODE.DZ # predicate zeroing
1172 elif mapreduce_svm:
1173 mode |= (0b1 << SVP64MODE.SVM) # sets SVM mode
1174
1175 ######################################
1176 # "failfirst" modes
1177 elif sv_mode == 0b01:
1178 assert src_zero == 0, "dest-zero not allowed in failfirst mode"
1179 if failfirst == 'RC1':
1180 mode |= (0b1 << SVP64MODE.RC1) # sets RC1 mode
1181 mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
1182 assert rc_mode == False, "ffirst RC1 only ok when Rc=0"
1183 elif failfirst == '~RC1':
1184 mode |= (0b1 << SVP64MODE.RC1) # sets RC1 mode
1185 mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
1186 mode |= (0b1 << SVP64MODE.INV) # ... with inversion
1187 assert rc_mode == False, "ffirst RC1 only ok when Rc=0"
1188 else:
1189 assert dst_zero == 0, "dst-zero not allowed in ffirst BO"
1190 assert rc_mode, "ffirst BO only possible when Rc=1"
1191 mode |= (failfirst << SVP64MODE.BO_LSB) # set BO
1192
1193 ######################################
1194 # "saturation" modes
1195 elif sv_mode == 0b10:
1196 mode |= src_zero << SVP64MODE.SZ # predicate zeroing
1197 mode |= dst_zero << SVP64MODE.DZ # predicate zeroing
1198 mode |= (saturation << SVP64MODE.N) # signed/us saturation
1199
1200 ######################################
1201 # "predicate-result" modes. err... code-duplication from ffirst
1202 elif sv_mode == 0b11:
1203 assert src_zero == 0, "dest-zero not allowed in predresult mode"
1204 if predresult == 'RC1':
1205 mode |= (0b1 << SVP64MODE.RC1) # sets RC1 mode
1206 mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
1207 assert rc_mode == False, "pr-mode RC1 only ok when Rc=0"
1208 elif predresult == '~RC1':
1209 mode |= (0b1 << SVP64MODE.RC1) # sets RC1 mode
1210 mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
1211 mode |= (0b1 << SVP64MODE.INV) # ... with inversion
1212 assert rc_mode == False, "pr-mode RC1 only ok when Rc=0"
1213 else:
1214 assert dst_zero == 0, "dst-zero not allowed in pr-mode BO"
1215 assert rc_mode, "pr-mode BO only possible when Rc=1"
1216 mode |= (predresult << SVP64MODE.BO_LSB) # set BO
1217
1218 # whewww.... modes all done :)
1219 # now put into svp64_rm
1220 mode |= sv_mode
1221 # mode: bits 19-23
1222 svp64_rm.mode.eq(SelectableInt(mode, SVP64RM_MODE_SIZE))
1223
1224 # put in predicate masks into svp64_rm
1225 if ptype == '2P':
1226 # source pred: bits 16-18
1227 svp64_rm.smask.eq(SelectableInt(smask, SVP64RM_SMASK_SIZE))
1228 # mask mode: bit 0
1229 svp64_rm.mmode.eq(SelectableInt(mmode, SVP64RM_MMODE_SIZE))
1230 # 1-pred: bits 1-3
1231 svp64_rm.mask.eq(SelectableInt(pmask, SVP64RM_MASK_SIZE))
1232
1233 # and subvl: bits 8-9
1234 svp64_rm.subvl.eq(SelectableInt(subvl, SVP64RM_SUBVL_SIZE))
1235
1236 # put in elwidths
1237 # srcwid: bits 6-7
1238 svp64_rm.ewsrc.eq(SelectableInt(srcwid, SVP64RM_EWSRC_SIZE))
1239 # destwid: bits 4-5
1240 svp64_rm.elwidth.eq(SelectableInt(destwid, SVP64RM_ELWIDTH_SIZE))
1241
1242 # nice debug printout. (and now for something completely different)
1243 # https://youtu.be/u0WOIwlXE9g?t=146
1244 svp64_rm_value = svp64_rm.spr.value
1245 log("svp64_rm", hex(svp64_rm_value), bin(svp64_rm_value))
1246 log(" mmode 0 :", bin(mmode))
1247 log(" pmask 1-3 :", bin(pmask))
1248 log(" dstwid 4-5 :", bin(destwid))
1249 log(" srcwid 6-7 :", bin(srcwid))
1250 log(" subvl 8-9 :", bin(subvl))
1251 log(" mode 19-23:", bin(mode))
1252 offs = 2 if etype == 'EXTRA2' else 3 # 2 or 3 bits
1253 for idx, sv_extra in extras.items():
1254 if idx is None:
1255 continue
1256 if idx[0] == 'imm':
1257 continue
1258 srcdest, idx, duplicate = idx
1259 start = (10+idx*offs)
1260 end = start + offs-1
1261 log(" extra%d %2d-%2d:" % (idx, start, end),
1262 bin(sv_extra))
1263 if ptype == '2P':
1264 log(" smask 16-17:", bin(smask))
1265 log()
1266
1267 # first, construct the prefix from its subfields
1268 svp64_prefix = SVP64PrefixFields()
1269 svp64_prefix.major.eq(SelectableInt(0x1, SV64P_MAJOR_SIZE))
1270 svp64_prefix.pid.eq(SelectableInt(0b11, SV64P_PID_SIZE))
1271 svp64_prefix.rm.eq(svp64_rm.spr)
1272
1273 # fiinally yield the svp64 prefix and the thingy. v3.0b opcode
1274 rc = '.' if rc_mode else ''
1275 yield ".long 0x%08x" % svp64_prefix.insn.value
1276 log(v30b_op, v30b_newfields)
1277 # argh, sv.fmadds etc. need to be done manually
1278 if v30b_op == 'ffmadds':
1279 opcode = 59 << (32-6) # bits 0..6 (MSB0)
1280 opcode |= int(v30b_newfields[0]) << (32-11) # FRT
1281 opcode |= int(v30b_newfields[1]) << (32-16) # FRA
1282 opcode |= int(v30b_newfields[2]) << (32-21) # FRB
1283 opcode |= int(v30b_newfields[3]) << (32-26) # FRC
1284 opcode |= 0b00101 << (32-31) # bits 26-30
1285 if rc:
1286 opcode |= 1 # Rc, bit 31.
1287 yield ".long 0x%x" % opcode
1288 # argh, sv.fdmadds need to be done manually
1289 elif v30b_op == 'fdmadds':
1290 opcode = 59 << (32-6) # bits 0..6 (MSB0)
1291 opcode |= int(v30b_newfields[0]) << (32-11) # FRT
1292 opcode |= int(v30b_newfields[1]) << (32-16) # FRA
1293 opcode |= int(v30b_newfields[2]) << (32-21) # FRB
1294 opcode |= int(v30b_newfields[3]) << (32-26) # FRC
1295 opcode |= 0b01111 << (32-31) # bits 26-30
1296 if rc:
1297 opcode |= 1 # Rc, bit 31.
1298 yield ".long 0x%x" % opcode
1299 # argh, sv.ffadds etc. need to be done manually
1300 elif v30b_op == 'ffadds':
1301 opcode = 59 << (32-6) # bits 0..6 (MSB0)
1302 opcode |= int(v30b_newfields[0]) << (32-11) # FRT
1303 opcode |= int(v30b_newfields[1]) << (32-16) # FRA
1304 opcode |= int(v30b_newfields[2]) << (32-21) # FRB
1305 opcode |= 0b01101 << (32-31) # bits 26-30
1306 if rc:
1307 opcode |= 1 # Rc, bit 31.
1308 yield ".long 0x%x" % opcode
1309 # sigh have to do svstep here manually for now...
1310 elif v30b_op in ["svstep", "svstep."]:
1311 insn = 22 << (31-5) # opcode 22, bits 0-5
1312 insn |= int(v30b_newfields[0]) << (31-10) # RT , bits 6-10
1313 insn |= int(v30b_newfields[1]) << (31-22) # SVi , bits 16-22
1314 insn |= int(v30b_newfields[2]) << (31-25) # vf , bit 25
1315 insn |= 0b10011 << (31-30) # XO , bits 26..30
1316 if opcode == 'svstep.':
1317 insn |= 1 << (31-31) # Rc=1 , bit 31
1318 log("svstep", bin(insn))
1319 yield ".long 0x%x" % insn
1320 # argh, sv.fcoss etc. need to be done manually
1321 elif v30b_op in ["fcoss", "fcoss."]:
1322 insn = 59 << (31-5) # opcode 59, bits 0-5
1323 insn |= int(v30b_newfields[0]) << (31-10) # RT , bits 6-10
1324 insn |= int(v30b_newfields[1]) << (31-20) # RB , bits 16-20
1325 insn |= 0b1000101110 << (31-30) # XO , bits 21..30
1326 if opcode == 'fcoss.':
1327 insn |= 1 << (31-31) # Rc=1 , bit 31
1328 log("fcoss", bin(insn))
1329 yield ".long 0x%x" % insn
1330 else:
1331 yield "%s %s" % (v30b_op+rc, ", ".join(v30b_newfields))
1332 log("new v3.0B fields", v30b_op, v30b_newfields)
1333
1334 def translate(self, lst):
1335 for insn in lst:
1336 yield from self.translate_one(insn)
1337
1338
1339 def macro_subst(macros, txt):
1340 again = True
1341 log("subst", txt, macros)
1342 while again:
1343 again = False
1344 for macro, value in macros.items():
1345 if macro == txt:
1346 again = True
1347 replaced = txt.replace(macro, value)
1348 log("macro", txt, "replaced", replaced, macro, value)
1349 txt = replaced
1350 continue
1351 toreplace = '%s.s' % macro
1352 if toreplace == txt:
1353 again = True
1354 replaced = txt.replace(toreplace, "%s.s" % value)
1355 log("macro", txt, "replaced", replaced, toreplace, value)
1356 txt = replaced
1357 continue
1358 toreplace = '%s.v' % macro
1359 if toreplace == txt:
1360 again = True
1361 replaced = txt.replace(toreplace, "%s.v" % value)
1362 log("macro", txt, "replaced", replaced, toreplace, value)
1363 txt = replaced
1364 continue
1365 toreplace = '(%s)' % macro
1366 if toreplace in txt:
1367 again = True
1368 replaced = txt.replace(toreplace, '(%s)' % value)
1369 log("macro", txt, "replaced", replaced, toreplace, value)
1370 txt = replaced
1371 continue
1372 log(" processed", txt)
1373 return txt
1374
1375
1376 def get_ws(line):
1377 # find whitespace
1378 ws = ''
1379 while line:
1380 if not line[0].isspace():
1381 break
1382 ws += line[0]
1383 line = line[1:]
1384 return ws, line
1385
1386
1387 def asm_process():
1388 # get an input file and an output file
1389 args = sys.argv[1:]
1390 if len(args) == 0:
1391 infile = sys.stdin
1392 outfile = sys.stdout
1393 # read the whole lot in advance in case of in-place
1394 lines = list(infile.readlines())
1395 elif len(args) != 2:
1396 print("pysvp64asm [infile | -] [outfile | -]", file=sys.stderr)
1397 exit(0)
1398 else:
1399 if args[0] == '--':
1400 infile = sys.stdin
1401 else:
1402 infile = open(args[0], "r")
1403 # read the whole lot in advance in case of in-place overwrite
1404 lines = list(infile.readlines())
1405
1406 if args[1] == '--':
1407 outfile = sys.stdout
1408 else:
1409 outfile = open(args[1], "w")
1410
1411 # read the line, look for custom insn, process it
1412 macros = {} # macros which start ".set"
1413 isa = SVP64Asm([])
1414 for line in lines:
1415 op = line.split("#")[0].strip()
1416 # identify macros
1417 if op.startswith(".set"):
1418 macro = op[4:].split(",")
1419 (macro, value) = map(str.strip, macro)
1420 macros[macro] = value
1421 if not op.startswith('sv.') and not op.startswith(tuple(CUSTOM_INSNS)):
1422 outfile.write(line)
1423 continue
1424
1425 (ws, line) = get_ws(line)
1426 lst = isa.translate_one(op, macros)
1427 lst = '; '.join(lst)
1428 outfile.write("%s%s # %s\n" % (ws, lst, op))
1429
1430
1431 if __name__ == '__main__':
1432 lst = ['slw 3, 1, 4',
1433 'extsw 5, 3',
1434 'sv.extsw 5, 3',
1435 'sv.cmpi 5, 1, 3, 2',
1436 'sv.setb 5, 31',
1437 'sv.isel 64.v, 3, 2, 65.v',
1438 'sv.setb/dm=r3/sm=1<<r3 5, 31',
1439 'sv.setb/m=r3 5, 31',
1440 'sv.setb/vec2 5, 31',
1441 'sv.setb/sw=8/ew=16 5, 31',
1442 'sv.extsw./ff=eq 5, 31',
1443 'sv.extsw./satu/sz/dz/sm=r3/dm=r3 5, 31',
1444 'sv.extsw./pr=eq 5.v, 31',
1445 'sv.add. 5.v, 2.v, 1.v',
1446 'sv.add./m=r3 5.v, 2.v, 1.v',
1447 ]
1448 lst += [
1449 'sv.stw 5.v, 4(1.v)',
1450 'sv.ld 5.v, 4(1.v)',
1451 'setvl. 2, 3, 4, 0, 1, 1',
1452 'sv.setvl. 2, 3, 4, 0, 1, 1',
1453 ]
1454 lst = [
1455 "sv.stfsu 0.v, 16(4.v)",
1456 ]
1457 lst = [
1458 "sv.stfsu/els 0.v, 16(4)",
1459 ]
1460 lst = [
1461 'sv.add./mr 5.v, 2.v, 1.v',
1462 ]
1463 macros = {'win2': '50', 'win': '60'}
1464 lst = [
1465 'sv.addi win2.v, win.v, -1',
1466 'sv.add./mrr 5.v, 2.v, 1.v',
1467 #'sv.lhzsh 5.v, 11(9.v), 15',
1468 #'sv.lwzsh 5.v, 11(9.v), 15',
1469 'sv.ffmadds 6.v, 2.v, 4.v, 6.v',
1470 ]
1471 lst = [
1472 #'sv.fmadds 0.v, 8.v, 16.v, 4.v',
1473 #'sv.ffadds 0.v, 8.v, 4.v',
1474 'svremap 11, 0, 1, 2, 3, 2, 1',
1475 'svshape 8, 1, 1, 1, 0',
1476 'svshape 8, 1, 1, 1, 1',
1477 ]
1478 lst = [
1479 #'sv.lfssh 4.v, 11(8.v), 15',
1480 #'sv.lwzsh 4.v, 11(8.v), 15',
1481 #'sv.svstep. 2.v, 4, 0',
1482 #'sv.fcfids. 48.v, 64.v',
1483 'sv.fcoss. 80.v, 0.v',
1484 'sv.fcoss. 20.v, 0.v',
1485 ]
1486 lst = [
1487 'sv.bc/all 3,12,192',
1488 'sv.bclr/vsbi 3,81.v,192',
1489 'sv.ld 5.v, 4(1.v)',
1490 'sv.svstep. 2.v, 4, 0',
1491 ]
1492 lst = [
1493 'maxs 3,12,5',
1494 'maxs. 3,12,5',
1495 'avgadd 3,12,5',
1496 'absdu 3,12,5',
1497 'absds 3,12,5',
1498 'absdacu 3,12,5',
1499 'absdacs 3,12,5',
1500 'cprop 3,12,5',
1501 'svindex 0,0,1,0,0,0,0',
1502 ]
1503 lst = [
1504 'sv.svstep./m=r3 2.v, 4, 0',
1505 'ternlogi 0,0,0,0x5',
1506 'fmvis 5,65535',
1507 'fmvis 5,1',
1508 'fmvis 5,32768',
1509 ]
1510 isa = SVP64Asm(lst, macros=macros)
1511 log("list", list(isa))
1512 asm_process()