1 from openpower
.simulator
.program
import Program
2 from openpower
.sv
.trans
.pysvp64dis
import load
, dump
3 from openpower
.sv
.trans
.svp64
import SVP64Asm
4 from openpower
.decoder
.power_insn
import Database
, Verbosity
5 from openpower
.decoder
.power_enums
import find_wiki_dir
6 from openpower
.sv
import sv_binutils_fptrans
10 class SVSTATETestCase(unittest
.TestCase
):
12 def _do_tst(self
, expected
):
13 isa
= SVP64Asm(expected
)
15 with
Program(lst
, bigendian
=False) as program
:
16 print ("ops", program
._instructions
)
17 program
.binfile
.seek(0)
18 insns
= load(program
.binfile
)
22 print ("insns", insns
)
23 for i
, line
in enumerate(dump(insns
, verbosity
=Verbosity
.SHORT
)):
24 name
= expected
[i
].split(" ")[0]
25 with self
.subTest("%d:%s" % (i
, name
)):
26 print("instruction", repr(line
), repr(expected
[i
]))
27 self
.assertEqual(expected
[i
], line
,
28 "instruction does not match "
29 "'%s' expected '%s'" % (line
, expected
[i
]))
33 expected
= ['addi 1,5,2',
39 self
._do
_tst
(expected
)
41 def test_1_svshape2(self
):
43 'svshape2 12,1,15,5,0,0'
45 self
._do
_tst
(expected
)
47 def test_2_d_custom_op(self
):
53 self
._do
_tst
(expected
)
55 def test_3_sv_isel(self
):
59 'sv.isel 12,2,3,*483',
63 self
._do
_tst
(expected
)
65 def test_4_sv_crand(self
):
67 'sv.crand *16,*2,*33',
70 self
._do
_tst
(expected
)
72 def test_5_setvl(self
):
77 self
._do
_tst
(expected
)
79 def test_6_sv_setvl(self
):
81 "sv.setvl 5,4,5,0,1,1",
82 "sv.setvl 63,35,5,0,1,1",
84 self
._do
_tst
(expected
)
86 def test_7_batch(self
):
87 "these come from https://bugs.libre-soc.org/show_bug.cgi?id=917#c25"
101 "sv.fmuls *32,*32,*40",
107 "sv.fmuls *32,*32,*40",
122 "sv.lfs *48,256(16)",
123 "sv.fmuls *40,*32,*40",
125 "sv.fmuls *32,*32,*48",
133 "sv.lfs *48,256(16)",
134 "sv.fmuls *40,*32,*40",
136 "sv.fmuls *32,*32,*48",
153 "sv.fmuls *32,*32,*40",
158 self
._do
_tst
(expected
)
160 def test_8_madd(self
):
166 self
._do
_tst
(expected
)
168 def test_9_fptrans(self
):
169 "enumerates a list of fptrans instruction disassembly entries"
170 db
= Database(find_wiki_dir())
171 entries
= sorted(sv_binutils_fptrans
.collect(db
))
172 dis
= lambda entry
: sv_binutils_fptrans
.dis(entry
, binutils
=False)
173 self
._do
_tst
(list(map(dis
, entries
)))
175 def test_10_vec(self
):
177 "sv.add./vec2 *3,*7,*11",
178 "sv.add./vec3 *3,*7,*11",
179 "sv.add./vec4 *3,*7,*11",
181 self
._do
_tst
(expected
)
183 def test_11_elwidth(self
):
185 "sv.add./dw=8 *3,*7,*11",
186 "sv.add./dw=16 *3,*7,*11",
187 "sv.add./dw=32 *3,*7,*11",
188 "sv.add./sw=8 *3,*7,*11",
189 "sv.add./sw=16 *3,*7,*11",
190 "sv.add./sw=32 *3,*7,*11",
191 "sv.add./dw=8/sw=16 *3,*7,*11",
192 "sv.add./dw=16/sw=32 *3,*7,*11",
193 "sv.add./dw=32/sw=8 *3,*7,*11",
194 "sv.add./w=32 *3,*7,*11",
195 "sv.add./w=8 *3,*7,*11",
196 "sv.add./w=16 *3,*7,*11",
198 self
._do
_tst
(expected
)
200 def test_12_sat(self
):
202 "sv.add./satu *3,*7,*11",
203 "sv.add./sats *3,*7,*11",
205 self
._do
_tst
(expected
)
207 def test_12_mr_r(self
):
209 "sv.add./mrr/vec2 *3,*7,*11",
210 "sv.add./mr/vec2 *3,*7,*11",
211 "sv.add./mrr *3,*7,*11",
212 "sv.add./mr *3,*7,*11",
214 self
._do
_tst
(expected
)
216 def test_13_RC1(self
):
218 "sv.add/ff=RC1 *3,*7,*11",
219 "sv.add/pr=RC1 *3,*7,*11",
220 "sv.add/ff=~RC1 *3,*7,*11",
221 "sv.add/pr=~RC1 *3,*7,*11",
223 self
._do
_tst
(expected
)
225 def test_14_rc1_ff_pr(self
):
227 "sv.add./ff=eq *3,*7,*11",
228 "sv.add./ff=ns *3,*7,*11",
229 "sv.add./pr=eq *3,*7,*11",
230 "sv.add./pr=ns *3,*7,*11",
232 self
._do
_tst
(expected
)
234 def test_15_predicates(self
):
236 "sv.add./m=r3 *3,*7,*11",
237 "sv.add./m=1<<r3 *3,*7,*11",
238 "sv.add./m=~r10 *3,*7,*11",
239 "sv.add./m=so *3,*7,*11",
240 "sv.add./m=ne *3,*7,*11",
241 "sv.add./m=lt *3,*7,*11",
243 "sv.extsw/m=r30 3,7",
244 "sv.extsw/sm=r30/dm=~r30 3,7",
245 "sv.extsw/sm=gt/dm=eq 3,7",
246 "sv.extsw/sm=~r3 3,7",
247 "sv.extsw/dm=r30 3,7",
249 self
._do
_tst
(expected
)
251 def test_15_els(self
):
253 "sv.stw/els *4,16(2)",
254 "sv.lfs/els *1,256(4)",
256 self
._do
_tst
(expected
)
258 def test_16_bc(self
):
260 "sv.bc/all 12,*1,0xc",
261 "sv.bc/snz 12,*1,0xc",
262 "sv.bc/all/sl/slu 12,*1,0xc",
263 "sv.bc/all/snz/sl/slu/lru 12,*1,0xc",
265 self
._do
_tst
(expected
)
267 if __name__
== "__main__":