src/openpower/sv/trans/test_pysvp64dis.py

   1 from openpower.simulator.program import Program
   2 from openpower.sv.trans.pysvp64dis import load, dump
   3 from openpower.sv.trans.svp64 import SVP64Asm
   4 from openpower.decoder.power_insn import Database, Verbosity
   5 from openpower.decoder.power_enums import find_wiki_dir
   6 from openpower.sv import sv_binutils_fptrans
   7 import unittest
   8 import sys
   9
  10 class SVSTATETestCase(unittest.TestCase):
  11
  12     def _do_tst(self, expected):
  13         isa = SVP64Asm(expected)
  14         lst = list(isa)
  15         with Program(lst, bigendian=False) as program:
  16             print ("ops", program._instructions)
  17             program.binfile.seek(0)
  18             insns = load(program.binfile)
  19             #for insn in insns:
  20                 #print ("insn", insn)
  21             insns = list(insns)
  22             print ("insns", insns)
  23             for i, line in enumerate(dump(insns, verbosity=Verbosity.SHORT)):
  24                 name = expected[i].split(" ")[0]
  25                 with self.subTest("%d:%s" % (i, name)):
  26                     print("instruction", repr(line), repr(expected[i]))
  27                     self.assertEqual(expected[i], line,
  28                                      "instruction does not match "
  29                                      "'%s' expected '%s'" % (line, expected[i]))
  30
  31
  32     def test_0_add(self):
  33         expected = ['addi 1,5,2',
  34                     'add 1,5,2',
  35                     'add. 1,5,2',
  36                     'addo 1,5,2',
  37                     'addo. 1,5,2',
  38                         ]
  39         self._do_tst(expected)
  40
  41     def test_1_svshape2(self):
  42         expected = [
  43                     'svshape2 12,1,15,5,0,0'
  44                         ]
  45         self._do_tst(expected)
  46
  47     def test_2_d_custom_op(self):
  48         expected = [
  49                     'fishmv 12,2',
  50                     'fmvis 12,97',
  51                     'addpcis 12,5',
  52                         ]
  53         self._do_tst(expected)
  54
  55     def test_3_sv_isel(self):
  56         expected = [
  57                     'sv.isel 12,2,3,33',
  58                     'sv.isel 12,2,3,*33',
  59                     'sv.isel 12,2,3,*483',
  60                     'sv.isel 12,2,3,63',
  61                     'sv.isel 12,2,3,*99',
  62                         ]
  63         self._do_tst(expected)
  64
  65     def test_4_sv_crand(self):
  66         expected = [
  67                     'sv.crand *16,*2,*33',
  68                     'sv.crand 12,2,33',
  69                         ]
  70         self._do_tst(expected)
  71
  72     def test_5_setvl(self):
  73         expected = [
  74                     "setvl 5,4,5,0,1,1",
  75                     "setvl. 5,4,5,0,1,1",
  76                         ]
  77         self._do_tst(expected)
  78
  79     def test_6_sv_setvl(self):
  80         expected = [
  81                     "sv.setvl 5,4,5,0,1,1",
  82                     "sv.setvl 63,35,5,0,1,1",
  83                         ]
  84         self._do_tst(expected)
  85
  86     def test_7_batch(self):
  87         "these come from https://bugs.libre-soc.org/show_bug.cgi?id=917#c25"
  88         expected = [
  89                     "addi 2,2,0",
  90                     "addis 9,2,0",
  91                     "addi 9,9,0",
  92                     "rlwinm 7,7,2,0,29",
  93                     "mulli 0,7,31",
  94                     "add 10,6,0",
  95                     "setvl 0,0,8,1,1,0",
  96                     "addi 16,4,124",
  97                     "lfiwax 0,0,5",
  98                     "addi 5,3,64",
  99                     "sv.lfs *32,256(4)",
 100                     "sv.lfs *40,256(5)",
 101                     "sv.fmuls *32,*32,*40",
 102                     "sv.fadds 0,*32,0",
 103                     "addi 5,3,192",
 104                     "addi 4,4,128",
 105                     "sv.lfs *32,256(4)",
 106                     "sv.lfs *40,256(5)",
 107                     "sv.fmuls *32,*32,*40",
 108                     "sv.fsubs 0,0,*32",
 109                     "addi 4,4,-128",
 110                     "stfs 0,0(6)",
 111                     "add 6,6,7",
 112                     "addi 4,4,4",
 113                     "addi 0,0,15",
 114                     "mtspr 288,0",
 115                     "addi 8,0,4",
 116                     "lfiwax 0,0,9",
 117                     "lfiwax 1,0,9",
 118                     "addi 5,3,64",
 119                     "add 5,5,8",
 120                     "sv.lfs *32,256(5)",
 121                     "sv.lfs *40,256(4)",
 122                     "sv.lfs *48,256(16)",
 123                     "sv.fmuls *40,*32,*40",
 124                     "sv.fadds 0,0,*40",
 125                     "sv.fmuls *32,*32,*48",
 126                     "sv.fsubs 1,1,*32",
 127                     "addi 5,3,192",
 128                     "subf 5,8,5",
 129                     "addi 4,4,128",
 130                     "addi 16,16,128",
 131                     "sv.lfs *32,256(5)",
 132                     "sv.lfs *40,256(4)",
 133                     "sv.lfs *48,256(16)",
 134                     "sv.fmuls *40,*32,*40",
 135                     "sv.fsubs 0,0,*40",
 136                     "sv.fmuls *32,*32,*48",
 137                     "sv.fsubs 1,1,*32",
 138                     "addi 4,4,-128",
 139                     "addi 16,16,-128",
 140                     "stfs 0,0(6)",
 141                     "add 6,6,7",
 142                     "stfs 1,0(10)",
 143                     "subf 10,7,10",
 144                     "addi 8,8,4",
 145                     "addi 4,4,4",
 146                     "addi 16,16,-4",
 147                     "bc 16,0,-0xb4",
 148                     "addi 5,3,128",
 149                     "addi 4,4,128",
 150                     "lfiwax 0,0,9",
 151                     "sv.lfs *32,256(4)",
 152                     "sv.lfs *40,256(5)",
 153                     "sv.fmuls *32,*32,*40",
 154                     "sv.fsubs 0,0,*32",
 155                     "stfs 0,0(6)",
 156                     "bclr 20,0,0",
 157                         ]
 158         self._do_tst(expected)
 159
 160     def test_8_madd(self):
 161         expected = [
 162                     "maddhd 5,4,5,3",
 163                     "maddhdu 5,4,5,3",
 164                     "maddld 5,4,5,3",
 165                         ]
 166         self._do_tst(expected)
 167
 168     def test_9_fptrans(self):
 169         "enumerates a list of fptrans instruction disassembly entries"
 170         db = Database(find_wiki_dir())
 171         entries = sorted(sv_binutils_fptrans.collect(db))
 172         dis = lambda entry: sv_binutils_fptrans.dis(entry, binutils=False)
 173         self._do_tst(list(map(dis, entries)))
 174
 175     def test_10_vec(self):
 176         expected = [
 177                     "sv.add./vec2 *3,*7,*11",
 178                     "sv.add./vec3 *3,*7,*11",
 179                     "sv.add./vec4 *3,*7,*11",
 180                         ]
 181         self._do_tst(expected)
 182
 183     def test_11_elwidth(self):
 184         expected = [
 185                     "sv.add./dw=8 *3,*7,*11",
 186                     "sv.add./dw=16 *3,*7,*11",
 187                     "sv.add./dw=32 *3,*7,*11",
 188                     "sv.add./sw=8 *3,*7,*11",
 189                     "sv.add./sw=16 *3,*7,*11",
 190                     "sv.add./sw=32 *3,*7,*11",
 191                     "sv.add./dw=8/sw=16 *3,*7,*11",
 192                     "sv.add./dw=16/sw=32 *3,*7,*11",
 193                     "sv.add./dw=32/sw=8 *3,*7,*11",
 194                     "sv.add./w=32 *3,*7,*11",
 195                     "sv.add./w=8 *3,*7,*11",
 196                     "sv.add./w=16 *3,*7,*11",
 197                         ]
 198         self._do_tst(expected)
 199
 200     def test_12_sat(self):
 201         expected = [
 202                     "sv.add./satu *3,*7,*11",
 203                     "sv.add./sats *3,*7,*11",
 204                         ]
 205         self._do_tst(expected)
 206
 207     def test_12_mr_r(self):
 208         expected = [
 209                     "sv.add./mrr/vec2 *3,*7,*11",
 210                     "sv.add./mr/vec2 *3,*7,*11",
 211                     "sv.add./mrr *3,*7,*11",
 212                     "sv.add./mr *3,*7,*11",
 213                         ]
 214         self._do_tst(expected)
 215
 216 if __name__ == "__main__":
 217     unittest.main()
 218